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CN101740539B - Four-square plane non-guide pin package unit and its manufacturing method and its lead frame - Google Patents

Four-square plane non-guide pin package unit and its manufacturing method and its lead frame Download PDF

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Publication number
CN101740539B
CN101740539B CN200810175561XA CN200810175561A CN101740539B CN 101740539 B CN101740539 B CN 101740539B CN 200810175561X A CN200810175561X A CN 200810175561XA CN 200810175561 A CN200810175561 A CN 200810175561A CN 101740539 B CN101740539 B CN 101740539B
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pins
chip
lead frame
package unit
concave portion
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CN101740539A (en
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李春源
洪孝仁
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A quad flat non-leaded package unit comprising: the lead frame comprises a chip seat and a plurality of pins, wherein the chip seat and the plurality of pins are respectively provided with a first surface and an opposite second surface; the active surface of the chip is provided with a plurality of welding pads, and the inactive surface of the chip is connected with the chip seat; a plurality of wires electrically connected to the chip and the pins respectively; the packaging colloid coats the chip, the lead and the lead frame, but the chip seat and the second surfaces of the plurality of pins are exposed; the pins at the outermost periphery of the lead frame are provided with extending parts and opposite concave parts, so that when the packaging unit is subjected to reflow soldering, the concave parts accommodate solder, and the bonding in the horizontal and vertical directions is provided to increase the bonding area, thereby having the advantage of improving the bonding strength of the packaging unit.

Description

四方平面无导脚封装单元及其制法和其导线架Four-square plane non-guide pin package unit and its manufacturing method and its lead frame

技术领域 technical field

本发明涉及一种四方平面无导脚封装单元,尤指一种具有增强焊料结合强度的接脚的四方平面无导脚封装单元。The invention relates to a package unit without pins in a square plane, in particular to a package unit without pins in a square plane with pins that enhance the bonding strength of solder.

背景技术 Background technique

四方平面无导脚封装单元为一种使芯片座和接脚底面外露于封装胶体底部表面的封装单元,一般采用表面耦接技术将封装单元耦接至印刷电路板上,由此形成一特定功能的电路模块。在表面耦接工序中,四方平面无导脚封装单元的芯片座和接脚为直接焊接至印刷电路板上。The quadrilateral planar pinless package unit is a package unit in which the chip base and the bottom surface of the pins are exposed on the bottom surface of the encapsulant. Generally, the surface coupling technology is used to couple the package unit to the printed circuit board, thereby forming a specific function. circuit modules. In the surface coupling process, the die paddle and pins of the quad planar leadless package unit are directly soldered to the printed circuit board.

举例而言,第6,201,292和7,049,177号美国专利揭露一种现有的四方平面无导脚封装单元,以下配合图1,说明现有的四方平面无导脚封装单元至印刷电路板的耦接方法。For example, US Pat. Nos. 6,201,292 and 7,049,177 disclose a conventional quadrilateral planar leadless package unit. The coupling method of the conventional quadrilateral planar leadless package unit to a printed circuit board is described below with reference to FIG. 1 .

现有的四方平面无导脚封装单元100,包括以下构件:(a)导线架110,具有芯片座111和多个接脚113,该芯片座111和该多个接脚113分别具有第一表面120和相对的第二表面130;(b)芯片140,具有主动面150和相对的非主动面160,该主动面150上具有多个焊垫151,其中,该芯片140的非主动面160接置于该芯片座111的第一表面120上;(c)多个导线170,分别电性连接所述焊垫151和所述接脚113,且所述导线170接合于所述接脚113的第一表面120;以及(d)封装胶体180,包覆该芯片140、所述导线170和该导线架110,但使该芯片座111和该多个接脚113的第二表面130显露于外;其中,该芯片座111的第二表面130与该接脚113的第二表面130呈现一平面。The existing quadrilateral planar leadless package unit 100 includes the following components: (a) lead frame 110, which has a chip base 111 and a plurality of pins 113, and the chip base 111 and the plurality of pins 113 respectively have a first surface 120 and the opposite second surface 130; (b) chip 140 has an active surface 150 and an opposite non-active surface 160, with a plurality of solder pads 151 on the active surface 150, wherein the non-active surface 160 of the chip 140 is connected to Placed on the first surface 120 of the chip holder 111; (c) a plurality of wires 170 electrically connected to the pads 151 and the pins 113 respectively, and the wires 170 are bonded to the pins 113 The first surface 120; and (d) encapsulant 180, covering the chip 140, the lead 170 and the lead frame 110, but exposing the second surface 130 of the chip base 111 and the plurality of pins 113 to the outside ; Wherein, the second surface 130 of the die holder 111 and the second surface 130 of the pin 113 present a plane.

印刷电路板190包括一基板191、接地部193、以及多个导电部195。接地部193用以作为四方平面无导脚封装单元100的芯片座111的安置区域,其面积大致等于芯片座的面积;而导电部195则作为印刷电路板190上的电性连接点,其面积大致等于四方平面无导脚封装单元上的各个接脚的外露表面的面积。The printed circuit board 190 includes a substrate 191 , a ground portion 193 , and a plurality of conductive portions 195 . The grounding part 193 is used as a placement area for the chip holder 111 of the square planar leadless package unit 100, and its area is approximately equal to the area of the chip holder; and the conductive part 195 is used as an electrical connection point on the printed circuit board 190, and its area It is approximately equal to the area of the exposed surface of each pin on the quadrilateral planar leadless package unit.

接着,进行涂焊程序,藉以将焊料197涂布于接地部193和各个导电部195的表面上。之后再进行表面耦接程序,将四方平面无导脚封装单元100安置于印刷电路板190上,并使各个接脚113和芯片座111分别对齐至对应的导电部195和接地部193。Next, a solder coating process is performed, so that the solder 197 is coated on the surface of the ground portion 193 and each conductive portion 195 . Afterwards, the surface coupling procedure is performed to place the quadrilateral planar leadless package unit 100 on the printed circuit board 190 , and align each pin 113 and chip holder 111 to the corresponding conductive portion 195 and ground portion 193 respectively.

最后,进行一回焊程序(solder-reflow process),藉以将焊料回焊于各个接脚和导电部之间以及芯片座和接地部之间,这样就完成了四方平面无导脚封装单元至印刷电路板的耦接工序。Finally, a reflow process (solder-reflow process) is carried out, so as to reflow the solder between each pin and the conductive part and between the chip base and the ground part, thus completing the quadrangular planar leadless package unit to the printed circuit board. Circuit board coupling process.

然而,由于在回焊工序中,熔化的焊料会向中心聚缩,因此会使回焊后的焊料略为向上隆起,使得结合面积变小,且由于该芯片座的第二表面与该接脚的第二表面皆为平坦表面,该仅有的平面结合亦使得焊料结合强度较差,因而产生可靠度不佳的问题。However, during the reflow process, the melted solder will shrink towards the center, so the reflowed solder will slightly bulge upwards, so that the bonding area becomes smaller, and because the second surface of the chip base and the pin The second surfaces are all flat surfaces, and the only planar combination also makes the bonding strength of the solder poor, thus causing the problem of poor reliability.

因此,如何解决上述现有焊料结合强度较差所产生的问题,并开发一种新颖的四方平面无导脚封装单元,实为目前急欲解决的课题。Therefore, how to solve the above-mentioned problems caused by the poor bonding strength of the existing solders and develop a novel quadrangular planar leadless package unit is an urgent subject to be solved at present.

发明内容 Contents of the invention

鉴于以上所述背景技术的缺点,本发明提供一种接脚底面具有凹部的四方平面无导脚封装单元,以提高水平方向和垂直方向的焊料结合强度。In view of the disadvantages of the above-mentioned background technology, the present invention provides a quadrangular planar leadless package unit with recesses on the bottom surface of the leads, so as to improve the solder bonding strength in the horizontal direction and the vertical direction.

本发明所揭露一种四方平面无导脚封装单元,包括:(a)导线架,包括芯片座和多个接脚,该芯片座和该多个接脚分别具有第一表面和相对的第二表面;(b)芯片,具有主动面和相对的非主动面,该主动面上具有多个焊垫,其中,该芯片的非主动面接置于该芯片座的第一表面上;(c)多个导线,分别电性连接所述焊垫和所述接脚,且所述导线接合于所述接脚的第一表面;以及(d)封装胶体,包覆该芯片、所述导线和该导线架,但使该芯片座和该多个接脚的第二表面显露于外;其中,该导线架最外围的接脚的第一表面处形成有延伸部,并向远离第一表面的方向延伸,且相对的第二表面形成有凹部,用以在该四方平面无导脚封装单元进行回焊时,使该凹部容纳焊料。The present invention discloses a quadrangular planar leadless package unit, comprising: (a) a lead frame including a chip seat and a plurality of pins, the chip seat and the plurality of pins respectively have a first surface and an opposite second surface surface; (b) a chip having an active surface and an opposite non-active surface, the active surface has a plurality of pads, wherein the non-active surface of the chip is placed on the first surface of the chip holder; (c) multiple a wire electrically connected to the pad and the pin respectively, and the wire is bonded to the first surface of the pin; and (d) an encapsulant covering the chip, the wire and the wire frame, but the second surface of the chip base and the plurality of pins are exposed; wherein, the first surface of the outermost pins of the lead frame is formed with an extension, and extends away from the first surface , and the opposite second surface is formed with a concave portion, which is used to make the concave portion accommodate solder when the quadrilateral planar leadless package unit is reflowed.

本发明还揭露一种制作四方平面无导脚封装单元的方法,包括:提供载板,该载板包括定义于该载板表面的多个切割线、形成于该切割线上的多个凸块、以及该多个凸块所围绕的平坦部;在该具有凸块的载板表面上形成金属层后,图案化该金属层以得到导线架,该导线架具有形成于该平坦部上的具有第一表面和相对的第二表面的芯片座和多个接脚,其中,部分的接脚形成于该凸块处并包覆该凸块,而形成于该凸块处的接脚具有延伸部和凹部;接着将芯片接合于该芯片座上;再形成多个导线,以电性连接芯片与接脚;形成封装胶体于该载板上,以包覆该接脚、芯片座、芯片和导线;移除该载板,使外露出该导线架;以及沿着所述切割线切割分离以得到多个四方平面无导脚封装单元。The present invention also discloses a method for manufacturing a quadrilateral planar leadless package unit, including: providing a carrier board, the carrier board includes a plurality of cutting lines defined on the surface of the carrier board, and a plurality of bumps formed on the cutting lines , and the flat portion surrounded by the plurality of bumps; after forming a metal layer on the surface of the carrier with bumps, the metal layer is patterned to obtain a lead frame, and the lead frame has a lead frame formed on the flat portion The first surface and the opposite second surface have a chip seat and a plurality of pins, wherein some of the pins are formed at the bump and cover the bump, and the pins formed at the bump have extensions and the concave portion; then the chip is bonded on the chip holder; then a plurality of wires are formed to electrically connect the chip and the pins; an encapsulant is formed on the carrier board to cover the pins, the chip holder, the chip and the wires ; removing the carrier board to expose the lead frame; and cutting and separating along the cutting line to obtain a plurality of quadrangular planar leadless package units.

本发明另揭露一种四方平面无导脚的导线架,包括:芯片座;以及多个围绕该芯片座的接脚,该芯片座和该多个接脚分别具有第一表面和相对的第二表面;其中,该导线架最外围的接脚的第一表面处形成有延伸部,并向远离第一表面的方向延伸,且相对的第二表面形成有凹部,用以容纳焊料。The present invention also discloses a lead frame with no guide pins on a square plane, comprising: a chip seat; and a plurality of pins surrounding the chip seat, the chip seat and the plurality of pins respectively have a first surface and an opposite second surface surface; wherein, an extension part is formed on the first surface of the outermost pin of the lead frame, and extends away from the first surface, and a concave part is formed on the opposite second surface to accommodate solder.

以下结合上述技术方案,说明本发明的有益效果。本发明通过形成于接脚的第二表面的凹部,利用该凹部于该四方平面无导脚封装单元进行回焊时容纳焊料,提供了水平和垂直方向上的结合,并增加了粘合的面积,从而提高焊料结合强度。The beneficial effects of the present invention will be described below in combination with the above technical solutions. The present invention utilizes the concave portion formed on the second surface of the pin to accommodate the solder when the quadrilateral plane leadless package unit is reflowed, provides bonding in the horizontal and vertical directions, and increases the bonding area , thereby improving the solder bonding strength.

附图说明 Description of drawings

图1为现有的四方平面无导脚封装单元的剖面示意图;FIG. 1 is a schematic cross-sectional view of an existing four-square planar package unit without leads;

图2A至图2G为本发明的四方平面无导脚封装单元及其制法的剖面示意图;2A to FIG. 2G are schematic cross-sectional views of the quadrangular planar pinless package unit and its manufacturing method of the present invention;

图2A’为显示形成于载板上的导线架的剖面示意图;2A' is a schematic cross-sectional view showing a lead frame formed on a carrier;

图2A”为显示另一形成于载板上的导线架的剖面示意图;2A" is a schematic cross-sectional view showing another lead frame formed on a carrier;

图3A为本发明另一四方平面无导脚封装单元的剖面示意图;以及3A is a schematic cross-sectional view of another quadrangular planar leadless package unit of the present invention; and

图3B至图3D为显示本发明的形成于芯片座第二表面的凹部示意图。3B to 3D are schematic diagrams showing the concave portion formed on the second surface of the die holder according to the present invention.

【主要元件符号说明】[Description of main component symbols]

100、200  四方平面无导脚封装单元100, 200 square planar lead-free package unit

110、210  导线架110, 210 lead frame

111、211  芯片座111, 211 chip holder

113、213  接脚113, 213 pins

120、220  第一表面120, 220 first surface

130、230  第二表面130, 230 second surface

140、240  芯片140, 240 chips

150、250  主动面150, 250 active face

151、251  焊垫151, 251 welding pad

160、260  非主动面160, 260 non-active surface

170、270  导线170, 270 wire

180、280  封装胶体180, 280 encapsulation colloid

190、290  印刷电路板190, 290 printed circuit board

191       基板191 Substrate

193、293  接地部193, 293 Grounding part

195、295  导电部195, 295 Conductive part

197、297  焊料197, 297 Solder

212       载板212 carrier board

214       表面214 Surface

216       矩阵封胶区216 Matrix sealing area

218       切割线218 cutting line

219       矩阵单元219 matrix unit

221       平坦部221 flat part

223       凸块223 bump

225       延伸部225 extension

227       凹部227 concave part

241       胶粘剂241 Adhesive

具体实施方式 Detailed ways

以下通过特定的具体实施例说明本发明的实施方式,所属技术领域的普通技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。The implementation of the present invention is described below through specific specific examples, and those of ordinary skill in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

第一实施例first embodiment

请参阅图2A至图2G,为本发明的四方平面无导脚封装单元及其制法的示意图。Please refer to FIG. 2A to FIG. 2G , which are schematic diagrams of the quadrilateral planar leadless package unit and its manufacturing method of the present invention.

如图2A所示,提供一载板212,载板212的材料可为(但不限于)例如铜等金属材料。该载板212的表面214包括一矩阵封胶区216,该矩阵封胶区216定义有多个切割线218和矩阵单元219。As shown in FIG. 2A , a carrier 212 is provided, and the material of the carrier 212 can be (but not limited to) a metal material such as copper. The surface 214 of the carrier 212 includes a matrix sealing area 216 , and the matrix sealing area 216 defines a plurality of cutting lines 218 and matrix units 219 .

再参阅图2A’,该载板212每一矩阵单元219具有平坦部221和多个凸块223形成于该切割线218上并环绕该平坦部221,所述凸块223环绕该平坦部221所得的面积大致等于一四方平面无导脚封装单元200的面积;接着,在该载板212上利用电镀和图案化工艺技术形成图案化的金属层,金属层具有,例如金/钯/镍/钯层或金/镍/铜/钯层,并以该图案化金属层作为导线架210,该导线架210具有芯片座211和多个接脚213,其中,该芯片座211形成于该平坦部221上且芯片座211的面积大致等于芯片的面积;部分的接脚213形成于该芯片座211和该凸块223之间以及部分的接脚213形成于该凸块223处并包覆该凸块223,因此,相对于该凸块,形成于该凸块223处的接脚213具有延伸部225和凹部227。2A', each matrix unit 219 of the carrier 212 has a flat portion 221 and a plurality of bumps 223 are formed on the cutting line 218 and surround the flat portion 221, and the bumps 223 surround the flat portion 221 to obtain The area is approximately equal to the area of a quadrangular plane leadless package unit 200; then, a patterned metal layer is formed on the carrier board 212 using electroplating and patterning techniques, and the metal layer has, for example, gold/palladium/nickel/ A palladium layer or a gold/nickel/copper/palladium layer, and the patterned metal layer is used as a lead frame 210, the lead frame 210 has a chip holder 211 and a plurality of pins 213, wherein the chip holder 211 is formed on the flat portion 221 and the area of the chip seat 211 is approximately equal to the area of the chip; part of the pin 213 is formed between the chip seat 211 and the bump 223 and part of the pin 213 is formed at the bump 223 and covers the bump Block 223 , therefore, relative to the bump, the pin 213 formed at the bump 223 has an extension 225 and a recess 227 .

或者,如图2A”所示,载板每一矩阵单元219的切割线218内侧也具有环绕该平坦部221的凸块223,因此,该平坦部221的面积较图2A’所示的面积要小。Or, as shown in FIG. 2A ", the inner side of the cutting line 218 of each matrix unit 219 of the substrate also has a bump 223 surrounding the flat portion 221. Therefore, the area of the flat portion 221 is larger than that shown in FIG. 2A' Small.

具体而言,参照图2A’,本发明所揭露的四方平面无导脚的导线架210,包括:芯片座211;以及多个围绕该芯片座211的接脚213,该芯片座211和该多个接脚213分别具有第一表面220和相对的第二表面230;其中,该导线架210最外围的接脚213的第一表面220处形成有延伸部225,并向远离第一表面220的方向延伸,且相对的第二表面230形成有凹部227,用以容纳焊料。Specifically, referring to FIG. 2A', the lead frame 210 disclosed in the present invention includes: a chip holder 211; and a plurality of pins 213 surrounding the chip holder 211; Each pin 213 respectively has a first surface 220 and an opposite second surface 230; wherein, an extension 225 is formed on the first surface 220 of the outermost pin 213 of the lead frame 210, and extends away from the first surface 220. The direction extends, and the opposite second surface 230 is formed with a recess 227 for accommodating solder.

同样地,根据图2A”所示,该导线架的全部接脚的第一表面处可形成有延伸部,并向远离第一表面的方向延伸,且相对的第二表面形成有凹部。另外,该导线架的芯片座的第二表面可还形成有凹部,用以在该四方平面无导脚封装单元进行回焊时,使该凹部容纳焊料。Similarly, as shown in FIG. 2A ″, extensions may be formed on the first surface of all the pins of the lead frame, extending in a direction away from the first surface, and recesses are formed on the opposite second surface. In addition, The second surface of the chip holder of the lead frame may further form a concave portion, which is used for allowing the concave portion to accommodate solder when the quadrilateral planar leadless package unit is reflowed.

如图2B所示,执行粘晶步骤,提供主动面250上具有多个焊垫251的芯片240,并通过胶粘剂241使芯片240的相对该主动面250的非主动面260接合该芯片座211。本发明中,胶粘剂的实例包括(但不限于)银胶。As shown in FIG. 2B , a die bonding step is performed to provide a chip 240 with a plurality of bonding pads 251 on the active surface 250 , and the non-active surface 260 of the chip 240 opposite to the active surface 250 is bonded to the chip holder 211 through an adhesive 241 . In the present invention, examples of the adhesive include, but are not limited to, silver paste.

如图2C所示,执行芯片与接脚的电性连接步骤,其利用打线(wire-bonding)的方式形成多个导线270,所述导线270电性连接芯片240的焊垫251与接脚213。As shown in FIG. 2C , the step of electrically connecting the chip and the pins is performed, and a plurality of wires 270 are formed by way of wire-bonding, and the wires 270 are electrically connected to the pads 251 of the chip 240 and the pins. 213.

如图2D所示,执行一封胶步骤,其利用压模或涂胶的方式形成封装胶体,封装胶体280形成于该载板212上,以包覆该接脚213、芯片座211、芯片240和导线270。As shown in FIG. 2D , an encapsulation step is performed, which forms an encapsulant by means of molding or gluing, and the encapsulant 280 is formed on the carrier 212 to cover the pins 213, the chip holder 211, and the chip 240. and wire 270 .

如图2E所示,执行一如湿式蚀刻的蚀刻步骤,以移除该载板,从而显露出该导线架210的底面261和封装胶体280的底面261,且由于移除该具有凸块的载板,先前形成于该凸块处的接脚213相对地具有凹部227。As shown in FIG. 2E, an etching step such as wet etching is performed to remove the carrier, thereby exposing the bottom surface 261 of the lead frame 210 and the bottom surface 261 of the encapsulant 280, and since the carrier with bumps is removed Board, the pin 213 previously formed at the bump has a recess 227 opposite.

如图2F所示,接着进行切割的步骤,其沿着所述切割线218切割分离每一个矩阵单元,以得到本发明的四方平面无导脚封装单元200。As shown in FIG. 2F , a dicing step is performed next, wherein each matrix unit is diced and separated along the dicing line 218 to obtain the quadrangular planar leadless package unit 200 of the present invention.

通过前述制法,本发明还揭示一种四方平面无导脚封装单元200,包括:导线架210,包括芯片座211和多个接脚213,该芯片座211和该多个接脚213分别具有第一表面220和相对的第二表面230;Through the foregoing manufacturing method, the present invention also discloses a quadrangular planar leadless package unit 200, comprising: a lead frame 210, including a chip holder 211 and a plurality of pins 213, and the chip holder 211 and the plurality of pins 213 respectively have a first surface 220 and an opposite second surface 230;

芯片240,具有主动面250和相对的非主动面260,该主动面250上具有多个焊垫251,其中,该芯片240的非主动面260接置于该芯片座211的第一表面220上;The chip 240 has an active surface 250 and an opposite non-active surface 260, and the active surface 250 has a plurality of bonding pads 251, wherein the non-active surface 260 of the chip 240 is connected to the first surface 220 of the chip holder 211 ;

多个导线270,分别电性连接所述焊垫251和所述接脚213,且所述导线270接合于所述接脚213的第一表面220;以及a plurality of wires 270 electrically connecting the pads 251 and the pins 213 respectively, and the wires 270 are bonded to the first surface 220 of the pins 213; and

封装胶体280,包覆该芯片240、所述导线270和该导线架210,但使该芯片座211和该多个接脚213的第二表面230显露于外;The encapsulant 280 covers the chip 240, the wires 270 and the lead frame 210, but exposes the second surface 230 of the chip holder 211 and the plurality of pins 213;

其中,该导线架210最外围的接脚213的第一表面220处形成有延伸部225,并向远离第一表面220的方向延伸,且相对的第二表面230形成有凹部227,用以在该四方平面无导脚封装单元200进行回焊时,使该凹部容纳焊料。更具体而言,所述最外围的接脚具有阶梯状结构,且该接脚的凹部位于该封装单元的外侧缘。Wherein, an extension portion 225 is formed on the first surface 220 of the outermost pin 213 of the lead frame 210 and extends away from the first surface 220, and a concave portion 227 is formed on the opposite second surface 230 for When the quadrilateral planar leadless package unit 200 is reflowed, the concave portion is made to accommodate solder. More specifically, the outermost pin has a stepped structure, and the concave portion of the pin is located on the outer edge of the packaging unit.

在本发明的另一具体实例中,全部接脚的第一表面处皆形成有延伸部,并向远离第一表面的方向延伸,且相对的第二表面形成有凹部。In another embodiment of the present invention, extensions are formed on the first surfaces of all the pins and extend in a direction away from the first surfaces, and recesses are formed on the opposite second surfaces.

如图2G所示,依序进行涂焊和回焊步骤,提供一印刷电路板290,该印刷电路板290具有预设的接地部293和导电部295,藉以将焊料297涂布于接地部293和各个导电部295的表面上,之后再将四方平面无导脚封装单元200安置于印刷电路板290上,并使各个接脚213和芯片座211分别对齐至对应的导电部295和接地部293。As shown in FIG. 2G, the soldering and reflow steps are performed in sequence to provide a printed circuit board 290, which has a predetermined ground portion 293 and a conductive portion 295, so that solder 297 is coated on the ground portion 293 and on the surface of each conductive portion 295, and then place the quadrilateral planar leadless package unit 200 on the printed circuit board 290, and align each pin 213 and chip holder 211 to the corresponding conductive portion 295 and ground portion 293 respectively .

最后,进行一回焊程序(solder-reflow process),藉以将焊料297回焊于各个接脚213和导电部295之间以及芯片座211和接地部293之间,这样就完成了本发明的四方平面无导脚封装单元200至印刷电路板290的耦接工序,此外,由于本发明的四方平面无导脚封装单元的具有凹部的接脚位于切割线上,因此在回焊之后,该焊料可包覆该封装单元侧边的接脚,从而提供更佳的结合强度。Finally, carry out a reflow process (solder-reflow process), whereby the solder 297 is reflowed between each pin 213 and the conductive part 295 and between the chip holder 211 and the ground part 293, thus completing the four sides of the present invention The coupling process of the planar leadless package unit 200 to the printed circuit board 290. In addition, since the pins with the concave portion of the quadrangular planar leadless package unit of the present invention are located on the cutting line, after reflow, the solder can The pins on the sides of the packaging unit are covered to provide better bonding strength.

因此,本发明的四方平面无导脚封装单元的接脚具有凹部,用以容纳焊料,进而提高水平和垂直方向的结合强度;再者,该接脚的第一表面处形成有延伸部,并向远离第一表面的方向延伸,因此本发明的接脚提供更多与封装胶体结合的面积,也加强了接脚与封装胶体的结合强度。Therefore, the pins of the quadrilateral planar leadless package unit of the present invention have recesses to accommodate solder, thereby improving the bonding strength in the horizontal and vertical directions; moreover, an extension is formed on the first surface of the pins, and Extending away from the first surface, the pins of the present invention provide more areas for bonding with the encapsulant, and also enhance the bonding strength between the pins and the encapsulant.

第二实施例second embodiment

请参阅图3A至图3D,为本发明的四方平面无导脚封装单元第二实施例的示意图。同时为简化本图,本实施例中对应前述相同或相似的元件均采用相同标号表示。Please refer to FIG. 3A to FIG. 3D , which are schematic diagrams of a second embodiment of the quadrangular planar leadless package unit of the present invention. At the same time, in order to simplify the figure, in this embodiment, the same or similar components as described above are represented by the same reference numerals.

本实施例的四方平面无导脚封装单元及其制法与前述实施例大致相同,主要差异在于该芯片座的第二表面还形成有凹部,用以在该四方平面无导脚封装单元进行回焊时,使该凹部容纳焊料。该芯片座的第二表面的凹部的形成方法,可视需要在移除该载板后,在该芯片座的第二表面形成有凹部。The quadrangular plane leadless package unit and its manufacturing method of the present embodiment are substantially the same as those of the foregoing embodiments, the main difference being that a recess is formed on the second surface of the chip base for returning to the square planar leadless package unit. When soldering, the recess is made to accommodate solder. The method for forming the concave portion on the second surface of the chip holder may optionally form a concave portion on the second surface of the chip holder after removing the carrier board.

如图3A所示,该芯片座211的凹部227形成于该芯片座211第二表面230的中央位置。As shown in FIG. 3A , the concave portion 227 of the die holder 211 is formed at the center of the second surface 230 of the die holder 211 .

此外,如图3B和图3C所示,该中央位置的凹部227为矩形或者该中央位置的凹部227为圆形。In addition, as shown in FIG. 3B and FIG. 3C , the concave portion 227 at the central position is rectangular or the concave portion 227 at the central position is circular.

如图3D所示,该芯片座211的凹部227也可形成于该芯片座211第二表面230的周边位置。As shown in FIG. 3D , the concave portion 227 of the die holder 211 can also be formed at the peripheral position of the second surface 230 of the die holder 211 .

另一方面,由图3A至图3D可知,本发明的四方平面无导脚的导线架所包括的芯片座的凹部可形成于该芯片座第二表面的中央位置,且该凹部的形状未有特别限制,因此该中央位置的凹部可为矩形或圆形。此外,该芯片座的凹部亦可形成于该芯片座第二表面的周边位置。On the other hand, it can be seen from FIG. 3A to FIG. 3D that the concave part of the chip holder included in the leadframe with no guide pin in the square plane of the present invention can be formed at the central position of the second surface of the chip holder, and the shape of the concave part has no difference. Particularly restrictive, the recess in this central position can therefore be rectangular or circular. In addition, the concave portion of the chip holder can also be formed on the peripheral position of the second surface of the chip holder.

本发明的四方平面无导脚封装单元通过形成于接脚的第二表面的凹部,利用该凹部在该四方平面无导脚封装单元进行回焊时容纳焊料,提供水平和垂直方向上的结合,并增加粘合的面积,此外,由于位于封装单元外侧缘的接脚向内形成有阶梯状结构,故可在回焊时使焊料包覆该外侧缘的接脚,更可提高封装单元结合强度。The quadrilateral planar leadless package unit of the present invention provides bonding in horizontal and vertical directions by using the recess formed on the second surface of the pin to accommodate solder when the quadrilateral planar leadless package unit is reflowed, And increase the bonding area. In addition, since the pins located on the outer edge of the package unit form a stepped structure inward, the solder can cover the pins on the outer edge during reflow, which can further improve the bonding strength of the package unit. .

以上所述的具体实施例,仅为用以例释本发明的特点及功效,而非用以限定本发明的可实施范畴,在未脱离本发明上述精神与技术范畴下,任何运用本发明所揭示内容而完成的等效改变及修饰,均仍应为所附的权利要求书范围所涵盖。The specific embodiments described above are only used to illustrate the characteristics and effects of the present invention, rather than to limit the scope of the present invention. Without departing from the spirit and technical scope of the present invention, any application of the present invention Equivalent changes and modifications accomplished through the disclosed content should still fall within the scope of the appended claims.

Claims (16)

1.一种四方平面无导脚封装单元,包括:1. A four-square planar package unit without guide pins, comprising: 导线架,包括芯片座和多个接脚,该芯片座和该多个接脚分别具有第一表面和相对的第二表面;a lead frame comprising a die pad and a plurality of pins, the die pad and the plurality of pins respectively having a first surface and an opposite second surface; 芯片,具有主动面和相对的非主动面,该主动面上具有多个焊垫,其中,该芯片的非主动面接置于该芯片座的第一表面上;A chip has an active surface and an opposite non-active surface, the active surface has a plurality of pads, wherein the non-active surface of the chip is placed on the first surface of the chip holder; 多个导线,分别电性连接所述焊垫和所述接脚,且所述导线接合于所述接脚的第一表面;以及a plurality of wires electrically connected to the pads and the pins respectively, and the wires are bonded to the first surface of the pins; and 封装胶体,包覆该芯片、所述导线和该导线架,但使该芯片座和该多个接脚的第二表面显露于外;an encapsulant covering the chip, the wires and the lead frame, but exposing the second surface of the chip holder and the plurality of pins; 其特征在于,该导线架最外围的接脚的第一表面处形成有延伸部,并向远离第一表面的方向延伸,且相对的第二表面形成有凹部,用以在该四方平面无导脚封装单元进行回焊时,使该凹部容纳焊料。It is characterized in that an extension part is formed on the first surface of the outermost pin of the lead frame, and extends away from the first surface, and a concave part is formed on the opposite second surface, so that there is no guide on the square plane. When the foot package unit is reflowed, the recess is made to accommodate solder. 2.根据权利要求1所述的四方平面无导脚封装单元,其特征在于,该最外围的接脚具有阶梯状结构,且该接脚的凹部位于该封装单元的外侧缘。2 . The quadrilateral planar leadless package unit according to claim 1 , wherein the outermost pin has a stepped structure, and the concave portion of the pin is located at the outer edge of the package unit. 3 . 3.根据权利要求1所述的四方平面无导脚封装单元,其特征在于,全部的该接脚的第一表面处形成有延伸部,并向远离第一表面的方向延伸,且相对的第二表面形成有凹部。3. The quadrilateral planar leadless package unit according to claim 1, wherein all the pins are formed with extensions on the first surface, and extend in a direction away from the first surface, and the opposite second Concaves are formed on the two surfaces. 4.根据权利要求1所述的四方平面无导脚封装单元,其特征在于,该芯片座的第二表面还形成有凹部,用以在该四方平面无导脚封装单元进行回焊时,使该芯片座的第二表面形成的该凹部容纳焊料。4. The quadrilateral planar leadless package unit according to claim 1, wherein the second surface of the chip holder is further formed with a concave portion for reflowing the quadrilateral planar leadless package unit. The recess formed by the second surface of the die paddle accommodates solder. 5.根据权利要求4所述的四方平面无导脚封装单元,其特征在于,该芯片座的凹部形成于该芯片座第二表面的中央位置。5 . The quadrilateral planar leadless package unit according to claim 4 , wherein the concave portion of the die holder is formed at the center of the second surface of the die holder. 5 . 6.根据权利要求4所述的四方平面无导脚封装单元,其特征在于,该芯片座的凹部形成于该芯片座第二表面的周边位置。6 . The quadrilateral planar leadless package unit according to claim 4 , wherein the concave portion of the die holder is formed at a peripheral position of the second surface of the die holder. 7 . 7.一种四方平面无导脚的导线架,包括:7. A lead frame with no guide pins on a square plane, comprising: 芯片座;以及chip holder; and 多个围绕该芯片座的接脚,该芯片座和该多个接脚分别具有第一表面和相对的第二表面;a plurality of pins surrounding the die paddle, the die paddle and the plurality of pins respectively have a first surface and an opposite second surface; 其特征在于,该导线架最外围的接脚的第一表面处形成有延伸部,并向远离第一表面的方向延伸,且相对的第二表面形成有凹部,用以在进行回焊时,使该凹部容纳焊料。It is characterized in that an extension portion is formed on the first surface of the outermost pin of the lead frame, and extends in a direction away from the first surface, and a concave portion is formed on the opposite second surface for reflow soldering. This recess is made to accommodate solder. 8.根据权利要求7所述的四方平面无导脚的导线架,其特征在于,该最外围的接脚具有阶梯状结构,且该接脚的凹部位于该封装单元的外侧缘。8 . The quadrilateral flat lead frame without leads according to claim 7 , wherein the outermost pins have a stepped structure, and the recesses of the pins are located on the outer edge of the packaging unit. 9 . 9.根据权利要求7所述的四方平面无导脚的导线架,其特征在于,全部的该接脚的第一表面处形成有延伸部,并向远离第一表面的方向延伸,且相对的第二表面形成有凹部。9. The lead frame with no guide pins on a square plane according to claim 7, characterized in that, all the first surfaces of the pins are formed with extensions, which extend in a direction away from the first surface, and are opposite to each other. A recess is formed on the second surface. 10.根据权利要求7所述的四方平面无导脚的导线架,其特征在于,该芯片座的第二表面还形成有凹部,用以在该四方平面无导脚封装单元进行回焊时,使该芯片座的第二表面形成的该凹部容纳焊料。10. The lead frame without leads in a square plane according to claim 7, wherein a concave portion is formed on the second surface of the chip base for reflowing the package unit without leads in a square plane, The recess formed by the second surface of the die paddle receives solder. 11.根据权利要求10所述的四方平面无导脚的导线架,其特征在于,该芯片座的凹部形成于该芯片座第二表面的中央位置。11 . The quadrilateral flat lead frame without guide pins according to claim 10 , wherein the concave portion of the die holder is formed at the center of the second surface of the die holder. 12 . 12.根据权利要求10所述的四方平面无导脚的导线架,其特征在于,该芯片座的凹部形成于该芯片座第二表面的周边位置。12 . The lead frame without lead pins in a square plane as claimed in claim 10 , wherein the concave portion of the chip pad is formed at a peripheral position of the second surface of the chip pad. 13 . 13.一种四方平面无导脚封装单元的制法,其特征在于,包括如下步骤:13. A method for manufacturing a four-square planar package unit without guide pins, comprising the following steps: 提供载板,该载板包括定义于该载板表面的多个切割线、形成于该切割线上的多个凸块、以及该多个凸块所围绕的平坦部;A carrier is provided, the carrier includes a plurality of cutting lines defined on the surface of the carrier, a plurality of bumps formed on the cutting lines, and a flat portion surrounded by the plurality of bumps; 于该具有凸块的载板表面上形成金属层后,图案化该金属层以得到导线架,该导线架具有形成于该平坦部上的具有第一表面和相对的第二表面的芯片座和多个接脚,其中,部分的接脚形成于该凸块处并包覆该凸块,而形成于该凸块处的接脚具有延伸部和凹部;After forming a metal layer on the surface of the carrier with bumps, the metal layer is patterned to obtain a lead frame having a chip pad having a first surface and an opposite second surface formed on the flat portion and a plurality of pins, wherein some of the pins are formed at the bump and cover the bump, and the pins formed at the bump have extensions and recesses; 将芯片接合于该芯片座上;bonding a chip to the chip holder; 形成多个导线,以电性连接芯片与接脚;forming a plurality of wires to electrically connect the chip and pins; 形成封装胶体于该载板上,以包覆该接脚、芯片座、芯片和导线;Forming an encapsulant on the carrier board to cover the pins, chip holders, chips and wires; 移除该载板,使外露出该导线架;以及removing the carrier plate to expose the lead frame; and 沿着所述切割线切割分离以得到多个四方平面无导脚封装单元。Cutting and separating along the cutting line to obtain a plurality of quadrangular planar leadless package units. 14.根据权利要求13所述的四方平面无导脚封装单元的制法,其特征在于,还包括通过焊料将该矩阵单元的芯片座和接脚接合于印刷电路板。14 . The method for manufacturing the quadrilateral planar leadless package unit according to claim 13 , further comprising bonding the chip base and the pins of the matrix unit to a printed circuit board by solder. 14 . 15.根据权利要求13所述的四方平面无导脚封装单元的制法,其特征在于,还包括在移除该载板后,在该芯片座的第二表面形成有凹部。15 . The manufacturing method of the quadrilateral planar leadless package unit according to claim 13 , further comprising forming a concave portion on the second surface of the die pad after removing the carrier board. 16 . 16.根据权利要求15所述的四方平面无导脚封装单元的制法,其特征在于,该芯片座的凹部形成于该芯片座第二表面的周边位置。16 . The manufacturing method of the quadrilateral planar leadless package unit according to claim 15 , wherein the concave portion of the die holder is formed at a peripheral position of the second surface of the die holder. 17 .
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