CN101870443A - Multilayer line conduction type wafer-level chip of micro-electro-mechanical system - Google Patents
Multilayer line conduction type wafer-level chip of micro-electro-mechanical system Download PDFInfo
- Publication number
- CN101870443A CN101870443A CN200910031523A CN200910031523A CN101870443A CN 101870443 A CN101870443 A CN 101870443A CN 200910031523 A CN200910031523 A CN 200910031523A CN 200910031523 A CN200910031523 A CN 200910031523A CN 101870443 A CN101870443 A CN 101870443A
- Authority
- CN
- China
- Prior art keywords
- wafer
- integrated circuit
- pad
- lines
- tin ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000011521 glass Substances 0.000 claims abstract description 7
- 239000011347 resin Substances 0.000 claims abstract description 4
- 229920005989 resin Polymers 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 16
- 239000012790 adhesive layer Substances 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a multilayer line conduction type wafer-level chip of a micro-electro-mechanical system. An integrated circuit pad and a light gathering zone are arranged on the upper end surface of a wafer, both sides of the integrated circuit pad are filled with adhesive layers, the integrated circuit pad and the adhesive layers are bonded with glass through resins, the lower part of the wafer is provided with at least two layers of lines conducted with the integrated circuit pad, all the layers of lines of the wafer are conducted as designed, the lines close to the integrated circuit pad and the non-conducting part of the integrated circuit pad are separated by an insulating layer, the non-conducting parts among each layer of lines are separated by insulating layers, a plurality of tin ball pads are formed on the lines close to the lower end surface of the wafer as designed, the lower end surface of the wafer is an insulating layer, a tin ball exposing out of the lower end surface of the wafer is arranged on the position corresponding to the tin ball pad on the lower end surface of the wafer, and the tin ball and the tin ball pad are conducted. Because the lower part of the wafer is provided with at least two layers of mutually conducted lines to replace one layer of original lines, the invention meets the various needs of clients in respects of multiple lines, wide lines and small pad spaces on small sizes.
Description
Technical field
The present invention relates to the wafer-level chip of micro-electro-mechanical system technical field, especially a kind of multilayer line conduction type wafer-level chip of micro-electro-mechanical system.
Background technology
(the English abbreviation: MEMS) (English is called for short the chip through-silicon-via wafer current level micro electromechanical system: TSV) in the encapsulation technology manufacturing process, generally adopt individual layer line layout form, expose wafer inner conductive piece (English abbreviation: pad) by preceding operation, sputtering aluminum, photoresistance coating exposure imaging, nickel plating, remove photoresist, deluster and carve the aluminium of glue-line, etching, the nickel plating gold, welding resisting layer coating exposure imaging, paste solder printing, technologies such as Reflow Soldering make the wafer inside and outside electrically interconnected, produce needed circuit and BGA (English abbreviation: BGA) weld pad, wafer-level micro electromechanical system (MEMS) chip of producing by above-mentioned technology contains the circuit of one deck and conducting block conducting, general line width and circuit or weld pad spacing are at the 40-100 micrometer range, spacing between the weld pad edge is many about 300 microns, electrically interconnectedly in the spacing about 300 microns go out three to four circuits from the wafer inside and outside, and satisfy the requirement of live width line-spacing, operation faces various problems under the prior art condition, there is etching unclean during as etching, disconnected short circuit problem etc., it is extremely difficult to avoid bad problem, directly influences output and yield, and the design of customer line must be drawn three or above circuit sometimes in spacing between the weld pad edge, make production technology face adverse conditions, the yield cost advantage no longer, thereby the restriction competitiveness of product.
Summary of the invention
In order to overcome above-mentioned defective, the invention provides a kind of multilayer line conduction type wafer-level chip of micro-electro-mechanical system, can reach multi-line on the customer requirement product small size, wide circuit and little weld pad spacing each side needs.
The present invention for the technical scheme that solves its technical problem and adopt is:
A kind of multilayer line conduction type wafer-level chip of micro-electro-mechanical system, comprise glass and wafer, (the English abbreviation: IC) face is the upper surface with the integrated circuit of wafer, the upper surface of described wafer is provided with integrated circuit weld pad and extraction regions, the integrated circuit weld pad part both sides of described wafer are filled with glue and form glue-line, the integrated circuit weld pad of the upper surface of wafer and glue-line are by resin and glass bonding, the bottom of described wafer is provided with the circuit that the integrated circuit weld pad with wafer is conducted, the bottom of described wafer is provided with two-layer at least circuit, press the design conducting between each layer line road of wafer, near the circuit of integrated circuit weld pad and the non-conduction place obstruct of integrated circuit weld pad insulating barrier is arranged, non-conduction place between each layer line road intercepts insulating barrier, circuit near the wafer lower surface is formed with some tin ball pad by design, the wafer lower surface is an insulating barrier, the position of the corresponding tin ball pad in described wafer lower surface is provided with the tin ball that exposes outside the wafer lower surface, described tin ball and the conducting of tin ball pad.
The invention has the beneficial effects as follows:, thereby realized client's multi-line on small size, the each side needs of wide circuit and little weld pad spacing because the bottom of wafer is provided with and two-layerly at least substitutes one deck circuit originally by design conducting mutual conduction line; Can adopt traditional circuit interlayer conduction technology during making, successfully manage product size downsizing and product circuit densification, improve the product yield.
Description of drawings
Fig. 1 is a cross-sectional view of the present invention.
The specific embodiment
Embodiment: a kind of multilayer line conduction type wafer-level chip of micro-electro-mechanical system, comprise glass 1 and wafer, integrated circuit (IC) face with wafer is the upper surface, the upper surface of described wafer is provided with integrated circuit weld pad 2 and extraction regions 3, the integrated circuit weld pad part both sides of described wafer are filled with glue 4 and form glue-line, the integrated circuit weld pad 2 of the upper surface of wafer and glue-line are by resin 5 and glass bonding, the bottom of described wafer is provided with the circuit 6 that the integrated circuit weld pad 2 with wafer is conducted, the bottom of described wafer is provided with two-layer at least circuit 6, press the design conducting between each layer line road 6 of wafer, near the circuit of integrated circuit weld pad 2 and the non-conduction place obstruct of integrated circuit weld pad 2 insulating barrier 7 is arranged, non-conduction place between each layer line road 6 intercepts insulating barrier 7, circuit 6 near the wafer lower surface is formed with some tin ball pad 8 by design, the wafer lower surface is an insulating barrier 7, the position of the corresponding tin ball pad 8 in described wafer lower surface is provided with the tin ball 9 that exposes outside the wafer lower surface, described tin ball 9 and 8 conductings of tin ball pad.
Because the bottom of wafer is provided with and two-layerly at least substitutes one deck circuit originally by design conducting mutual conduction line, thereby has realized client's multi-line on small size, the each side needs of wide circuit and little weld pad spacing; Can adopt traditional circuit interlayer conduction technology during making, successfully manage product size downsizing and product circuit densification, improve the product yield.
Claims (1)
1. multilayer line conduction type wafer-level chip of micro-electro-mechanical system, comprise glass (1) and wafer, integrated circuit face with wafer is the upper surface, the upper surface of described wafer is provided with integrated circuit weld pad (2) and extraction regions (3), the integrated circuit weld pad part both sides of described wafer are filled with glue (4) and form glue-line, the integrated circuit weld pad of the upper surface of wafer and glue-line are by resin (5) and glass bonding, the bottom of described wafer is provided with the circuit (6) that the integrated circuit weld pad with wafer is conducted, it is characterized in that: the bottom of described wafer is provided with two-layer at least circuit, press the design conducting between each layer line road of wafer, near the circuit of integrated circuit weld pad and the non-conduction place obstruct of integrated circuit weld pad insulating barrier (7) is arranged, non-conduction place between each layer line road intercepts insulating barrier, circuit near the wafer lower surface is formed with some tin ball pad (8) by design, the wafer lower surface is an insulating barrier, the position of the corresponding tin ball pad in described wafer lower surface is provided with the tin ball (9) that exposes outside the wafer lower surface, described tin ball and the conducting of tin ball pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910031523A CN101870443A (en) | 2009-04-22 | 2009-04-22 | Multilayer line conduction type wafer-level chip of micro-electro-mechanical system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910031523A CN101870443A (en) | 2009-04-22 | 2009-04-22 | Multilayer line conduction type wafer-level chip of micro-electro-mechanical system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101870443A true CN101870443A (en) | 2010-10-27 |
Family
ID=42995561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910031523A Pending CN101870443A (en) | 2009-04-22 | 2009-04-22 | Multilayer line conduction type wafer-level chip of micro-electro-mechanical system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101870443A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6262464B1 (en) * | 2000-06-19 | 2001-07-17 | International Business Machines Corporation | Encapsulated MEMS brand-pass filter for integrated circuits |
| CN1445829A (en) * | 2002-03-20 | 2003-10-01 | 裕沛科技股份有限公司 | Wafer type packaging and manufacturing method thereof |
| CN1495916A (en) * | 2002-07-15 | 2004-05-12 | ��ʽ���綫֥ | Micro electromechanical system device |
| US20050067681A1 (en) * | 2003-09-26 | 2005-03-31 | Tessera, Inc. | Package having integral lens and wafer-scale fabrication method therefor |
| CN1816731A (en) * | 2003-05-07 | 2006-08-09 | 霍尼韦尔国际公司 | Methods and apparatus for particle reduction in mems devices |
| CN101123231A (en) * | 2007-08-31 | 2008-02-13 | 晶方半导体科技（苏州）有限公司 | Encapsulation structure for wafer chip dimension of micro mechanical-electrical system and its making method |
| CN101177234A (en) * | 2006-11-08 | 2008-05-14 | 精工爱普生株式会社 | Electronic device and manufacturing method thereof |
| CN101292335A (en) * | 2005-10-19 | 2008-10-22 | Nxp股份有限公司 | Redistribution layer for wafer-level chip scale package and method therefor |
| CN201376891Y (en) * | 2009-04-22 | 2010-01-06 | 昆山西钛微电子科技有限公司 | Multi-layer circuit conducting wafer-level MEMS chip |
-
2009
- 2009-04-22 CN CN200910031523A patent/CN101870443A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6262464B1 (en) * | 2000-06-19 | 2001-07-17 | International Business Machines Corporation | Encapsulated MEMS brand-pass filter for integrated circuits |
| CN1445829A (en) * | 2002-03-20 | 2003-10-01 | 裕沛科技股份有限公司 | Wafer type packaging and manufacturing method thereof |
| CN1495916A (en) * | 2002-07-15 | 2004-05-12 | ��ʽ���綫֥ | Micro electromechanical system device |
| CN1816731A (en) * | 2003-05-07 | 2006-08-09 | 霍尼韦尔国际公司 | Methods and apparatus for particle reduction in mems devices |
| US20050067681A1 (en) * | 2003-09-26 | 2005-03-31 | Tessera, Inc. | Package having integral lens and wafer-scale fabrication method therefor |
| CN101292335A (en) * | 2005-10-19 | 2008-10-22 | Nxp股份有限公司 | Redistribution layer for wafer-level chip scale package and method therefor |
| CN101177234A (en) * | 2006-11-08 | 2008-05-14 | 精工爱普生株式会社 | Electronic device and manufacturing method thereof |
| CN101123231A (en) * | 2007-08-31 | 2008-02-13 | 晶方半导体科技（苏州）有限公司 | Encapsulation structure for wafer chip dimension of micro mechanical-electrical system and its making method |
| CN201376891Y (en) * | 2009-04-22 | 2010-01-06 | 昆山西钛微电子科技有限公司 | Multi-layer circuit conducting wafer-level MEMS chip |
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Application publication date: 20101027 |