CN101840972B - Structure and manufacturing method of flip-chip semiconductor optoelectronic element - Google Patents

Abstract

The present invention is a structure of a flip-chip semiconductor optoelectronic element and a manufacturing method thereof, the manufacturing method comprising: first forming a sacrificial layer on an epitaxial substrate; forming a semiconductor light-emitting structure on the sacrificial layer; etching the semiconductor light-emitting structure; fixing the semiconductor optoelectronic bare chip on the packaging substrate in a flip-chip manner, and then separating the epitaxial substrate by lift-off technology. The manufacturing method of the flip-chip semiconductor optoelectronic element is simple in process, and the semiconductor optoelectronic element manufactured by the manufacturing method has high luminous efficiency and good heat dissipation.

Description

Structure and manufacturing method of flip-chip semiconductor optoelectronic element

technical field

The present invention relates to the structure and manufacturing method of a flip-chip semiconductor optoelectronic element, in particular to the method of fixing the bare chip on the packaging substrate in a flip-chip manner, and then separating the temporary epitaxy by lift-off technology. The structure of semiconductor optoelectronic element and its manufacturing method.

Background technique

Light Emitting Diode (LED for short) is an electronic component that can convert electrical energy into light energy, and also has the characteristics of a diode. The most special feature of light-emitting diodes is that they will only emit light when they are powered from the positive pole. Generally, when a direct current is applied, the light-emitting diodes will emit light stably. However, if the AC power is connected, the LED will flash. The frequency of flashing depends on the frequency of the input AC power. The light-emitting principle of light-emitting diodes is to apply an external voltage to make electrons and holes combine in the semiconductor to release energy in the form of light.

For light-emitting diodes, long life, low calorific value and low power consumption, energy saving and pollution reduction are the biggest advantages. Light-emitting diodes have a wide range of applications, but luminous efficiency is one of the problems that needs to be improved, and it has always plagued the promotion and popularization of light-emitting diode lighting technology. To improve the luminous efficiency, it is necessary to effectively increase the light output efficiency.

The packaging components of light emitting diodes can be divided into two types: horizontal components and vertical components. Please refer to FIG. 1a and FIG. 1b , which are comparison diagrams of the package structures of the traditional wire bonding technology and the flip-chip technology. The substrate used for the so-called horizontal element is a non-conductive sapphire substrate, and its n-type electrode 105 and p-type electrode 107 are located on the same surface of the element. Component packaging is mainly in two ways: wire bonding technology (Wire Bonding) and flip chip technology (Flip Chip). As shown in FIG. 1a, the upward arrow in FIG. 1a is the main light emitting direction, and the downward arrow is the main heat dissipation direction. The wire bonding technology is to directly paste the light emitting diode die 123 on the packaging substrate 115, and then use the metal wire 311 to The LED die 123 is electrically connected to the packaging substrate 115 . As shown in Figure 1b, the upward arrow in Figure 1b is the main direction of light emission, and the downward arrow is the main direction of heat dissipation. It is fixed and electrically connected with the packaging substrate 115 . The wire bonding technology is currently the most widely used technology, and it can quickly obtain mass production. However, the flip-chip technology has relatively higher brightness than the wire-bonding technology because there are no electrodes and metal wires to interfere on the light-emitting surface. In addition, the flip chip technology uses bumps to raise the bare chip, and its heat dissipation is relatively better than the wire bonding technology that is directly bonded to the package substrate.

Please refer to FIG. 2 , which is a structural diagram of a vertical component in the prior art. In this figure, the upward arrow is the main light emitting direction, and the downward arrow is the main heat dissipation direction. The so-called vertical element is a light-emitting diode structure developed in recent years, which is characterized by replacing the sapphire substrate with a substrate with better conductivity such as silicon carbide (SiC), or separating the sapphire substrate from the light-emitting structure by lift-off technology. . In addition, the first electrode 215 of the vertical element can be an n-type electrode or a p-type electrode and the second electrode 217 is located on the opposite side of the element, wherein the first electrode 215 is an n-type electrode and the second electrode 217 is a p-type electrode, and the second electrode 217 is a p-type electrode. One electrode 215 is a p-type electrode and the second electrode 217 is an n-type electrode. During packaging, the first electrode 215 at one end can be directly bonded to the packaging substrate 115 , and the second electrode 217 at the other end needs to be electrically connected by wire bonding with the metal wire 311 . Vertical components have better heat dissipation and luminous efficiency than horizontal components, especially the removal of the substrate by lift-off technology increases the conductivity of the components. Since the second electrode 217 at one end of the vertical element is formed on the light-emitting area, when the element emits light, the second electrode 217 will affect the light-emitting intensity of the element due to covering the light-emitting area. Especially, the smaller the light-emitting area of the element, the larger the relative shielding area of its electrodes, and the more affected the luminous intensity. Theoretically, in order to avoid the shielding of the electrodes, packaging with flip-chip technology can achieve the advantages of good heat dissipation and high brightness, but there are difficulties in the process. Please refer to FIG. 3a , FIG. 3b and FIG. 3c , which are simple schematic diagrams of etching, peeling off the epitaxial substrate and flip-chip packaging. As shown in FIG. 3 a , after forming a light emitting structure 309 on the epitaxial substrate 101 , a first electrode 215 is formed on the light emitting structure 309 . Then etch to the light emitting structure 309 and expose the n-type conductive layer. As shown in FIG. 3 b , the second electrode 217 is formed on the n-type conductive layer by sputtering, and then the bumps 113 are respectively placed on the second electrode 217 and the first electrode 215 to achieve electrical connection. Next, the epitaxial substrate 101 is removed. Fig. 3c is die dicing, which is formed into individual dies, and the dotted arrow in the figure is the cutting direction. In practice, there are several parts of the process that need to be overcome. The first part is the etching process. Since the actual thickness ratio between the light emitting structure 309 and the first electrode 215 can reach more than 1:20, the first electrode 215 must be completely removed before reaching the light emitting structure 309 during the etching process. Therefore, the etching must consider the thickness of the first electrode, but it is often difficult to control the etching depth of the light emitting structure. The second part is the process of forming the second electrode. The electrodes are generally formed by sputtering. It can be seen from FIG. 3 a that the position where the second electrode 217 is formed is a deep U-shaped space 313 . The difficulty of forming the second electrode 217 has increased for the sputtering technique. The requirements for forming the second electrode 217 also include that the height of the electrode must be the same as that of the first electrode 215, and the distance between the second electrode 217 and the first electrode 215 and the light emitting structure 309 must be kept so as not to cause an electrical short circuit and to keep the rear end. It is even more difficult to form electrodes in the deep U-shaped space 313 due to the space for die dicing. The third part is the thermal stress between the first electrode 215 and the light emitting structure 309 . The electrode material is mainly metal material, while the light emitting structure is III-V group compound. The thermal expansion coefficient (Thermal expansion coefficient; TEC) of general metal materials is higher than that of GaN. Please refer to FIG. 3b, when the epitaxial substrate 101 is removed by laser lift-off technology (Laser Lift Off; LLO), its temperature will reach about 400 degrees, which will easily cause thermal stress between the first electrode 215 and the light emitting structure 309, thus The deformation of the first electrode 215 and the cracking of the light emitting structure 309 are caused.

Therefore, the present invention provides a package structure of a flip-chip semiconductor optoelectronic device to improve the above-mentioned disadvantages.

Contents of the invention

In view of the deficiencies in the background technology described above, in order to meet the needs of the market, the technical problem to be solved by the present invention is to provide a packaging structure of a flip-chip semiconductor optoelectronic element and a manufacturing method thereof, which has a simple process, high luminous efficiency, Good heat dissipation.

In order to solve the above-mentioned technical problems, the present invention provides a flip-chip semiconductor optoelectronic element structure, comprising: a package substrate having a first surface and a second surface opposite to the first surface, wherein the first surface has a first surface A welding pad and a second welding pad, a first bump is located on the first welding pad, a second bump is located on the second welding pad; a semiconductor light emitting structure has a first surface and The second surface, wherein the first surface includes an n-type electrode and a p-type electrode, the n-type electrode is electrically connected to the first bump, and the p-type electrode is electrically connected to the second bump; an insulating layer, located between the n-type electrode and the p-type electrode, electrically isolating the n-type electrode and the p-type electrode; and a transparent adhesive material, located between the first surface of the packaging substrate and the first surface of the semiconductor light emitting structure Between one surface, the first welding pad, the second welding pad, the first bump and the second bump are covered.

In order to solve the above-mentioned another technical problem, the present invention provides a method for manufacturing a flip-chip semiconductor optoelectronic device, the method includes: providing an epitaxial substrate; forming a sacrificial layer on the epitaxial substrate; forming a semiconductor light-emitting structure on the On the sacrificial layer, the semiconductor light emitting structure has a first surface and a second surface opposite to the first surface, the sacrificial layer is located on the second surface of the semiconductor light emitting structure; an n-type electrode and a p-type electrode are formed on the On the first surface of the semiconductor light emitting structure; reverse the semiconductor light emitting structure on a package substrate, the package substrate has a first surface and a second surface opposite to the first surface, wherein the first surface has a first solder Pad and a second pad, the packaging substrate also includes a first bump and a second bump, the first bump is located on the first pad, the second bump is located on the second pad, The n-type electrode is electrically connected to the first bump, and the p-type electrode is electrically connected to the second bump; a transparent glue is filled between the first surface of the packaging substrate and the first surface of the semiconductor light emitting structure. covering the first pad, the second pad, the first bump and the second bump; etching the sacrificial layer to peel off the epitaxial substrate.

The beneficial technical effect of the present invention is: compared with the luminous rate of general traditional semiconductor optoelectronic horizontal element, the semiconductor optoelectronic element of the present invention is packaged with flip-chip technology and then peeled off the epitaxial substrate, and the light emitted by the element is less disturbed by the substrate and electrodes, so Its luminous rate is higher than that of general traditional semiconductor photoelectric level components. In addition, the heat dissipation of semiconductor optoelectronic elements is better than that of general semiconductor optoelectronic elements. In addition, the process method of the semiconductor optoelectronic element of the present invention is relatively simple.

Description of drawings

Figure 1a and Figure 1b are comparison diagrams of the packaging structure of traditional wire bonding technology and flip chip technology;

Fig. 2 is a prior art vertical element structure diagram;

3a to 3c are simple schematic diagrams of etching, peeling off the epitaxial substrate and flip-chip packaging;

Fig. 4 is main method flowchart of the present invention;

Fig. 5 a to Fig. 5 q are the schematic diagrams of forming each step of the flip-chip semiconductor photoelectric element of the present invention (Fig. 5a to Fig. 5e are the schematic diagrams of each step of forming the first sacrificial layer method of the present invention);

6a to 6e are schematic diagrams of steps in the second method for forming a sacrificial layer of the present invention; and

7a to 7e are schematic diagrams of steps in the third method for forming a sacrificial layer according to the present invention.

Wherein, the reference signs are explained as follows:

101 epitaxial substrate 121 cylinder

103 masks 123 bare chips

105n-type electrode 125 semiconductor optoelectronic components

107p type electrode 127 grooves

109 light-emitting area 201 the first group III nitride

111 Cutting Platform 203 Group III Nitride

113 Bumps 205 Group III Nitride

115 package substrate 207 ohm contact layer

117 Welding pad 209 Insulation layer

119 holes 305 electron blocking layer

211 transparent adhesive material 307p type conductive layer

213 protective layer 309 light-emitting structure

215 first electrode 311 metal wire

217 second electrode 313 U-shaped space

301n-type conductive layer 303 light-emitting layer

Detailed ways

The direction of the present invention discussed here is a package structure of a flip-chip semiconductor optoelectronic element and a manufacturing method thereof. In order to provide a thorough understanding of the present invention, detailed steps and components thereof will be set forth in the following description. Obviously, the practice of the invention is not limited to specific details well known to those skilled in the semiconductor optoelectronic process. On the other hand, well-known components or steps have not been described in detail so as not to unnecessarily limit the invention. Preferred embodiments of the present invention will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited, it is defined by the claims range prevails.

The invention provides a package structure of a flip-chip semiconductor optoelectronic element, which includes a package substrate with a first surface and a second surface opposite to the first surface. Wherein the first surface has a first welding pad and a second welding pad. A first bump is located on the first welding pad, and a second bump is located on the second welding pad. A semiconductor light emitting structure has a first surface and a second surface opposite to the first surface. Wherein the first surface includes an n-type electrode and a p-type electrode. The n-type electrode is electrically connected to the first bump. The p-type electrode is electrically connected to the second bump. An insulating layer is located between the n-type electrode and the p-type electrode, electrically isolating the n-type electrode and the p-type electrode. And, a transparent adhesive material is located between the first surface of the packaging substrate and the first surface of the semiconductor light emitting structure. The transparent adhesive material simultaneously covers the first pad, the second pad, the first bump and the second bump.

The above package substrate can be printed circuit board (Printed Circuit Board; PCB), BT resin printed circuit board (Bismaleimide Triazine resin Printed Circuit Board; BT PCB), high thermal coefficient aluminum substrate (Metal Core Printed Circuit Board; MCPCB), flexible printed circuit board Circuit board (Flexible Printed Circuit Board; Flexible PCB), ceramic substrate (Ceramic), silicon substrate.

The aforementioned bumps can be palladium-tin alloy (Pd/Tin).

The aforementioned n-type electrode can be titanium/aluminum/titanium/gold alloy (Ti/Al/Ti/Au), chrome-gold alloy (Cr/Au) or lead-gold alloy (Pd/Au).

The above-mentioned p-type electrode can be nickel-gold alloy (Ni/Au), platinum-gold alloy (Pt/Au), chromium-gold alloy (Cr/Au), tungsten (W) or palladium (Pd).

The above insulating layer can be silicon dioxide (SiO ₂ ), epoxy resin (Epoxy), silicon nitride (Si ₃ N ₄ ), titanium dioxide (TiO2) or aluminum nitride (AlN).

The above-mentioned transparent adhesive material can be silicon dioxide (SiO ₂ ), epoxy resin (Epoxy), or silicon nitride (Si ₃ N ₄ ).

The above protective layer can be silicon dioxide (SiO ₂ ).

In addition, the present invention also provides a method for manufacturing a flip-chip semiconductor optoelectronic device structure, which includes providing an epitaxial substrate. A sacrificial layer is formed on the epitaxial substrate. A semiconductor light emitting structure is formed on the sacrificial layer. The semiconductor light emitting structure has a first surface and a second surface opposite to the first surface. The sacrificial layer is located on the second surface of the semiconductor light emitting structure. An n-type electrode and a p-type electrode are formed on the first surface of the semiconductor light emitting structure. The semiconductor light-emitting structure is flipped on a packaging substrate. The packaging substrate has a first surface and a second surface opposite to the first surface. Wherein the first surface has a first welding pad and a second welding pad. A first bump is located on the first welding pad, and a second bump is located on the second welding pad. The substrate includes a first bump and a second bump. The n-type electrode is electrically connected to the first bump, and the p-type electrode is electrically connected to the second bump. A transparent glue is filled between the first surface of the packaging substrate and the first surface of the semiconductor light emitting structure. The transparent adhesive material simultaneously covers the first pad, the second pad, the first bump and the second bump. The sacrificial layer is etched to lift off the epitaxial substrate.

The step of forming the sacrificial layer on the epitaxial substrate includes forming a first III-nitride on the epitaxial substrate. Next, a patterned mask is formed on the first III-nitride. The first Ill-nitride is etched again, and the patterned mask is removed.

In addition, the step of forming the sacrificial layer on the epitaxial substrate includes forming a first III-nitride on the epitaxial substrate. A patterned mask is formed on the first Ill-nitride. A second III-nitride is formed on the patterned mask, and the patterned mask is removed to form a plurality of holes.

In addition, the step of forming the sacrificial layer on the epitaxial substrate includes forming a mask on the epitaxial substrate. Annealing forms a patterned mask. The epitaxial substrate is etched, and the patterned mask is removed.

The above etching can be wet etching, dry etching or inductively coupled plasma etcher (ICP).

The above method further includes forming an insulating layer between the n-type electrode and the p-type electrode, which can increase the structural rigidity of the semiconductor light-emitting structure and electrically isolate the n-type electrode and the p-type electrode.

The above method further includes firstly forming a protection layer on the periphery of the semiconductor light emitting structure, and then etching the sacrificial layer to peel off the epitaxial substrate.

The aforementioned epitaxial substrates can be sapphire (Al ₂ O ₃ ) substrates, silicon carbide (SiC) substrates, lithium aluminate substrates (AlLiO ₂ ), lithium gallate substrates (LiGaO ₂ ), silicon (Si) substrates, gallium nitride ( GaN) substrate, zinc oxide (ZnO) substrate, aluminum zinc oxide substrate (AlZnO), gallium arsenide (GaAs) substrate, gallium phosphide (GaP) substrate, gallium antimonide substrate (GaSb), indium phosphide (InP) substrate , Indium Arsenide (InAs) substrate or Zinc Selenide (ZnSe) substrate.

Please refer to FIG. 4 , which is a flowchart of a method mainly forming the present invention. In the first step, the present invention firstly forms a sacrificial layer, and the sacrificial layer can be formed by three methods. The first method includes forming a first Ill-nitride on the epitaxial substrate. Next, a patterned mask is formed on the first III-nitride. The first Ill-nitride is etched again, and the patterned mask is removed. The second method includes first forming a first III-nitride on the epitaxial substrate. Next, a patterned mask is formed on the first III-nitride. A second III-nitride compound is formed on the patterned mask, and the patterned mask is removed to form a plurality of holes. The third method includes first forming a mask on the epitaxial substrate. A patterned mask is then formed by annealing. Next the epitaxial substrate is etched, and finally the patterned mask is removed. Forming a sacrificial layer is an easier way to remove the epitaxial substrate in a later process without using a laser.

In the second step, a semiconductor light emitting structure is formed on the sacrificial layer. Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE) can be used to deposit the semiconductor light emitting structure on the sacrificial layer. The semiconductor light-emitting structure may include an n-type conductive layer, a light-emitting layer, an electron blocking layer, and a p-type conductive layer. In addition, an ohmic contact layer can be formed on the p-type conductive layer, so that the current-voltage characteristic curve is linear, and the stability of the element is increased.

The third step is to etch the above-mentioned semiconductor light-emitting structure to form a light-emitting region, a cutting platform and expose the n-type conductive layer. Separately form n-type electrodes on the n-type conductive layer, and p-type electrodes on the ohmic contact layer to achieve electrical connection. In addition, providing an insulating layer formed between the n-type electrode and the p-type electrode can not only support the semiconductor light-emitting structure and increase the rigidity of the structure, but also reduce the mutual interference between the n-type electrode and the p-type electrode.

The fourth step is to reverse the above-mentioned semiconductor light-emitting structure on a packaging substrate. A bump is respectively formed on the n-type electrode and the p-type electrode of the above-mentioned semiconductor light-emitting structure. By using the flip-chip technology, the bump is electrically connected to the welding pad of a packaging substrate, which can prevent the electrode from covering the light-emitting area and affecting the light-emitting rate.

In the fifth step, etching the sacrificial layer to peel off the epitaxial substrate. Before etching, the components need to be protected from damage caused by the etchant. Therefore, a transparent adhesive material is provided to fill between the semiconductor light emitting structure and the package substrate, and cover the bumps and pads to maintain electrical connection. In addition, a protective layer is used to cover the semiconductor light-emitting structure and the packaging substrate so as not to be affected by the etching solution. Then, an etchant with an appropriate selection ratio is used to destroy the sacrificial layer through holes in the sacrificial layer, so as to peel off the epitaxial substrate. Finally, the protective layer is removed.

The implementation content of the above-mentioned flow chart of the method of the present invention will be combined with diagrams and structural schematic diagrams of each step to introduce the structure of the present invention and the formation of each step in detail.

Firstly, a sacrificial layer is formed on an epitaxial substrate. The present invention proposes three methods of forming the sacrificial layer. For the first method of forming a sacrificial layer, please refer to FIG. 5a to FIG. 5e. As shown in FIG. 5 a , a first III-nitride compound 201 is formed on the epitaxial substrate 101 . As shown in FIG. 5 b , a patterned mask 103 is formed on the first III-nitride 201 . As shown in FIG. 5c, the first III-nitride 201 is etched next. As shown in FIG. 5 d , the patterned mask 103 is removed from the first III-nitride 201 to form a sacrificial layer, and the sacrificial layer includes a plurality of grooves 127 and a plurality of pillars 121 . Finally, as shown in FIG. 5e, a second III-nitride 203 is formed as a buffer layer on the sacrificial layer. For the detailed content and formation method of the first step of forming the sacrificial layer, you can refer to the patent application proposal of Advanced Development Optoelectronics Co., Ltd., China Taiwan Patent Application No. 097107609, the patent name is the manufacture of group III nitrogen compound semiconductor photoelectric elements method and its structure.

In addition, for another method of forming a sacrificial layer, please refer to FIG. 6a to FIG. 6e. As shown in FIG. 6 a , a first III-nitride compound 201 is first formed on the epitaxial substrate 101 . As shown in FIG. 6 b , a patterned mask 103 is then formed on the first III-nitride 201 . As shown in FIG. 6 c , a second III-nitride compound 203 is formed on the patterned mask 103 . As shown in FIG. 6d, the patterned mask 103 is removed to form a plurality of holes 119, so that the second III-nitride 203 becomes a sacrificial layer. Finally, as shown in FIG. 6e, a third III-nitride compound 205 is formed as a buffer layer on the sacrificial layer. For the detailed content and formation method of the second step of forming the sacrificial layer, you can refer to the patent application proposal of Advanced Development Optoelectronics Co., Ltd., China Taiwan Patent Application No. 097115512, the patent name is the manufacture of group III nitrogen compound semiconductor optoelectronic components method and its structure.

In addition, for yet another method of forming a sacrificial layer, please refer to FIG. 7a to FIG. 7e. As shown in FIG. 7 a , a first electrode 215 is firstly formed on the epitaxial substrate 101 . As shown in FIG. 7 b , the first electrode 215 is annealed to form a patterned mask 103 . As shown in FIG. 7c, the epitaxial substrate 101 is etched again to form a sacrificial layer. The sacrificial layer includes a plurality of grooves 127 and a plurality of pillars 121 . As shown in Figure 7d, the patterned mask 103 is removed. Finally, as shown in FIG. 7e, a group III nitride 201 is formed as a buffer layer on the sacrificial layer. For the detailed content and formation method of the third step of forming a sacrificial layer, please refer to the patent application proposal of Advanced Development Optoelectronics Co., Ltd., China Taiwan Patent Application No. 097117099, and the patent name is a method for separating semiconductors and their substrates.

The following steps will be described in detail by taking the first method of forming a sacrificial layer as an example.

Next, as shown in FIG. 5 f , doping group IV atoms to form an n-type conductive layer 301 on the second group III nitride 203 . In this embodiment, the dopant is silicon atom (Si), and the precursor of silicon can be silane (SiH ₄ ) or silicon ethane (Si ₂ H ₆ ) in the metalorganic chemical vapor deposition equipment. The formation method of the n-type conductive layer 301 is sequentially from gallium nitride layer (GaN) or aluminum gallium nitride layer (AlGaN) doped with silicon atoms (Si) at a high concentration to nitrogen doped with silicon atoms (Si) at a low concentration. gallium nitride layer or aluminum gallium nitride layer (AlGaN). Gallium nitride (GaN) or aluminum gallium nitride (AlGaN) layer doped with silicon atoms (Si) at a high concentration can provide better conduction effect between n-type electrodes.

Next, a light emitting layer 303 is formed on the n-type conductive layer 301 . The light-emitting layer 303 can be a single heterostructure, a double heterostructure, a single quantum well layer or a multiple quantum well layer structure. At present, multiple quantum well layer structures are mostly used, that is, multiple quantum well layer/barrier layer structures. Indium gallium nitride (InGaN) can be used for the quantum well layer, and a ternary structure such as aluminum gallium nitride (AlGaN) can be used for the barrier layer. In addition, a quaternary structure may also be adopted, that is, aluminum gallium indium nitride (Al _x In _y Ga _1-xy N) is used as the quantum well layer and the barrier layer at the same time. The ratio of aluminum to indium is adjusted so that the energy levels of the aluminum gallium indium nitride lattice can respectively become a barrier layer of a high energy level and a quantum well layer of a low energy level. The light-emitting layer 303 can be doped with n-type or p-type dopant, can be doped with n-type and p-type dopant at the same time, or can be completely undoped. And, it may be that the quantum well layer is doped but the barrier layer is not doped, the quantum well layer is not doped but the barrier layer is doped, both the quantum well layer and the barrier layer are doped, or the quantum well layer and the barrier layer are both doped. Not adulterated. In addition, high-concentration doping (delta doping) can also be performed in some regions of the quantum well layer.

Afterwards, a p-type conductive electron blocking layer 305 is formed on the light emitting layer 303 . The p-type conductive electron blocking layer 305 includes a first type III-V group semiconductor layer and a second type III-V group semiconductor layer. The energy gaps of these two kinds of III-V semiconductor layers are different, and they are periodically and repeatedly deposited on the above-mentioned light-emitting layer 303. The previous periodic and repeated deposition actions can form an electron blocking layer with a higher energy barrier (the energy barrier is higher than The energy barrier of the active light-emitting layer) is used to prevent excessive electrons (e-) from overflowing the light-emitting layer 303 . The first type III-V group semiconductor layer may be an aluminum indium gallium nitride (Al _x In _y Ga _1-xy N) layer, and the second type III-V group semiconductor layer may be an aluminum indium gallium nitride ( Al _{uIn v} Ga _1-uv N) layer. Wherein, 0<x≤1, 0≤y<1, x+y≤1, 0≤u<1, 0≤v≤1 and u+v≤1. When x=u, y≠v. In addition, the III-V group semiconductor layer may also be gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) or Aluminum indium nitride (AlInN).

Finally, group II atoms are doped to form a p-type conductive layer 307 on the electron blocking layer 305 . In this example it is a magnesium atom. The precursor of magnesium can use CP ₂ Mg in metalorganic chemical vapor deposition equipment. The p-type conductive layer 307 is formed sequentially from a gallium nitride layer (GaN) or an aluminum gallium nitride layer (AlGaN) doped with a low concentration of magnesium atoms (Mg) to a nitride layer doped with a high concentration of magnesium atoms (Mg). Gallium layer or aluminum gallium nitride layer (AlGaN). A gallium nitride (GaN) layer or an aluminum gallium nitride layer doped with a high concentration of magnesium atoms (Mg) can provide a better conduction effect between the p-type electrodes.

As shown in FIG. 5 g , an ohmic contact layer 207 is then formed on the light emitting structure 309 . Generally, the ohmic contact layer 207 is formed on the light emitting structure 309 by physical vapor deposition methods such as evaporation and sputtering. Its material can be nickel/gold (Ni/Au), indium tin oxide (Indium Tin Oxide; ITO), indium zinc oxide (Indium Zinc Oxide; IZO), indium tungsten oxide (Indium Tungsten Oxide; IWO), indium gallium oxide ( Indium Gallium Oxide; IGO), platinum/gold (Pt/Au), chromium/gold (Cr/Au), nickel/chromium (Ni/Cr) or nickel/magnesium/nickel/chromium (Ni/Mg/Ni/Cr ).

As shown in Figure 5h, after covering the ohmic contact layer 207, the photoresist is fully coated on the surface of the ohmic contact layer 207 by a photoresist spin coater to form a photoresist agent film. Then photolithography is used to pattern the photoresist film to form a mask, so that the part expected to be etched is exposed. Then use wet etching, dry etching or inductively coupled plasma etcher (ICP) for mesa (benchtop) process. The mesa process is to etch the light emitting structure 309 to form a light emitting region 109 and a cutting platform 111 , while exposing the n-type conductive layer 301 . Finally, the wafer is cut into bare chips 123 by laser cutting, and the direction of the dotted arrow in the figure is the cutting direction.

As shown in FIG. 5 i , an n-type electrode 105 is formed on the n-type conductive layer 301 , and a p-type electrode 107 is formed on the ohmic contact layer 207 . The n-type electrode 105 and the p-type electrode 107 can deposit metal on the n-type conductive layer 301 and the ohmic contact layer 207 by physical vapor deposition methods such as sputtering and evaporation. The n-type electrode 105 can be titanium/aluminum/titanium/gold (Ti/Al/Ti/Au), chrome-gold alloy (Cr/Au) or lead-gold alloy (Pd/Au). The p-type electrode 107 can be nickel-gold alloy (Ni/Au), platinum-gold alloy (Pt/Au), tungsten (W), chromium-gold alloy (Cr/Au) or palladium (Pd).

As shown in FIG. 5 j , an insulating layer 209 is formed between the n-type electrode 105 and the p-type electrode 107 . The insulating layer 209 can reduce the mutual interference between the n-type electrode 105 and the p-type electrode 107 , and can also strengthen the light-emitting structure 309 so that it is not easily broken. The insulating layer can be silicon dioxide (SiO ₂ ), epoxy resin (Epoxy), silicon nitride (Si ₃ N ₄ ), titanium dioxide (TiO ₂ ) or aluminum nitride (AlN).

As shown in FIG. 5k and FIG. 5l , one or more dies 123 are electrically connected to a packaging substrate 115 by flip-chip bonding technology. Firstly, the bumps 113 are individually formed on the n-type electrode 105 and the p-type electrode 107 , and then the bumps 113 are respectively corresponding to the soldering pads 117 on the packaging substrate to achieve electrical connection. The composition of the bump 113 for flip-chip bonding is generally made of lead-tin alloy, and the selection of the ratio depends on the type of the substrate and the assembly procedure. The most commonly used ratio is 95% lead-5% tin. The packaging substrate 115 can be a printed circuit board (Printed Circuit Board; PCB), a BT resin printed circuit board (Bismaleimide Triazine resin Printed Circuit Board; BT PCB), a high thermal coefficient aluminum substrate (Metal Core Printed Circuit Board; MCPCB), soft Flexible Printed Circuit Board (FlexiblePrinted Circuit Board; Flexible PCB), ceramic substrate (Ceramic), or silicon substrate. For the detailed content and steps of the silicon substrate packaging, please refer to the patent application proposal of Advanced Development Optoelectronics Co., Ltd., China Taiwan Patent No. I292962, the patent name is the packaging structure of solid-state light-emitting elements and its manufacturing method.

As shown in FIG. 5m and FIG. 5n , before peeling off the epitaxial substrate 101 , the electrical connection between the bump 113 and the packaging substrate 115 and the entire light-emitting element must be protected from damage caused by chemical solution corrosion. The bump 113 and the packaging substrate 115 are first covered with a transparent material, and then the entire light-emitting device is covered with a protective layer, but the epitaxial substrate 101 and the first III-nitride layer 201 are not included. The transparent adhesive material can be silicon dioxide (SiO ₂ ), epoxy resin (Epoxy), or silicon nitride (Si ₃ N ₄ ). The protective layer 213 can be silicon dioxide (SiO ₂ ).

As shown in FIG. 5o, after the element protection is completed, the epitaxial substrate 101 will be peeled off by wet etching. Through the selection and preparation of the chemical solution, the chemical solution is injected into the first III-nitride layer 201 . The chemical reaction between the first III-nitride compound layer 201 and the chemical solution will cause the structure of the first III-nitride compound layer 201 to collapse. Therefore, the epitaxial substrate 101 on the first group III nitride layer 201 is immediately peeled off.

Finally, as shown in FIG. 5p and FIG. 5q, after removing the protective layer 213 on the element, the packaging substrate 115 is cut (the direction of the dotted arrow in FIG. 5p is the cutting direction), that is, a plurality of semiconductor optoelectronic elements 125 are formed. The protective layer 213 can be removed by wet and dry methods. The wet method is to use an organic solution to dissolve the protective material to achieve the purpose of removing the protective layer. The organic solvents used such as acetone (Acetone), methyl-pyrrolidinone (N-Methyl-Pyrolidinone; NMP), dimethyl sulfoxide (Dimethyl Sulfoxide) ; DMSO), 2-(2-aminoethoxy)ethanol 2-(2-Aminoethoxyethanol), ethanolamine (MonoEthanolAmine; MEA), and ethylene glycol monobutyl ether (ButoxyDiGlycol; BDG) and the like. Another wet method can use an inorganic solution such as a mixed solution (SPM) of sulfuric acid and hydrogen peroxide, and the process cost of this method is relatively low. Dry demasking uses oxygen or its plasma to remove the photoresist. After removing the protection layer 213 , the packaging substrate 115 is cut with a common knife to form a plurality of semiconductor photoelectric elements 125 .

The steps of the above method can be changed in sequence according to different conditions, so that the process can better meet the actual needs.

Based on the above description, compared with the luminous efficiency of conventional semiconductor optoelectronic horizontal elements, the semiconductor optoelectronic element of the present invention is encapsulated by flip-chip technology and then peeled off the epitaxial substrate. The light emitted by the element is less disturbed by the substrate and electrodes. The luminous rate is higher than that of the general traditional semiconductor photoelectric level components. In addition, the heat dissipation of semiconductor optoelectronic elements is better than that of general semiconductor optoelectronic elements. In addition, the process method of the semiconductor optoelectronic element of the present invention is relatively simple.

Obviously, according to the description in the above embodiments, the present invention may have many modifications and differences. It is therefore to be understood within the scope of the claims that the invention may be practiced broadly in other embodiments than those described in detail above. The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed in the present invention should be included in the scope of the present invention. within the scope defined in the claims.

Claims (8)

1. the manufacturing approach of a flip-chip type semiconductor photoelectric cell structure comprises:

One epitaxial substrate is provided;

Form a sacrifice layer on this epitaxial substrate, said sacrifice layer comprises a plurality of grooves and a plurality of cylinder;

Form the semiconductor ray structure on this sacrifice layer; This semiconductor light emitting structure has a first surface and with respect to the second surface of first surface; This sacrifice layer is positioned at the second surface of this semiconductor light emitting structure, and said semiconductor light emitting structure is not filled said a plurality of groove;

Form a n type electrode and a p type electrode on the first surface of this semiconductor light emitting structure;

Be inverted this semiconductor light emitting structure on a base plate for packaging; This base plate for packaging has a first surface and with respect to the second surface of first surface, wherein this first surface has one first weld pad and one second weld pad, also comprises one first projection and one second projection on this base plate for packaging; This first projection is positioned on this first weld pad; This second projection is positioned on this second weld pad, and this n type electrode and this first projection electrically connect, and this p type electrode and this second projection electrically connect;

Fill a transparent adhesive tape material between the first surface of the first surface of this base plate for packaging and semiconductor light emitting structure, coat this first weld pad, this second weld pad, this first projection and this second projection;

This sacrifice layer of etching is to peel off this epitaxial substrate.

2. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, the step of this sacrifice layer of wherein said formation on this epitaxial substrate comprises:

Form one first III-nitride on this epitaxial substrate;

The shade that forms a patterning is on this first III-nitride;

This first III-nitride of etching; And

Remove the shade of this patterning.

3. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, the step of this sacrifice layer of wherein said formation on this epitaxial substrate comprises:

Form one first III-nitride on this epitaxial substrate;

The shade that forms a patterning is in this first III-nitride;

Form one second III-nitride on the shade of this patterning; And

The shade that removes said patterning forms a plurality of holes.

4. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, the step of this sacrifice layer of wherein said formation on this epitaxial substrate comprises:

Form a shade on this epitaxial substrate;

Annealing forms the shade of a patterning;

This epitaxial substrate of etching; And

Remove the shade of this patterning.

5. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, wherein said wet etching, dry ecthing or the inductance type plasma etch system of being etched to.

6. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, wherein said method also comprise formation one insulating barrier structural rigidity and this n type electrode of electrical isolation and this p type electrode with the increase semiconductor light emitting structure between this n type electrode and this p type electrode.

7. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, wherein said method also comprise elder generation and form a protective layer in this semiconductor light emitting structure periphery, and this sacrifice layer of etching is to peel off this epitaxial substrate again.

8. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, it is wet etching that wherein said etch sacrificial layer is peeled off this epitaxial substrate.

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