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CN101836293A - 安装结构体 - Google Patents

安装结构体 Download PDF

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Publication number
CN101836293A
CN101836293A CN200880104222A CN200880104222A CN101836293A CN 101836293 A CN101836293 A CN 101836293A CN 200880104222 A CN200880104222 A CN 200880104222A CN 200880104222 A CN200880104222 A CN 200880104222A CN 101836293 A CN101836293 A CN 101836293A
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semiconductor element
sealing resin
circuit substrate
slot part
pattern
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CN101836293B (zh
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松野行壮
山口敦史
酒谷茂昭
宫川秀规
植田干也
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

一种安装结构体，槽部以其端部朝半导体元件延伸的形态形成于电路基板表面，以使得密封树脂的注入作业简单且可靠地进行密封，滴下后的低粘度的密封树脂被引导到上述槽部并流入电路基板与半导体元件之间，不容易扩散到半导体元件以外的范围。

Description

安装结构体
技术领域
本发明涉及一种将半导体元件安装于电路基板的安装结构体，尤其涉及对表面安装后的半导体元件填充密封树脂的安装结构体。
背景技术
近年来，以电子设备的小型化、轻量化、高性能化以及高速化为目的，在电子设备的电路基板上也要求进行高密度安装。因而，对包含安装于电路基板的电子元器件及芯片部件、BGA(球栅阵列：Ball Grid Array)形状的半导体元件、将平面电极焊盘而不是BGA的焊球格子状排列的LGA(触点阵列：Land GridArray)形状的半导体元件、GSP(芯片级封装：Chip Size Package)形状的半导体元件的安装结构体而言，也可实现小型化、薄型化、高速化、多端子化。其结果是，安装结构体的机械强度降低，对于所施加的机械应力和温度变化，脆弱的安装结构体增多。
作为将半导体元件安装在电路基板上的方法，一般采用如下方法：在电路基板上的规定位置将半导体元件的电极以接触的形态配置，向应连接的各个电极之间供给焊锡材料或导电性粘接剂，并将其送入回流熔炉等中，藉此将半导体元件与电路基板的各个电极接合，继而，与上述接合操作并行或在其前后将包括接合部周围的半导体元件与电路基板之间用密封树脂材密封。
即使此后被暴露在热循环和高温多湿的环境下，由于上述树脂密封将半导体元件粘接、固定于电路基板，因而能高可靠性地保护接合部。
此外，在树脂密封中，形成于半导体元件周围的嵌条(fillet)对其可靠性有很大影响，因而要求稳定地形成嵌条。
图8A表示将半导体元件1a、1b表面安装在电路基板2上的安装结构体。图8B表示填充密封树脂3前的状态，图8C表示在半导体元件1a与电路基板2之间、以及半导体元件1b与电路基板2之间填充密封树脂3后的状态。
图9A表示安装半导体元件1a、1b前的电路基板，图9B表示沿图9A的X-X线剖切的剖视图，电路基板2的安装面除了安装半导体元件1a、1b的各焊盘4之外，其整个表面均作为基底图案(ground pattern)。
在这种情况下，现行的做法是：用注射器等如图8A的箭头所示从半导体元件1a、1b全周的各位置每次分别注入少量的低粘度的密封树脂3。
专利文献1中记载了为不使注入后的密封树脂3流出到外部而在半导体元件1a、1b的周围设置隔墙来防止流出的技术。
专利文献1：日本专利特开2006-237367号公报
发明的公开
发明所要解决的技术问题
然而，现状是：以往虽在半导体元件的周围设置隔墙来控制填充后的密封树脂的形状，但在半导体元件周围每次分别注入少量密封树脂的作业非常麻烦，且无法稳定地密封半导体元件，因而要求得到改善。
本发明的目的在于提供一种密封树脂的注入作业简单且可实现用密封树脂稳定密封半导体元件的安装结构体。
解决技术问题所采用的技术方案
本发明的安装结构体中，第一半导体元件与第二半导体元件相邻地被表面安装于电路基板的上表面，其特征在于，在相邻的上述半导体元件之间的上述电路基板的图案上形成有槽部，上述槽部的一端形成到上述第一半导体元件的下方位置，上述槽部的另一端形成到上述第二半导体元件的下方位置，上述电路基板的图案与上述第一半导体元件的缝隙通过密封树脂密封，上述电路基板的图案与上述第二半导体元件的缝隙通过密封树脂密封，上述槽部的深度为将供给到上述槽部的密封树脂引导到上述电路基板的图案与上述第一半导体元件的缝隙以及上述电路基板的图案与上述第二半导体元件的缝隙所需要的深度。
此外，本发明的安装结构体中，第一半导体元件与第二半导体元件相邻地被表面安装于电路基板的上表面，其特征在于，在相邻的上述半导体元件之间的形成于上述电路基板的图案上的抗镀膜(resist)上形成有槽部，上述槽部的一端形成到上述第一半导体元件的下方位置，上述槽部的另一端形成到上述第二半导体元件的下方位置，上述电路基板的图案与上述第一半导体元件的缝隙通过密封树脂密封，上述电路基板的图案与上述第二半导体元件的缝隙通过密封树脂密封，上述槽部的深度为将供给到上述槽部的密封树脂引导到上述电路基板的图案与上述第一半导体元件的缝隙以及上述电路基板的图案与上述第二半导体元件的缝隙所需要的深度。
此外，还具有如下特征：上述密封树脂遍及上述槽部形成。
此外，还具有如下特征：上述第一半导体元件与上述第二半导体元件的间隔在5mm以内。
此外，还具有如下特征：上述槽部的方向是与上述第一半导体元件的边的方向和上述第二半导体元件的边的方向交叉的方向。
此外，还具有如下特征：形成有多条上述槽部。
发明效果
根据本发明的安装结构体，能高效率且稳定地向电路基板与被表面安装于该电路基板的半导体元件之间注入、密封树脂材料。
附图说明
图1A是本发明第一实施方式的安装结构体的俯视图。
图1B是上述实施方式的Z-Z线的剖视图。
图2A是上述实施方式的安装半导体元件前的电路基板的俯视图。
图2B是上述实施方式的J-J线的剖视图。
图3A是上述实施方式的滴下低粘度的树脂材料的第一工序图。
图3B是上述实施方式的滴下低粘度的树脂材料的第二工序图。
图4A是表示上述实施方式的电路基板的第一具体例的剖视图。
图4B是表示上述实施方式的电路基板的第二具体例的剖视图。
图5是本发明的第二实施方式的安装结构体的俯视图。
图6是本发明的第三实施方式的安装结构体的俯视图。
图7是本发明的第四实施方式的安装结构体的主要部分的剖视图。
图8A是现有的安装结构体的俯视图。
图8B是在上述现有例的安装结构体上滴下低粘度的树脂材料前的剖视图。
图8C是在上述现有例的安装结构体上滴下低粘度的树脂材料后的剖视图。
图9A是安装半导体元件前的现有的电路基板的俯视图。
图9B是图9A的X-X线的剖视图。
具体实施方式
以下，根据图1A、图1B～图7对本发明的各实施方式进行说明。
(第一实施方式)
图1A、图1B～图4A、图4B表示本发明的第一实施方式。
图1A表示将半导体元件1a、1b表面安装在电路基板2上的安装结构体。
图1B是沿图1A的Z-Z线剖切的剖视图，表示填充密封树脂3后的状态。
安装半导体元件1a、1b前的电路基板2如图2A所示，电路基板2的安装面除了安装半导体元件1a、1b的各焊盘4之外，其整个表面均作为基底图案。而且，图2B表示沿图2A的Y-Y线剖切的剖视图，半导体元件1a的安装预定位置与半导体元件1b的安装预定位置之间形成有窗6a、6b、6c、6d作为槽部7，该窗6a、6b、6c、6d将基底图案5的铜箔除去到底板2b处。
窗6a～6d(槽部7)的端部位置至少连续到装载半导体元件的位置的端部附近，更为理想的是如图1A、图1B所示连续形成到装载半导体元件的位置、即半导体元件1a、1b下。
具体而言，半导体元件1a、1b的平面形状为12mm×17mm见方，半导体1a、1b的距离为2mm。槽部7将以0.5mm为间隔的四条深度20μm、宽度0.5mm、长度3mm的槽7与半导体元件1a、1b的边形成直角。
图3A、图3B是沿图2A的J-J线剖切的放大剖视图，由于在电路基板2形成作为槽部7的窗6a～6d，因而如图3A所示，若用注射器等在窗6a～6d的点8一并滴下低粘度的密封树脂3，则滴下后的密封树脂不会沿基底图案5扩散，而是随着时间的经过扩散成以滴下的点为中心的同心圆状，并被引导到槽部7高效率地流入半导体元件1a、1b与电路基板2之间，如图3B所示沿槽部7流入半导体元件1a、1b的下方，如图1B所示能良好地密封。
在此，密封树脂3为低粘度的热固性环氧树脂，其粘度较为理想的是在10Pa·s以下，更为理想的是在5Pa·s以下，尤为理想的是在1Pa·s左右。
以上述结构为第一实施例，使用不锈钢制的喷嘴(武藏工程(株)制喷嘴、规格26的例如SN-26G-LF)在50块安装结构体的上述点8附近以25℃滴下50ml密封树脂3，观察30分钟后形成于两个半导体元件1a、1b的下表面的全周与电路基板2之间的嵌条形状。涂布的密封树脂的粘度为0.8Pa·s，在150℃下3分钟后固化。密封树脂3的量为装满半导体元件1a、1b与电路基板2之间的空间的量。
为了与本实施例1进行比较，使用如图9A和图9B所示未设置图2A、图2B所见的窗6a～6d(槽部7)的电路基板2，对在与实施例1相同的位置及相同的条件下一并滴下密封树脂3的情况进行了实验。
以下表示实施例1和比较例1的结果。实施例1和比较例1各自的两个半导体元件一起全周形成有嵌条的情况判定为○，而一部分未形成有嵌条的情况判定为×。在此，嵌条是指密封树脂从半导体元件溢出的部分、侧面的倾斜部分。
表1：
Figure GPA00001032857800051
如上所示，实施例1中，在全部的两个半导体元件1a、1b的下表面的全周上均形成有嵌条。
然而，在使用如比较例1这样的未加工窗6a～6d(槽部7)的电路基板2时，大约一半的概率是一部分未形成有嵌条。对未形成有嵌条的半导体元件1a、1b进行观察，密封树脂在两个半导体元件之间扩散、积存，密封树脂未供给到半导体元件。
由此可知，一并滴下的密封树脂容易沿作为槽部7的窗6a～6d扩散。另外，若密封树脂接触到半导体元件1a、1b，则会通过毛细管现象浸透到半导体元件的下部。
在实施例1中，半导体元件1a、1b之间的距离为2mm，但较为理想的是在5mm以内，更为理想的是在3mm以内。引导密封树脂的槽部7的条数为四条，但在半导体元件1a、1b的平面形状为12mm×17mm见方，槽部7的深度为20μm时，引导密封树脂的槽部7的宽度的总和在半导体元件1a、1b的边长的5％以上即可，较为理想的是在10％左右。
而且，将窗6a～6d(槽部7)的形状分别制成深度为5μm、10μm、30μm，其宽度为0.5mm，其长度为3mm的安装结构体作为实施例2、实施例3、实施例4，将制成深度为1μm、3μm，宽度为0.5mm，长度为3mm的安装结构体作为比较例2、比较例3，两个半导体元件一起全周形成有嵌条的情况判定为○，而一部分未形成有嵌条的情况判定为×。
表2：
实施例2中，虽发现有2块左右的安装结构体未形成有嵌条，但判定为可经得起实用。实施例3、实施例4中，全部形成有嵌条。比较例2、比较例3中无法得到可经得起实用的结果。由此意味着，窗6a～6d(槽部7)的深度如不在5μm以上便无法将密封树脂的扩散控制成沿固定方向。可以说，窗6a～6d(槽部7)起到将水引入大海的河流一般的作用，深度在5μm以下时，与河流的堤坝过低而引起决堤的状态相似。其结果是，深度需要在5μm以上。较为理想的是深度在10μm～50μm以上。
对窗6a～6d(槽部7)的深度假定为如图2B所示部分除去电路基板2的铜箔而得到目标深度的槽的尺寸进行了说明，但也可采用图4A和图4B中的任意一种。
图4A、图4B分别表示沿图2A的J-J线剖切的剖视图。在图4A中，基底图案5的上表面和窗6a～6d的底部形成有作为焊锡掩模剂的抗镀膜9，尺寸10为此时槽部7的深度。在图4B中，在基底图案5的上表面形成有抗镀膜9，而在窗6a～6d的底部未形成有抗镀膜9。此时，尺寸11为槽部7的深度。
(第二实施方式)
图5表示本发明的第二实施方式。
在第一实施方式中，由窗6a～6d形成的槽部7全部形成为与半导体元件1a、1b的边成直角，但在本第二实施方式中，设有形成与半导体元件1a、1b的边成直角的槽的窗6aa的槽部7和形成与半导体元件1a、1b的边成比直角小的角度的槽的窗6bb、6cc的槽部7。窗6aa和窗6bb、6cc的槽部7由形成于半导体元件1a、1b之间的凹部12连通。而且，为了减少滴下后的低粘度的密封树脂中未被窗6bb、6cc的槽部7捕捉到而欲如箭头13所示流出到外侧的密封树脂，根据需要在比窗6bb、6cc的槽部7更靠外侧的位置形成与半导体元件1a、1b的边成直角的窗6dd、6ee的槽部7，将尽可能多的密封树脂引导到半导体元件1a、1b。
另外，凹部12和窗6dd、6ee的槽部7也与窗6aa、6bb、6cc的槽部7一样，部分除去基底图案5的铜箔而构成。其他与第一实施方式相同。
(第三实施方式)
图6表示本发明的第三实施方式。
在第二实施方式中，窗6aa的槽部7与窗6bb、6cc的槽部7由形成于半导体元件1a、1b之间的凹部12连通，但如本第三实施方式所示，使窗6aa的槽部7和窗6bb、6cc的槽部7的各一端彼此接近地形成也是有效的。
(第四实施方式)
在上述各实施方式中，作为将密封树脂3向半导体元件1a与电路基板2的缝隙、半导体元件1b与电路基板2的缝隙引导的槽部7的窗6a～6c的槽部7和窗6aa～6cc、6dd、6ee的槽部7是除去电路基板2的基底图案5的铜箔而构成的，但如图7所示，当不除去基底图案5的铜箔而在其上面涂布形成抗镀膜9时，使用形成不涂布抗镀膜9的例如窗6a～6c的图案掩模。藉此，具有将滴下后的低粘度的密封树脂3向半导体元件1a、1b的下方引导所需的上述深度的槽部7可仅以抗镀膜9的厚度来形成。
在上述各实施方式中，对LGA(触点阵列：Land Grid Array)封装进行了说明，但本发明不限于此，还可以应用于BGA(球栅阵列：Ball Grid Array)等、其他形状的半导体元件等在电路基板上进行安装、密封的情况。此外，对半导体元件为两个的情况进行了说明，但本发明也适用于安装三个以上的多个半导体元件的情况。
工业上的可利用性
本发明的安装结构体有利于提高内置了将电路基板与半导体元件之间的缝隙用密封树脂密封的安装结构体的各种电子设备等的可靠性。

Claims (6)

1.一种安装结构体，其第一半导体元件与第二半导体元件相邻地被表面安装于电路基板的上表面，其特征在于，
在相邻的所述半导体元件之间的所述电路基板的图案上形成有槽部，
所述槽部的一端形成到所述第一半导体元件的下方位置，
所述槽部的另一端形成到所述第二半导体元件的下方位置，
所述电路基板的图案与所述第一半导体元件的缝隙通过密封树脂密封，
所述电路基板的图案与所述第二半导体元件的缝隙通过密封树脂密封，
所述槽部的深度为将供给到所述槽部的密封树脂引导到所述电路基板的图案与所述第一半导体元件的缝隙以及所述电路基板的图案与所述第二半导体元件的缝隙所需要的深度。
2.一种安装结构体，其第一半导体元件与第二半导体元件相邻地被表面安装于电路基板的上表面，其特征在于，
在相邻的所述半导体元件之间的形成于所述电路基板的图案上的抗镀膜上形成有槽部，
所述槽部的一端形成到所述第一半导体元件的下方位置，
所述槽部的另一端形成到所述第二半导体元件的下方位置，
所述电路基板的图案与所述第一半导体元件的缝隙通过密封树脂密封，
所述电路基板的图案与所述第二半导体元件的缝隙通过密封树脂密封，
所述槽部的深度为将供给到所述槽部的密封树脂引导到所述电路基板的图案与所述第一半导体元件的缝隙以及所述电路基板的图案与所述第二半导体元件的缝隙所需要的深度。
3.如权利要求1或2所述的安装结构体，其特征在于，所述密封树脂遍及所述槽部形成。
4.如权利要求1或2所述的安装结构体，其特征在于，所述第一半导体元件与所述第二半导体元件的间隔在5mm以内。
5.如权利要求1或2所述的安装结构体，其特征在于，所述槽部的方向是与所述第一半导体元件的边的方向和所述第二半导体元件的边的方向交叉的方向。
6.如权利要求1或2所述的安装结构体，其特征在于，形成有多条所述槽部。
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