CN101789857B

CN101789857B - Synchronization judging device, receiving device including the synchronizing judging device, and receiving method

Info

Publication number: CN101789857B
Application number: CN 200910002984
Authority: CN
Inventors: 林佐柏; 庄秉卓; 周裕彬
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2009-01-23
Filing date: 2009-01-23
Publication date: 2013-06-05
Anticipated expiration: 2029-01-23
Also published as: CN101789857A

Abstract

A synchronization determining apparatus in a receiving apparatus having a processing circuit for determining a synchronization state of a recovery clock, the synchronization determining apparatus comprising: a comparison unit coupled to the processing circuit for generating at least one comparison signal according to a processed signal and at least one reference value; and a judging unit, coupled to the comparing unit, for generating a synchronous state signal according to the at least one comparison signal; the synchronization state signal is used for indicating the synchronization state of the recovery clock, and the processing circuit is used for receiving and processing serial data to generate the processed signal. In addition, a receiving device and a receiving method are also disclosed.

Description

Synchronous decision maker, the receiving system that comprises this synchronous decision maker and method of reseptance

Technical field

The invention relates to a kind of synchronous judgment technology, refer to especially a kind of synchronous judgment technology of transmission system.

Background technology

System (for example uses USB/USB2.0/PCI-Express I/II/Serial-ATA I/II/DisplayPort in many numerical digit sequence transmission ... Deng the interface person) in, the transmission end is first with clock and the synthetic code signal of data, and then by receiving terminal with a clock and data recovery (Clock-DataRecovery, abbreviation CDR) circuit is analyzed this code signal, and then obtain a frequency and phase place all with the recovered clock of transmission end clock synchronous, in order to correctly decode this transmission data.

Therefore, recovered clock is the principal element that can receiving terminal be correctly decoded.Knownly utilize a clock (for example crystal clock (crystal clock)) with fixed frequency to come auxiliaryly to confirm in order to the circuit of confirming recovered clock, its confirmation mode is to weigh crystal clock number of cycles and the recovered clock number of cycles that contains within a certain period of time, then infers according to this whether the recovered clock frequency falls within the zone of reasonableness of relevant this transmission end clock.For example, Fig. 1 shows has contained x crystal clock cycle T x in certain hour P, be y and can contain the number of transmission end clock cycle in this section period P.If the number of cycles z of recovered clock in this section period P greater than y, represents that the too high need of recovered clock frequency z/ (xTx) downgrade; Otherwise, increase.

But such mode only can learn whether the recovered clock frequency falls within a zone of reasonableness, can not confirm effectively whether recovered clock is locked exactly and reach synchronous frequency and phase place.

Summary of the invention

Therefore, purpose of the present invention namely can judge the synchronous decision maker of the synchronous regime of recovered clock, the receiving system that comprises this synchronous decision maker and method of reseptance thereof exactly providing a kind of.

So receiving system of the present invention comprises: a restore circuit in order to receiving an input signal, and produces serial datum and a recovered clock; One treatment circuit is coupled to this restore circuit, processes this serial data, and produces a processed signal; Reach a synchronous decision maker, judge the synchronous regime of this recovered clock according to this processed signal and one first reference value; Wherein, this serial data includes together step mode, and this first reference value is corresponding to the numerical value of processing via this treatment circuit in this synchronous mode of at least one part.

And the synchronous decision maker of the present invention, be positioned at a receiving system with a treatment circuit, be used for judging the synchronous regime of a recovered clock, this synchronous decision maker comprises: a comparing unit, be coupled to this treatment circuit, produce at least one comparison signal according to a processed signal and at least one reference value; And a judging unit, be coupled to this comparing unit, produce a synchronous status signal according to this at least one comparison signal; Wherein, this synchronous state signal is in order to representing the synchronous regime of this recovered clock, and this treatment circuit is in order to receive and to process serial datum, to produce this processed signal.

And method of reseptance of the present invention, the synchronous regime for the clock of judging an input signal comprises: receive this input signal; Produce serial datum and a recovered clock according to this input signal; This serial data of decoding is to produce a decoded signal; Reach the synchronous regime of judging this recovered clock according to this decoded signal and at least one reference value; Wherein, this serial data includes together step mode, and this at least one reference value includes one first reference value, and this first reference value is corresponding to one first numerical value that produces through decoding in this synchronous mode of at least one part.

Description of drawings

Fig. 1 is a sequential chart, illustrates that each clock cycle number that contains within a certain period of time is different;

Fig. 2 is the calcspar of the preferred embodiment of a receiving system of the present invention;

Fig. 3 is the calcspar of another form of implementation of a preferred embodiment;

Fig. 4 is a schematic diagram, code signal is described, relatively requires and judge the relativeness of requirement; And

Fig. 5 is a schematic diagram, and the active line of the voltage controlled oscillator of this preferred embodiment is described.

The main element symbol description

1 clock data recovery circuit 54 second counters

11 voltage controlled oscillator 55 first determining devices

12 adjuster 56 second determining devices

2 transformation from serial to parallel device 57 determinants

3 decoding circuit 6 swinging of signal detecting units

4 comparing unit 7 judgement sequential devices

400 synchronous decision maker 8 period generator

5 judging unit 91 transmission ends

51 first comparator 92 decision circuit

52 second comparator 93 receiving systems

53 first counter 300 treatment circuits

Embodiment

This specification and follow-up claim are not used as distinguishing the mode of element with the difference of title, but the criterion that the difference on function is used as distinguishing with element.In the middle of specification and follow-up claims, be an open term mentioned " comprising " in the whole text, therefore should be construed to " comprise but be not limited to ".In addition, " couple " word and comprise any means that indirectly are electrically connected that directly reach at this.

About aforementioned and other technology contents, characteristics and effect of the present invention, in the following detailed description that coordinates with reference to two graphic preferred embodiments, can clearly present.

Many numerical digit sequence transmission system (for example uses USB/USB2.0/PCI-Express I/II/Serial-ATA I/II/DisplayPort ... Deng the interface person) be to send one by the transmission end to have the code signal of at least one frame (frame), and carry a plurality of synchronous modes that continue (synchronous pattern) for receiving terminal identification at the initial stage of each frame.Receiving system of the present invention is to utilize the decoding of these synchronous modes to reach the synchronous purpose of confirmation.This synchronous mode can have multiple, wherein an example is: ANSI (American National Standards Institute, ANSI) 8B/10B encoded radio D10.2 (i.e. 10 ' b0101010101) or ANSI 8B/10B encoded radio D5.2 (i.e. 10 ' b1010010101).In this example, these synchronous modes have continuous transfer characteristic.This specification be this example (being adopted by PCI-Express I/II interface) as an illustration.

In the transmission system of PCI-Express I/II interface, during from the transmission beginning, can first transmit first training symbol (Training Symbol, TS), transmit again afterwards second training symbol.And 15 code elements of the 6th code element to the in during first training symbol can transmit D10.2, and in the same manner, 15 code elements of the 6th code element to the in during second training symbol can transmit D5.2.When receiving terminal receives those training symbols, because may be synchronously or not under synchronous regime, and make the D10.2 that receives have two states (that is, 10 ' b 0101010101 and 10 ' b 1010101010), and the D5.2 that receives has six kinds of states (that is, 10 ' b 1010010101,10 ' b 0100101010,10 ' b1001010101,10 ' b 0010101010,10 ' b 0101010101 and 10 ' b 1010101010).Therefore, in order to the state that judges D10.2 and D5.2, need respectively two and six comparators (eight comparators will be arranged altogether), just can make correct judgement.Program in implementation process is identical with D5.2 due to D10.2, therefore only come the routine spirit of the present invention of saying take D10.2 as an embodiment.

Consult Fig. 2, the first embodiment of receiving system 93 of the present invention comprises the restore circuit (being a clock and data recovery (CDR) circuit 1 in the present embodiment), a treatment circuit 300 and the synchronous decision maker 400 that sequentially couple.This treatment circuit 300 comprises that a serial turns deserializer 2 and a decoding circuit 3 (is an ANSI 8B/10B decoding circuit in the present embodiment; Can be filter circuit at other embodiment, separate modulation circuit).In another form of implementation (as Fig. 3), this transformation from serial to parallel device 2 can independently go out this treatment circuit 300 and be that one of receiving system 93 comprises element.This synchronous decision maker 400 comprises that a comparing unit 4 and is coupled to the judging unit 5 of comparing unit 4.This comparing unit 4 has one first comparator 51, one second comparator 52, and this judging unit 5 has one first counter 53, one second counter 54, one first determining device 55, one second determining device 56 and a determinant 57.In one better the second embodiment, receiving system 93 of the present invention also comprises a swinging of signal detecting unit 6, a judgement sequential device 7 and a period generator 8.The relation that couples of these elements as shown in Figure 2.And the performed method of reseptance of the present invention of receiving system 93 of the present invention is in describing in the introduction to each element subsequently.

Consult Fig. 4, also carry a synchronous mode ending message after inherent these synchronous modes of each frame of this code signal, and this code signal is to be in idle state not transmitting image duration.At the second embodiment, so for effective indication synchronous mode position, this swinging of signal detecting unit 6 makes T between a comparable period that relatively requires _cmpTo originate in this code signal to transfer swing to by idle, and when ending to detect this synchronous mode ending message.

Because transmit the initial stage of these synchronous modes, receiving system 93 is not yet reached synchronously usually, so these judgement sequential device 7 meetings T during finding that this switching point that relatively requires (referring to rising edge here) is rear to wait for one section ignorance _Ignore, then make a judgement require to keep T during the judgement of one section high potential _JudgeAnd be to make this judgement require to be in electronegative potential in all the other times.Wherein, T during judgement _JudgeBe equivalent to the K of the signal period that this period generator 8 produces doubly.It should be noted that T during ignorance _IgnoreWith T during judgement _JudgeThe total value that adds must be less than T between this comparable period _cmp, to avoid T during this judgement _JudgeOverlap with the delivery time of this synchronous mode ending message.

Fig. 2 is consulted in recurrence, this clock data recovery circuit 1 receives an input signal (referring in the present embodiment this code signal), and produce according to this serial datum and a recovered clock, and this recovered clock can be used as this transformation from serial to parallel device 2, this decoding circuit 3, these

comparators

51,52 and these

counters

53,54 operating basis, certainly, also can produce a clock signal for above-mentioned circuit running by other circuit in addition.

Clock data recovery circuit 1 can be adopted various ways and realize, and this preferred embodiment is with a voltage controlled oscillator 11 (Voltage Controlled Oscillator, VCO) and one adjuster 12 is isolated this recovered clock, and this voltage controlled oscillator 11 has a plurality of active lines as shown in Figure 5.Suppose that transmission end 91 is to send this code signal according to a transmission end clock, and transmission end clock frequency F _TThe crystal clock frequency F that produces with voltage controlled oscillator 11 _xRatio be RA _T, recovered clock frequency F _RWith crystal clock frequency F _xRatio be RA _RAdjust when recovered clock frequency FR is subjected to voltage controlled oscillator 11, and make adjuster 12 measure ratio R A _RHigher than ratio R A _T, represent recovered clock frequency F _RToo high.As ratio R A _RLower than ratio R A _T, represent recovered clock frequency F _RToo low.

And adjuster 12 is known ratio R A _R, RA _TRelativeness after, the alignment processing mode has four.First mode is: adjuster 12 directly selects wherein a kind of suitable active line of voltage controlled oscillator 11 to make recovered clock accelerating ated test to the ideal frequency value.Second mode is: the decision circuit 92 of one outside notified the ratio relativeness by adjuster 12, then selects wherein a kind of suitable active line of voltage controlled oscillator 11 to adjust by this decision circuit 92.The 3rd mode is: adjuster 12 is notified synchronous decision maker 400 with the ratio relativeness, adjusts to be selected a suitable active line by synchronous decision maker 400.The 4th mode is: if voltage controlled oscillator 11 can't adjust the recovered clock of approaching transmission end clock frequency FT according to arbitrary active line, adjuster 12 can send a frequency conversion requirement to transmission end 91.Then, transmission end 91 increases or downgrades transmission end clock frequency F more according to this _T, to the working range of the active line that falls into voltage controlled oscillator 11 and the recovered clock of the frequency approaches of vibrating.

It is 10 parallel data that this transformation from serial to parallel device 2 is converted to a bit width with this serial data.Then, this decoding circuit 3 is processed parallel data to produce a processed signal, if this decoding circuit 3 is the ANSI8B/10B decoding circuit, this processed signal is that a bit width is 8 decoded signal.In addition, when this recovered clock is reached when synchronous, this serial data includes together step mode (D10.2 i.e. 10 ' b0101010101), and one first reference value (8 ' h4A) is one first decoded signal in this synchronous mode, and one second reference value (8 ' hB5) is one second decoded signal in this synchronous mode.In the present embodiment, this synchronous mode is 10 ' b0101010101, and its ANSI 8B/10B decode value is actually the first reference value (8 ' h4A); But consider because of the accepting state difference that causes of drift, so also the decode value of 10 ' b1010101010 (i.e. the second reference value, 8 ' hB5) is included in circuit design.Certainly, can only utilize the first reference value (8 ' h4A) or the second reference value (8 ' hB5) can complete purpose of the present invention.

This comparing unit 4 is judged the synchronous regime of this recovered clock according to this decoded signal and the first reference value or the second reference value, and produces one first comparison signal or one second comparison signal that represents result of determination.This judging unit 5 produces based on this first comparison signal or this second comparison signal the synchronous state signal that a generation is expressed as synchronous regime.

T between the comparable period _cmpIn, if this first comparator 51 finds that this decoded signal is different from the first reference value (8 ' h4A), produce this first comparison signal; This first counter 53 is adjusted one first stored accumulating values according to this first comparison signal, and in this embodiment, the each adjustment is that it is added up 1.If this second comparator 52 finds that this decoded signal is different from the second reference value (8 ' hB5), produce this second comparison signal; This second counter 54 also can be adjusted one second stored accumulating values according to this second comparison signal, and in this embodiment, the each adjustment is that it is added up 1.

Then, T during this judgement _JudgeIn, these

determining devices

55,56 are inspected respectively these

counters

53,54 result, and then make this determinant 57 (realizing with door (AND) with in the present embodiment) output represent the synchronous state signal of synchronous regime.In the situation that this first determining device 55 inspect learn this first counter 53 the first accumulating values less than a critical value N, produce first a judgement information in order to the synchronous regime that represents this recovered clock, reach synchronous regime with demonstration.In the situation that this second determining device 56 inspect learn this second counter 54 the second accumulating values less than critical value N, produce second a judgement information in order to the synchronous regime that represents this recovered clock, reach synchronous regime with demonstration.

Then, determinant 57 can produce the synchronous state signal (1 value) that synchronous regime is reached in representative according to this first judgement information and/or this second judgement information, at this moment, the frequency of this recovered clock and phase place all with the transmission end clock synchronous.When wherein any one was not less than this critical value N, this synchronous state signal is represented 0 value of not reaching synchronous regime, and namely this recovered clock is asynchronous in the transmission end clock.In addition, in another form of implementation, determinant 57 also can this first accumulating values of direct basis and this second accumulating values judge the synchronous regime of this recovered clock, and omit these determining

devices

55,56.

More specifically, find that when this synchronous decision maker 400 detects this decoded signal is same as this first/the second reference value, tendency judges that this recovered clock is in synchronous regime.When not identical, tendency judges that this recovered clock is in asynchronous regime.

It should be noted that this synchronous decision maker 400 also can replace with other forms of implementation, for example: the mode that applies in contrast with the previous embodiment.So, also can reach identical effect.At this moment, 57 need of this determinant with one or the door (an OR gate) realized.Certainly, the visual actual needs of this critical value N and transferring.

Apply on the contrary mode that is: when this first comparator 51 finds that these decoded signals are same as this first reference value, this first counter 53 can add up, and in the situation that this first determining device 55 inspect learn this first counter 53 output greater than a critical value M, this first judgement information shows and reaches synchronous regime.In like manner, can obtain this second judgement information by this second comparator 52, this second counter 54 and this second determining device 56.

Above-mentioned inference is reached synchronous reason: if almost can solve the decoding of correct synchronous mode, must be to reach the frequency locking state so, just can be correctly decoded because have this recovered clock frequency transmission end clock that coincide only.Moreover this has also hinted reaching of phase locked state, if because during the switching point of this recovered clock (one of rising edge or trailing edge) betides the conversion (transition) of this decoded signal, will cause decoding error.

And the desired bit error rate (bit error rate) of this synchronous decision maker 400 can be by T during this judgement of adjustment _JudgeN sets with this critical value.For example: when the bit error rate that requires is 2 ^-9=(10N)/(T/10t _bit), represent every T/10t _bitIndividual input is allowed at most 10N error bit, wherein t in the position _bitBe the inverse of code signal bit rate, 10 refer to the bit width of this parallel data.

In addition, what must illustrate is again, in the DisplayPort system, code signal does not carry the synchronous mode ending message, but see through an accessory channel (auxiliary channel by transmission end 91, be called for short the AUX passage) inform whether receiving system 93 is just transmitting synchronous mode (being equivalent to the relatively requirement that this swinging of signal detecting unit 6 sends) at present, and receiving system 93 also sees through this accessory channel and transmits its genlocing state to the transmission end, to transmit the foundation of synchronous mode as the transmission end.So, but when being applied to DisplayPort system footpath province, the present invention omits swinging of signal detecting unit 6.

And it should be noted that although this preferred embodiment is to explain with ANSI 8B/10B code signal and ANSI8B/10B decoding circuit, invention scope is not limited to this, also has code signal and the homographic solution decoding circuit of synchronous mode applicable to other.In addition, note that the more synchronous decision maker 400 in above-described embodiment is can be independently for receiving system 93.It is important to note that in another embodiment, more decoding circuit 3 can be incorporated in synchronous decision maker 400 and implement.

In sum, receiving system 93 of the present invention is with this synchronous decision maker 400 T during each section judgement _JudgeDetection receives the number of times that belongs to or do not belong to the decoded signal of synchronous mode, thereby can effectively learn frequency locking and the phase locked state of recovered clock, therefore really can reach purpose of the present invention.

The above person of thought, it is only preferred embodiment of the present invention, when not limiting scope of the invention process with this, the simple equivalence of namely generally doing according to the present patent application the scope of the claims and invention description content changes and modifies, and all still remains within the scope of the patent.

Claims

1. A receiving device, comprising:

A recovery circuit for receiving an input signal and generating a serial data and a recovered clock;

a processing circuit, coupled to the recovery circuit, processes the serial data and generates a processed signal; and

A synchronization judging device, judging the synchronization state of the recovered clock according to the processed signal and a first reference value;

Wherein, the serial data includes a synchronous pattern, and the first reference value corresponds to at least a part of the synchronous pattern values processed by the processing circuit, and

Wherein, the synchronous judging device includes:

a first comparator, judging the synchronization state of the recovered clock according to the processed signal and the first reference value;

a first counter for adjusting a stored first accumulated value according to a result of the synchronization status of the recovered clock determined by the first comparator; and

A first judging device generates a first judging information according to the first accumulated value.

2. The receiving device as claimed in claim 1, wherein the processing circuit comprises a decoding circuit, and the processed signal is a decoded signal.

3. The receiving device as claimed in claim 2, wherein when the synchronization determining means detects that the decoded signal is identical to the first reference value, it determines that the recovered clock is in a synchronous state.

4. The receiving device as claimed in claim 2, wherein the processing circuit further comprises a serial-to-parallel converter.

5. The receiving device as claimed in claim 2, wherein the decoding circuit is an ANSI8B/10B decoding circuit, and the synchronization pattern is 10'b0101010101.

6. The receiving apparatus as claimed in claim 4, wherein the deserializer converts the serial data into parallel data with a bit width of 10.

7. The receiving device according to claim 1, wherein the synchronization pattern is 10'b0101010101, and the first reference value is 8'h4A.

8. The receiving device according to claim 1, wherein the synchronization pattern is 10'b0101010101, and the first reference value is 8'hB5.

9. The receiving device as claimed in claim 1, wherein, when the first comparator finds that the processed signal is different from the first reference value, the first counter will be accumulated, and when the first judge checks that When the output of the first counter is known to be less than a critical value, the first judging information indicates that the synchronization state has been reached.

10. The receiving device as claimed in claim 1, wherein when the first comparator finds that the processed signal is the same as the first reference value, the first counter will be accumulated, and when the first judge checks that When it is known that the output of the first counter is greater than a critical value, the first judging information indicates that the synchronization state has been reached.

11. The receiving device as claimed in claim 1, wherein the synchronization determination device further comprises:

a second comparator for determining the synchronization state of the recovered clock according to the processed signal and a second reference value;

a second counter for adjusting a stored second accumulative value according to a result of the synchronization state of the recovered clock determined by the second comparator;

a second judging device, generating a second judging information according to the second accumulated value; and

A determiner, generating a synchronization state signal according to the first determination information and the second determination information;

Wherein, the second reference value corresponds to at least a part of values processed by the processing circuit in the synchronous mode, and the second judging information is used to indicate the synchronous state of the recovered clock judged by the second judging unit .

12. The receiving device as claimed in claim 1, wherein the processing circuit is an ANSI8B/10B decoding circuit, and the receiving device further comprises a serial-to-parallel converter, which converts the serial data into a bit width of 10 The parallel data is sent to the processing circuit, and the bit width of the processed signal output by the processing circuit is 8.

13. A synchronization determining device, located in a receiving device with a processing circuit, for determining the synchronization status of a recovered clock, the synchronization determining device comprising:

A comparison unit, coupled to the processing circuit, generates at least one comparison signal according to a processed signal and at least one reference value; and

A judging unit, coupled to the comparing unit, generates a synchronization status signal according to the at least one comparing signal;

Wherein, the synchronization state signal is used to indicate the synchronization state of the recovered clock, and the processing circuit is used to receive and process a serial data to generate the processed signal, and

Wherein, the serial data includes a synchronous pattern, and the at least one reference value corresponds to a value processed by the processing circuit in at least a part of the synchronous pattern.

14. The synchronization judging device as claimed in claim 13, wherein the comparing unit further comprises:

a first comparator, generating a first comparison signal according to the processed signal and a first reference value; and

a second comparator, generating a second comparison signal according to the processed signal and a second reference value;

Wherein, the serial data includes a synchronous pattern, and the first reference value corresponds to a first value processed by the processing circuit in at least a part of the synchronous pattern, and the second reference value corresponds to at least a part of A second value processed by the processing circuit in the synchronous mode.

15. The synchronization judging device as claimed in claim 14, wherein the judging unit further comprises:

a first counter, accumulating according to the first comparison signal;

a second counter, accumulating according to the second comparison signal;

a first judging device, generating a first judging information according to the accumulated value of the first counter and a critical value;

a second judging device, generating a second judging information according to the accumulated value of the second counter and the critical value; and

A determiner generates the synchronization state signal according to the first determination information and the second determination information.

16. The synchronization determining device as claimed in claim 13, wherein when the synchronization determining device detects that the processed signal is identical to one of the at least one reference value, it determines that the recovered clock is in a synchronous state.

17. A receiving method for determining the synchronization state of a clock of an input signal, comprising the following steps:

receiving the input signal;

generating a serial data and a recovered clock according to the input signal;

decoding the serial data to generate a decoded signal; and

determining the synchronization state of the recovered clock according to the decoded signal and at least one reference value;

Wherein, the serial data includes a synchronous pattern, and the at least one reference value includes a first reference value, and the first reference value corresponds to a first value generated by decoding in at least a part of the synchronous pattern, and

The step of determining the synchronization state of the recovered clock also includes:

comparing the decoded signal with the first reference value to accumulate a first accumulated value;

generating a first judgment message according to the first accumulated value; and

The synchronization state of the recovered clock is judged according to the first judgment information.

18. The receiving method as claimed in claim 17, wherein the step of determining the synchronization state of the recovered clock further comprises:

comparing the decoded signal with a second reference value to accumulate a second accumulated value;

Wherein, the at least one reference value further includes the second reference value, and the second reference value corresponds to a second value generated by decoding in at least a part of the synchronization pattern.

19. The receiving method as claimed in claim 18, wherein the step of determining the synchronization state of the recovered clock further comprises:

generating a second determination information according to the second accumulated value; and

The synchronization state of the recovered clock is determined according to the first determination information and the second determination information.