CN101789857A - Synchronization determining apparatus, receiving apparatus including the same, and receiving method - Google Patents

Abstract

A synchronization determining apparatus in a receiving apparatus having a processing circuit for determining a synchronization state of a recovery clock, the synchronization determining apparatus comprising: a comparison unit coupled to the processing circuit for generating at least one comparison signal according to a processed signal and at least one reference value; and a judging unit, coupled to the comparing unit, for generating a synchronous state signal according to the at least one comparison signal; the synchronization state signal is used for indicating the synchronization state of the recovery clock, and the processing circuit is used for receiving and processing serial data to generate the processed signal. In addition, a receiving device and a receiving method are also disclosed.

Description

Synchronization judging device, receiving device including the synchronizing judging device, and receiving method

technical field

The present invention relates to a synchronous judging technology, in particular to a synchronous judging technology of a transmission system.

Background technique

In many digital serial transmission systems (such as those using interfaces such as USB/USB2.0/PCI-Express I/II/Serial-ATA I/II/DisplayPort...), the transmitting end first synthesizes clock and data A coded signal, and then the receiving end analyzes the coded signal with a Clock-Data Recovery (CDR) circuit, and then obtains a recovered clock whose frequency and phase are synchronized with the clock of the transmitting end, so as to correctly decode The transfer data.

Therefore, the recovered clock is the main factor for correct decoding at the receiving end. Conventional circuits for confirming the recovered clock use a clock with a fixed frequency (such as a crystal clock) to assist the confirmation. The confirmation method is to measure the number of crystal clock cycles and the recovered clock period covered within a certain period of time. number, and then infer whether the frequency of the recovered clock falls within a reasonable range related to the clock at the transmitting end. For example, FIG. 1 shows that x crystal clock periods Tx are covered within a certain period of time P, and the number of clock periods at the transmitting end that can be covered within this period of time P is y. If the period number z of the recovered clock within the period P is greater than y, it means that the recovered clock frequency z/(xTx) is too high and needs to be lowered; otherwise, it should be increased.

However, this method can only know whether the frequency of the recovered clock falls within a reasonable range, but cannot effectively confirm whether the recovered clock is accurately locked to achieve a synchronized frequency and phase.

Contents of the invention

Therefore, the object of the present invention is to provide a synchronization determining device capable of accurately determining the synchronization state of the recovered clock, a receiving device including the synchronization determining device and a receiving method thereof.

Therefore, the receiving device of the present invention includes: a recovery circuit for receiving an input signal and generating a serial data and a recovery clock; a processing circuit coupled to the recovery circuit for processing the serial data and generating a processed signal; and a synchronous judging device, judging the synchronous state of the recovered clock according to the processed signal and a first reference value; wherein, the serial data includes a synchronous pattern, and the first reference value corresponds to Values processed by the processing circuit in at least a part of the synchronous pattern.

The synchronization determination device of the present invention is located in a receiving device with a processing circuit for determining the synchronization state of a recovered clock. The synchronization determination device includes: a comparison unit, coupled to the processing circuit, based on a processed signal generating at least one comparison signal with at least one reference value; and a judging unit, coupled to the comparison unit, generating a synchronization state signal according to the at least one comparison signal; wherein, the synchronization state signal is used to represent the synchronization state of the recovered clock , and the processing circuit is used to receive and process a serial data to generate the processed signal.

And the receiving method of the present invention is used to determine the synchronous state of a clock of an input signal, comprising: receiving the input signal; generating a serial data and a recovered clock according to the input signal; decoding the serial data to generate a decoded signal; and determining the synchronous state of the recovered clock according to the decoded signal and at least one reference value; wherein, the serial data includes a synchronous pattern, and the at least one reference value includes a first reference value, and the first reference value corresponds to A first value generated by decoding in at least a portion of the synchronization pattern.

Description of drawings

Fig. 1 is a timing diagram, illustrating that the number of each clock cycle covered within a certain period of time is different;

Fig. 2 is a block diagram of a preferred embodiment of the receiving device of the present invention;

Fig. 3 is a block diagram of another embodiment of a preferred embodiment;

Fig. 4 is a schematic diagram illustrating the relative relationship between coded signals, comparison requirements and judgment requirements; and

FIG. 5 is a schematic diagram illustrating the working lines of the VCO of the preferred embodiment.

Description of main component symbols

1 clock data recovery circuit 54 second counter

11 Voltage Controlled Oscillator 55 First Judgment Device

12 Adjuster 56 Second Judger

2 Serial to Parallel Converter 57 Decider

3 Decoding Circuit 6 Signal Swing Detection Unit

4 Comparison unit 7 Judgment sequencer

400 Synchronous Judgment Device 8 Period Generator

5 Judgment unit 91 Transmitter

51 first comparator 92 decision circuit

52 Second comparator 93 Receiver

53 first counter 300 processing circuit

Detailed ways

This description and subsequent patent applications do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The "comprising" mentioned throughout the specification and subsequent claims is an open term, so it should be interpreted as "including but not limited to". Otherwise, the term "coupled" includes any direct and indirect means of electrical connection.

The foregoing and other technical contents, features and functions of the present invention will be clearly presented in the following detailed description of two preferred embodiments with reference to the drawings.

Many digital serial transmission systems (such as those using interfaces such as USB/USB2.0/PCI-Express I/II/Serial-ATA I/II/DisplayPort...) are sent by the transmitting end with at least one frame (frame) Encode the signal and carry a plurality of consecutive synchronous patterns at the beginning of each frame for identification by the receiving end. The receiving device of the present invention uses the decoding of the synchronization patterns to achieve the purpose of confirming the synchronization. The synchronization mode can have many kinds, one of which is: ANSI (American National Standards Institute, American National Standards Institute) 8B/10B code value D10.2 (ie 10'b0101010101) or ANSI 8B/10B code value D5.2 ( ie 10'b1010010101). In this example, the synchronous patterns have continuous conversion characteristics. In this manual, this example (used for PCI-Express I/II interface) is used as an illustration.

In the transmission system of the PCI-Express I/II interface, from the beginning of the transmission, the first training symbol (Training Symbol, TS) will be transmitted first, and then the second training symbol will be transmitted. And in the 6th symbol to the 15th symbol in the first training symbol period, D10.2 will be transmitted, and similarly, in the 6th symbol to the 15th symbol in the second training symbol period symbols, D5.2 will be transmitted. When the receiving end receives these training symbols, because it may be in a synchronized or unsynchronized state, the received D10.2 will have two states (that is, 10'b 0101010101 and 10'b 1010101010 ), and the received D5.2 will have six states (that is, 10'b 1010010101, 10'b 0100101010, 10'b1001010101, 10'b 0010101010, 10'b 0101010101 and 10'b 1010101010). Therefore, two and six comparators (eight comparators in total) are required for judging the states of Dt 0.2 and D5.2, respectively, in order to make a correct judgment. Since the procedures of D10.2 and D5.2 are the same during implementation, only D10.2 is taken as an example to illustrate the spirit of the present invention.

Referring to Fig. 2, the first embodiment of the receiving device 93 of the present invention comprises a recovery circuit (a clock data recovery (CDR) circuit 1 in this embodiment), a processing circuit 300 and a synchronous determination coupled in sequence device 400 . The processing circuit 300 includes a serial-to-parallel converter 2 and a decoding circuit 3 (in this embodiment, it is an ANSI 8B/10B decoding circuit; in other embodiments, it can be a filter circuit, a demodulation circuit). In another implementation form (as shown in FIG. 3 ), the deserializer 2 can be independent of the processing circuit 300 and be an included component of the receiving device 93 . The synchronization determination device 400 includes a comparison unit 4 and a determination unit 5 coupled to the comparison unit 4 . This comparison unit 4 has a first comparator 51, a second comparator 52, and this judging unit 5 has a first counter 53, a second counter 54, a first judger 55, a second judger 56 and A determiner 57. In a preferred second embodiment, the receiving device 93 of the present invention further includes a signal swing detection unit 6 , a judging sequencer 7 and a period generator 8 . The coupling relationship of these elements is shown in FIG. 2 . The receiving method of the present invention executed by the receiving device 93 of the present invention will be described later in the introduction of each component.

Referring to FIG. 4 , each frame of the encoded signal carries a synchronous pattern end message after the synchronous patterns, and the encoded signal is in an idle state during the non-transmission frame period. In the second embodiment, in order to effectively indicate the position of the synchronous mode, the signal swing detection unit 6 makes a comparison period Tcmp of a comparison requirement start when the encoded signal changes from idle to swing, and end when the synchronous mode is detected to end information.

Because the receiving device 93 has not yet reached synchronization at the initial stage of transmitting these synchronous patterns, the judgment sequencer 7 will wait for a period of neglect T _ignore after finding the switching point (referred to here as the rising edge) of the comparison request, and then make a The judgment requirement is maintained at a high potential for a judgment period T _judge ; and the judgment requirement is kept at a low potential for the rest of the time. Wherein, the judgment period T _judge is equivalent to K times the period of the signal generated by the period generator 8 . It should be noted that the total value of the ignore period T _ignore and the judgment period T _judge must be smaller than the comparison period T _cmp , so as to avoid the overlapping of the transmission time of the judgment period T _judge and the synchronous mode end information.

Referring back to Fig. 2, the clock data recovery circuit 1 receives an input signal (referring to the encoded signal in this embodiment), and generates a serial data and a recovered clock accordingly, and the recovered clock can be used as the serial The operating basis of the parallelizer 2, the decoding circuit 3, the comparators 51, 52 and the counters 53, 54, of course, can also be generated by other circuits for the operation of the above-mentioned circuits.

The clock data recovery circuit 1 can be implemented in multiple ways, and the present preferred embodiment separates the recovered clock with a voltage-controlled oscillator 11 (Voltage Controlled Oscillator, VCO) and a regulator 12, and the voltage-controlled The oscillator 11 has a plurality of operating lines as shown in FIG. 5 . Assuming that the transmitting end 91 sends the encoded signal according to a transmitting end clock, and the ratio of the transmitting end clock frequency F _T to the crystal clock frequency F _x generated by the voltage-controlled oscillator 11 is R _T , the recovered clock frequency F _R and the crystal The ratio of the clock frequency _Fx is _RAR . When the recovered clock frequency FR is adjusted by the voltage-controlled oscillator 11 such that the ratio R _R measured by the regulator 12 is higher than the ratio R _T , it means that the recovered clock frequency _FR is too high. When the ratio R _R is lower than the ratio R _T , it means that the recovered clock frequency F _R is too low.

After the adjuster 12 learns the relative relationship between the ratios R _R and R _T , there are four corresponding processing methods. The first method is: the regulator 12 directly selects one of the appropriate working lines of the voltage-controlled oscillator 11 to speed up the convergence of the recovered clock to an ideal frequency value. The second method is: the regulator 12 informs an external decision-making circuit 92 of the ratio relative relationship, and then the decision-making circuit 92 selects one of the appropriate working lines of the voltage-controlled oscillator 11 for adjustment. The third method is: the adjuster 12 notifies the relative ratio relationship to the synchronization determination device 400, so that the synchronization determination device 400 selects an appropriate working line for adjustment. The fourth method is: if the voltage-controlled oscillator 11 cannot adjust a recovered clock close to the clock frequency FT of the transmitting end according to any working line, the adjuster 12 sends a frequency conversion request to the transmitting end 91 . Then, the transmitting end 91 increases or decreases the frequency F _T of the transmitting end clock accordingly, so as to fall into the working range of the working line of the voltage-controlled oscillator 11 and oscillate a recovered clock with a similar frequency.

The serial-to-parallelizer 2 converts the serial data into parallel data with a bit width of 10. Next, the decoding circuit 3 processes the parallel data to generate a processed signal. If the decoding circuit 3 is an ANSI8B/10B decoding circuit, the processed signal is a decoded signal with a bit width of 8. In addition, when the recovered clock is synchronized, the serial data contains a synchronous pattern (D10.2 ie 10'b0101010101), and a first reference value (8'h4A) is a first decoding in the synchronous pattern signal, a second reference value (8'hB5) is a second decoded signal in the sync mode. In this embodiment, the synchronization pattern is 10'b0101010101, and its ANSI 8B/10B decoded value is actually the first reference value (8'h4A); but considering the difference in receiving status caused by drift, 10' The decoded value of b1010101010 (ie, the second reference value, 8'hB5) is incorporated into the circuit design. Of course, the object of the present invention can be accomplished by using only the first reference value (8'h4A) or the second reference value (8'hB5).

The comparison unit 4 determines the synchronization state of the recovered clock according to the decoded signal and the first reference value or/and the second reference value, and generates a first comparison signal or/and a second comparison signal representing the determination result. The judging unit 5 generates a synchronization status signal representing a synchronization status based on the first comparison signal and/or the second comparison signal.

During the comparison period T _cmp , if the first comparator 51 finds that the decoded signal is different from the first reference value (8'h4A), then the first comparison signal is generated; the first counter 53 calculates according to the first comparison signal A stored first accumulated value is adjusted, and in this embodiment, it is incremented by 1 for each adjustment. If the second comparator 52 finds that the decoded signal is different from the second reference value (8'hB5), it will generate the second comparison signal; the second counter 54 will also adjust a stored value according to the second comparison signal. The second accumulated value, in this embodiment, is incremented by 1 for each adjustment.

Then, in the judgment period _Tjudge , the judgers 55, 56 check the results of the counters 53, 54 respectively, and then make the judger 57 (realized by an AND gate (AND) in this embodiment) output Synchronization status signal representing synchronization status. When the first judging unit 55 checks and finds that the first accumulated value of the first counter 53 is less than a critical value N, a first judging message is generated to indicate the synchronous state of the recovered clock, to show that the first accumulated value of the first counter 53 has reached sync status. When the second judging unit 56 checks and finds that the second accumulated value of the second counter 54 is less than the critical value N, a second judging message is generated to represent the synchronous state of the recovered clock to show that the synchronous state is reached. state.

Next, the determiner 57 will generate a synchronization state signal (value 1) representing a synchronization state according to the first judgment information and/or the second judgment information. At this time, the frequency and phase of the recovered clock are synchronized with the clock at the transmitting end . When any one of them is not less than the critical value N, the synchronization status signal exhibits a value of 0 representing a failure to achieve synchronization, that is, the recovered clock is not synchronized with the clock at the transmitting end. In addition, in another implementation form, the determiner 57 can also directly determine the synchronization state of the recovered clock according to the first accumulated value and the second accumulated value, and the determiners 55 and 56 are omitted.

More specifically, when the synchronization determining device 400 detects that the decoded signal is identical to the first/second reference value, it tends to determine that the recovered clock is in a synchronous state. If not, it tends to determine that the recovered clock is in an asynchronous state.

It should be noted that the synchronization determination device 400 can also be replaced by other implementation forms, for example: an implementation manner opposite to the above-mentioned embodiment. In this way, the same effect can also be achieved. At this time, the determiner 57 needs to be realized by an OR gate. Of course, the critical value N can be adjusted according to actual needs.

The opposite way of doing things is: when the first comparator 51 finds that the decoded signal is the same as the first reference value, the first counter 53 will be accumulated, and the first counter 55 will check to know the first counter When the output of 53 is greater than a critical value M, the first judging information indicates that the synchronization state has been reached. Similarly, the second determination information can be obtained through the second comparator 52 , the second counter 54 and the second determination unit 56 .

The reason for the above inference to achieve synchronization is that if the correct synchronization mode decoding can be almost solved, then the frequency locking state must be achieved, because only when the recovered clock frequency matches the transmitting end clock can it be decoded correctly. Furthermore, this also implies the achievement of a phase-locked state, because if the switching point (either rising edge or falling edge) of the recovered clock occurs during a transition of the decoded signal, decoding errors will result.

Moreover, the expected bit error rate of the synchronization judging device 400 can be set by adjusting the judging period _Tjudge and the threshold N. For example: when the required bit error rate is 2 ^-9 = (10N)/(T/10t _bit ), it means that a maximum of 10N error bits are allowed in every T/10t _bit input bit, where t _bit is the bit rate of the encoded signal Inverse, 10 refers to the bit width of the parallel data.

In addition, it must be further explained that in the DisplayPort system, the coded signal does not carry the end information of the synchronous mode, but the transmitting end 91 informs the receiving device 93 whether it is currently The synchronous mode is being transmitted (equivalent to the comparison request issued by the signal swing detection unit 6), and the receiving device 93 also transmits its genlock status to the transmitting end through the auxiliary channel, as the basis for transmitting the synchronous mode at the transmitting end. Therefore, when the present invention is applied to the DisplayPort system, the signal swing detection unit 6 can be omitted.

And it is worth noting that although the present preferred embodiment is illustrated with ANSI 8B/10B coded signal and ANSI8B/10B decoding circuit, the scope of the invention is not limited thereto, and it is also applicable to other coded signals and coded signals with synchronous patterns Corresponding decoding circuit. In addition, please note that the synchronization determining device 400 in the above embodiment can be independent from the receiving device 93 . It should also be noted that in another embodiment, the decoding circuit 3 can be further incorporated into the synchronization determining device 400 for implementation.

In summary, the receiving device 93 of the present invention uses the synchronization judging device 400 to detect the number of times of receiving decoded signals belonging to or not belonging to the synchronous mode in each judgment period T _judge , so that the frequency locking and sum of the recovered clock can be effectively known. phase-locked state, so the purpose of the present invention can really be achieved.

But the above-mentioned person is only preferred embodiment of the present invention, when can not limit the scope of the present invention implementation with this, promptly all the simple equivalent changes and modifications that are done according to the patent scope of the present invention and the content of the description of the invention, All still belong to the scope that the patent of the present invention covers.

Claims (22)

1. A receiving device, comprising: A recovery circuit for receiving an input signal and generating a serial data and a recovered clock; a processing circuit, coupled to the recovery circuit, processes the serial data and generates a processed signal; and A synchronization judging device, judging the synchronization state of the recovered clock according to the processed signal and a first reference value; Wherein, the serial data includes a synchronous pattern, and the first reference value corresponds to at least a part of the synchronous pattern values processed by the processing circuit. 2. The receiving device as claimed in claim 1, wherein the processing circuit comprises a decoding circuit, and the processed signal is a decoded signal. 3. The receiving device as claimed in claim 2, wherein when the synchronization determining means detects that the decoded signal is identical to the first reference value, it determines that the recovered clock is in a synchronous state. 4. The receiving device as claimed in claim 2, wherein the processing circuit further comprises a serial-to-parallel converter. 5. The receiving device as claimed in claim 2, wherein the decoding circuit is an ANSI 8B/10B decoding circuit, and the synchronization pattern is 10'b0101010101. 6. The receiving apparatus as claimed in claim 4, wherein the deserializer converts the serial data into parallel data with a bit width of 10. 7. The receiving device according to claim 1, wherein the synchronization pattern is 10'b0101010101, and the first reference value is 8'h4A. 8. The receiving device according to claim 1, wherein the synchronization pattern is 10'b0101010101, and the first reference value is 8'hB5. 9. The receiving device as claimed in claim 1, wherein the synchronization determining means comprises: a first comparator, judging the synchronization state of the recovered clock according to the processed signal and the first reference value; a first counter for adjusting a stored first accumulated value according to a result of the synchronization status of the recovered clock determined by the first comparator; and A first judging device generates a first judging information according to the first accumulated value. 10. The receiving device as claimed in claim 9, wherein, when the first comparator finds that the processed signal is different from the first reference value, the first counter will be accumulated, and when the first judge checks that When the output of the first counter is known to be less than a critical value, the first judging information indicates that the synchronization state has been reached. 11. The receiving device as claimed in claim 9, wherein, when the first comparator finds that the processed signal is the same as the first reference value, the first counter will be accumulated, and the first determiner checks that When it is known that the output of the first counter is greater than a critical value, the first judging information indicates that the synchronization state has been reached. 12. The receiving device as claimed in claim 9, wherein the synchronization determination device further comprises: a second comparator for determining the synchronization state of the recovered clock according to the processed signal and a second reference value; a second counter for adjusting a stored second accumulative value according to a result of the synchronization state of the recovered clock determined by the second comparator; a second judging device, generating a first and second judging information according to the second accumulated value; and A determiner, generating a synchronization state signal according to the first determination information and the second determination information; Wherein, the second reference value corresponds to at least a part of values processed by the processing circuit in the synchronous mode, and the second judging information is used to indicate the synchronous state of the recovered clock judged by the second judging unit . 13. The receiving device as claimed in claim 1, wherein the processing circuit is an ANSI 8B/10B decoding circuit, and the receiving device further comprises a serial-to-parallel converter, which converts the serial data into a bit width of The parallel data of 10 is sent to the processing circuit, and the bit width of the processed signal output by the processing circuit is 8. 14. A synchronization determining device, located in a receiving device with a processing circuit, for determining the synchronization status of a recovered clock, the synchronization determining device comprising: A comparison unit, coupled to the processing circuit, generates at least one comparison signal according to a processed signal and at least one reference value; and A judging unit, coupled to the comparing unit, generates a synchronization status signal according to the at least one comparing signal; Wherein, the synchronization status signal is used to indicate the synchronization status of the recovered clock, and the processing circuit is used to receive and process a serial data to generate the processed signal. 15. The synchronization judging device as claimed in claim 14, wherein the comparison unit further comprises: a first comparator, generating a first comparison signal according to the processed signal and a first reference value; and a second comparator, generating a second comparison signal according to the processed signal and a second reference value; Wherein, the serial data includes a synchronous pattern, and the first reference value corresponds to a first value processed by the processing circuit in at least a part of the synchronous pattern, and the second reference value corresponds to at least a part of A second value processed by the processing circuit in the synchronous mode. 16. The synchronization judging device as claimed in claim 15, wherein the judging unit further comprises: a first counter, accumulating according to the first comparison signal; a second counter, accumulating according to the second comparison signal; a first judging device, generating a first judging information according to the accumulated value of the first counter and a critical value; a second judging device, generating a second judging information according to the accumulated value of the second counter and the critical value; and A determiner generates the synchronization state signal according to the first determination information and the second determination information. 17. The synchronization determination device as claimed in claim 14, wherein when the synchronization determination device detects that the processed signal is identical to one of the at least one reference value, it determines that the recovered clock is in a synchronization state. 18. A receiving method for determining the synchronization state of a clock of an input signal, comprising the following steps: receiving the input signal; generating a serial data and a recovered clock according to the input signal; decoding the serial data to generate a decoded signal; and determining the synchronization state of the recovered clock according to the decoded signal and at least one reference value; Wherein, the serial data includes a synchronous pattern, and the at least one reference value includes a first reference value, and the first reference value corresponds to a first value generated by decoding at least a part of the synchronous pattern. 19. The receiving method as claimed in claim 18, wherein the step of determining the synchronization state of the recovered clock further comprises: A first accumulated value is accumulated by comparing the decoded signal with the first reference value. 20. The receiving method as claimed in claim 19, wherein the step of determining the synchronization state of the recovered clock further comprises: comparing the decoded signal with the second reference value to accumulate a second accumulated value; Wherein, the at least one reference value further includes the second reference value, and the second reference value corresponds to a second value generated by decoding in at least a part of the synchronization pattern. 21. The receiving method as claimed in claim 20, wherein the step of determining the synchronization state of the recovered clock further comprises: generating a first judgment message according to the first accumulated value; generating a second determination information according to the second accumulated value; and The synchronization state of the recovered clock is determined according to the first determination information and the second determination information. 22. The receiving method as claimed in claim 20, wherein the step of determining the synchronization state of the recovered clock further comprises: The synchronization state of the recovered clock is determined according to the first accumulated value and the second accumulated value.

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