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CN101785099B - 电子零件 - Google Patents

电子零件 Download PDF

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Publication number
CN101785099B
CN101785099B CN200980100229XA CN200980100229A CN101785099B CN 101785099 B CN101785099 B CN 101785099B CN 200980100229X A CN200980100229X A CN 200980100229XA CN 200980100229 A CN200980100229 A CN 200980100229A CN 101785099 B CN101785099 B CN 101785099B
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China
Prior art keywords
load
pad
resin
conductive pattern
semiconductor element
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CN101785099A (zh
Inventor
大野和幸
田中祥雄
中岛清
鞍谷直人
前川智史
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MMI Semiconductor Co Ltd
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Omron Corp
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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Abstract

本发明涉及一种电子零件，在基板(52)(印刷基板)的上表面设有由镀Au等无机材料(61b)覆盖导电图案部(61b)的表面的装片用焊盘(55)。在装片用焊盘(55)的中央部涂敷有抗焊料剂(67)，在装片用焊盘(55)的外周部露出无机材料(61b)。半导体元件(53)通过装片树脂粘接固定在装片用焊盘之上。装片用焊盘(55)和其它邻接的导电图案之间通过槽(60)分离，覆盖导电图案的抗焊料剂(67)不与装片用焊盘55接触。

Description

电子零件
技术领域
本发明涉及电子零件。具体而言，涉及在基板上安装有传感芯片及电子电路等半导体元件的电子零件。
背景技术
作为在印刷基板上安装半导体元件并由罩覆盖的电子零件(麦克风封装)，例如有专利文献1公示的结构。在专利文献1公示的电子零件中，如图1～图3各方式所示，使用MEMS技术制作的麦克风11在下表面中央部设有空洞12，使用环氧树脂1 3将麦克风11的下表面装片在印刷基板14的上表面。这样将麦克风11装片在印刷基板14上时，当被麦克风11压靠的环氧树脂13流入空洞12中时，由于流入的树脂，空洞12内的容积产生偏差，或由于环氧树脂13流出而使麦克风11与印刷基板14之间的环氧树脂13的膜厚产生偏差，麦克风11的特性可能会受到不良影响。因此，在专利文献1中，通过在空洞12内在印刷基板14的上表面设置保持环15，防止装片用的环氧树脂13流入空洞12中，抑制对麦克风11的不良影响。
具体而言，在图1所示的方式中，将麦克风11的下表面内周部重合在保持环15之上，利用环氧树脂13来粘接麦克风11的下表面外周部和印刷基板14之间。因此，在利用环氧树脂13装片麦克风11时，阻止环氧树脂13通过保持环15向空洞12的内部流入。
但是，在该方式中，对于向麦克风11的外侧流出的环氧树脂13没有任何的考虑，因此，不能抑制向外侧流出的环氧树脂13。因此，在将环氧树脂13加热固化之前，环氧树脂13向外侧流出，流出的环氧树脂13有时会到达用于将金属罩16接地的接地图案17。金属罩16与印刷基板14一起构成法拉第罩而遮蔽外部的高频干扰，因此，通过导电性粘接树脂与接地图案17粘接，但是，在粘接金属罩16之前，流出的环氧树脂13在接地图案17的表面形成非导电性覆膜时，在该部位引起金属罩16与接地图案17的导通不良，具有使高频干扰的遮蔽性降低的问题。
为了避免这种不良情况，以往，在装片麦克风11的区域与接地图案17的区域之间保持足够的距离。但是，增大该距离时，其结果是电子零件的设置面积(footprint)变大，电子零件的尺寸变大，妨碍电子零件的小型化。
另外，在图2所示的方式中，利用环氧树脂13将麦克风11的整个下表面粘接在印刷基板14上，在空洞12内设置保持环15，由保持环15堵截流入的环氧树脂13。
另外，在图3所示的方式中，为了提高保持环15堵截环氧树脂13的效果，将图2的方式中的保持环15的厚度增大。
但是，在图2及图3的方式中，即使正确地管理环氧树脂13的涂敷量，或以使麦克风11的按压力一定的方式进行管理，由于直至使涂敷的环氧树脂13固化的时间及外部环境的温度等，而使从麦克风11的下表面流出的环氧树脂13的量改变，因此，麦克风11的下表面与印刷基板14之间的固化后的树脂厚度的偏差变大。其结果是空洞12的容积变动、或环氧树脂13的厚度产生偏差、其弹性变化，存在麦克风11的特性受到影响的问题。
为了抑制这种不良情况，目前在组装工序中严格管理外部环境，另外，严格实施将涂敷环氧树脂13后到进行树脂烘烤(增加温度使环氧树脂13固化的工序)的时间缩短等的工序上的管理。但是，要严格进行组装工序中的外部环境的管理，需要高价的环境设备，在成本方面不理想。另外，若将涂敷环氧树脂13后到进行树脂烘烤的时间缩短，则必须将电子零件麻利地投入烘烤炉内，因此，人工费增加，并且，难以进行烘烤炉的温度管理，在这一点上导致成本提高，不理想。
另外，在图2的方式中，由印刷基板14的导体图案形成保持环15，因此，麦克风11由环氧树脂13固定在印刷基板14的除导体图案之外的区域上。印刷基板14的导体图案与金属罩对齐而起到遮蔽来自外部的高频干扰的作用，因此，在图2的方式中，麦克风11正下方的高频干扰的遮蔽性变差。与此同时，印刷基板14的导体图案大大有助于电子零件整体的刚性，因此，通过在该区域除去导体图案，电子零件的刚性变差，由此，也有可能对电子零件的功能产生不良影响。
另一方面，在图3的方式中，为了设置厚度大的保持环15，必须追加与印刷基板14的导体图案不同的其它部件而形成保持环15，导致成本增加。
专利文献1：美国专利第7,166,910号说明书
发明内容
本发明是鉴于上述问题而作出的，其目的在于提供一种电子零件，能够防止用于在基板上固定半导体元件的装片树脂从装片区域流出，并且能够将稳定化半导体元件的特性。
本发明提供一种电子零件，在基板的上表面设有装片用焊盘，该装片用焊盘的表面的至少外周部由无机材料形成，并且使该外周部的无机材料露出，通过装片树脂将半导体元件粘接在所述焊盘之上，其特征在于，通过空隙将与所述装片用焊盘邻接的导电图案和所述装片用焊盘之间分离，覆盖所述导电图案的覆盖部件不与所述装片用焊盘接触。
在本发明的电子零件中，在基板的上表面设有装片用焊盘，该装片用焊盘的表面的至少外周部由无机材料形成，并且使该外周部的无机材料露出，通过装片树脂将半导体元件粘接在所述焊盘之上，因此，装片树脂在装片用焊盘端部相对于无机材料具有较大的接触角，由此，装片树脂不易向装片用焊盘的外部流出。另外，通过空隙将与装片用焊盘邻接的导电图案和装片用焊盘之间分离，覆盖所述导电图案的覆盖部件不与装片用焊盘接触，因此，即使与装片树脂的润湿性好的覆盖部件涂敷在邻接的导电图案上的情况，装片树脂也不与覆盖部件接触，装片树脂不易向装片用焊盘的外部流出。
因此，用于使导电性罩接合的接地电极不会被装片树脂覆盖，故而不会出现导电性罩向接地电极的接合不足的问题，高频干扰的遮蔽性不易下降。另外，由于装片树脂不易向外流出，故而可通过结合树脂的涂敷量来控制半导体元件与装片用焊盘之间的装片树脂的厚度，半导体元件与装片用焊盘之间的装片树脂的厚度不易产生偏差。另外，在半导体元件之下设有装片用焊盘，故而不会像以往那样地使基板乃至电子零件的强度降低。
本发明的电子零件的一方面，所述无机材料为Cu和Au中的至少任一种。无机材料中尤其是Cu及Au与装片树脂的润湿性不好，因此，作为无机材料通过使用Cu及Au，能够提高阻止装片树脂流出的效果。
本发明的电子零件的另一方面，所述基板为印刷基板，所述装片用焊盘的主要部分由与印刷基板的导电图案同样的材料形成。根据本方面，利用印刷基板的导电图案能够制作装片用焊盘，因此，能够抑制电子零件的成本。
本发明的电子零件的又一方面，所述装片用焊盘的主要部分由Cu形成，其表面的至少外周部由所述无机材料即Au形成。在该方面中，装片用焊盘的主要部分由Cu形成，故而可利用印刷基板的导电图案来制作装片用焊盘，能够抑制电子零件的成本。另外，由于由Au形成装片用焊盘的表面外周部，故而通过降低装片树脂的润湿性能够提高阻止装片树脂流出的效果。
本发明的电子零件的其它方面，在所述装片用焊盘的表面，在除其外周部之外的区域涂敷覆盖部件。装片树脂相对于覆盖部件的粘接强度比无机材料更高，因此，通过在装片用焊盘除外周部之外的区域涂敷覆盖部件，能够提高半导体元件的粘接强度。
另外，本发明用于解决上述课题的方式具有将以上说明的构成要素适当组合的特征，本发明通过将上述构成要素适当组合而能够进行多种变化。
附图说明
图1是表示专利文献1公开的电子零件的一方式的剖面图；
图2是表示专利文献1公开的电子零件的其它方式的剖面图；
图3是表示专利文献1公开的电子零件的又一方式的剖面图；
图4是表示本发明第一实施方式的电子零件的结构的剖面图；
图5是图4的X部放大图；
图6是表示电子零件的基板的俯视图；
图7是表示在装片用焊盘的边缘形成无机材料时、涂敷在装片用焊盘的装片树脂的状态的示意剖面图；
图8是表示由抗焊料剂覆盖装片用焊盘的整个面时、涂敷在装片用焊盘的装片树脂的状态的示意剖面图；
图9是表示将半导体元件粘接在装片用焊盘上的装片树脂的不同浸湿状况的示意图；
图10是表示涂敷在邻接的导电图案的抗焊料剂到达装片用焊盘的边缘的状态下、涂敷在装片用焊盘的装片树脂的状态的示意剖面图；
图11(a)～(c)是说明将半导体元件粘接在装片用焊盘上时、装片树脂向装片用焊盘上扩展的状态的说明图；
图12是表示第一实施方式的变形例的剖面图。
附图标记说明：
51：电子零件
52：基板
52a：基板芯材
53：半导体元件
53a：空洞
55：装片用焊盘
56：焊盘
57：接地电极
58、59：表面侧接地图案
60：槽
61a：导电图案部
61b：无机材料
65：通孔
66：通孔
67：抗焊料剂
68：装片树脂
69：接合线
具体实施方式
以下，参照附图说明本发明的优选实施方式。
(第一实施方式)
图4是表示本发明第一实施方式的电子零件的结构的剖面图，图5是图4的X部放大图。另外，图6是基板的俯视图。在此所示的电子零件51，在基板52的上表面安装半导体元件53，在由基板52和导电性罩54构成的封装(法拉第罩)内收纳有半导体元件53。
基板52由印刷基板构成，如图6所示，在基板52的上表面，通过对粘贴于基板芯材52a上表面的Cu等金属薄膜进行构图而成的导电图案，形成装片用焊盘55、引线接合用的焊盘56、接地电极57等。接地电极57在基板52的外周部以包围装片用焊盘55及焊盘56的方式形成，焊盘56配置于装片用焊盘55的附近。
另外，作为半导体元件53，假设如后述在下表面中央部设有空洞并使下表面成为方环状，因此，装片用焊盘55也与此对应而形成方环状。在比接地电极57更靠内侧的区域中没有装片用焊盘55及焊盘56的区域，通过导电图案形成有表面侧接地图案58、59。尤其是，在装片用焊盘55的内侧设置有四边形的表面侧接地图案58。
装片用焊盘55、焊盘56、接地电极57、表面侧接地图案58、59通过槽60(空隙)相互分离。在此，槽60是指将导电图案彼此分离并使基板芯材52a在底面露出的区域。槽60通过蚀刻金属薄膜而形成，其宽度为0.10mm左右。但是，表面侧接地图案59也可以与接地电极57连接，成为一体。
另外，装片用焊盘55上表面的除外周部及内周部之外的区域被用于保护导体图案表面的抗焊料剂67覆盖。表面侧接地图案58、59的整个上表面也被抗焊料剂67覆盖。该抗焊料剂67通过将熔化状态的抗焊料剂进行网版印刷而在基板52的表面涂敷均匀的厚度，然后通过加热使其固化。另外，在该实施方式中，作为覆盖部件使用抗焊料剂，但是，除此以外也可以使用丝网图案等。
另外，如图4所示，在导电图案中从抗焊料剂67露出的区域即接地电极57、焊盘56、装片用焊盘55的内周部及外周部，覆盖相对于装片树脂的润湿性差的无机材料61b(例如，镀Au等)。
因此，装片用焊盘55在由导电图案形成的导电图案部61a的表面外周部及内周部成膜镀Au等无机材料61b而形成。即，装片用焊盘55由导电图案部61a和无机材料61b构成，导电图案部61a(导电图案的一部分)成为装片用焊盘55的主要部分。而且，在装片用焊盘55表面的除外周部及内周部之外的区域涂敷有抗焊料剂67。另外，装片用焊盘55的内周及外周被槽60包围，与接近的导电图案即表面侧接地图案58、59、56构造上分离。涂敷在邻接的导电图案的抗焊料剂67即涂敷在表面侧接地图案58、59的抗焊料剂67不与装片用焊盘55接触，理想的是，使抗焊料剂67不向槽60内流入。
在基板52的下表面，通过对粘贴于基板芯材52a下表面的Cu等金属薄膜进行构图而成的导电图案，形成引出电极62和背面侧接地图案63。背面侧接地图案63将没有引出电极62的大致整个区域覆盖，引出电极62和背面侧接地图案63通过槽64而相互分离。引出电极62及背面侧接地图案63为用于将电子零件51焊锡安装在基板(例如手机用的母板)上的图案。
在基板芯材52a上，以贯通表面背面的方式设有通孔，焊盘56通过通孔65与引出电极62电连接，装片用焊盘55及表面侧接地图案58、接地电极57通过通孔66与背面侧接地图案63连接。
半导体元件53是各种传感检测用的传感器芯片(例如，音响传感器、加速度传感器、压力传感器等)、LSI、ASIC等元件，但在该实施方式中为检测音响振动的音响传感器(或者将音响振动转换成电能的转换器)。该半导体元件53即音响传感器，在中央部形成感知音响振动的薄膜(隔膜)，在薄膜的下表面侧形成空洞53a，通过静电方式等检测音响振动引起的薄膜的位移。
半导体元件53的下表面包围空洞53a而形成方环状，通过装片树脂68粘接固定在装片用焊盘55之上。作为装片树脂68，使用具有柔软性的硅酮等粘接树脂，将涂敷于转印针(压模)的装片树脂68转印在装片用焊盘55上之后，在其之上装载半导体元件53并以均等的力进行按压，将装片树脂68加热固化而固定半导体元件53。装片树脂68除了固定半导体元件53之外，也起到遮断来自外部环境的余力的作用。半导体元件53的端子和焊盘56通过接合线69连接，因此，半导体元件53的端子与下表面的引出电极62导通。另外，表面侧接地图案58位于空洞53a的下表面开口部分。
另外，在基板52的上表面，可以安装多个半导体元件，也可以安装其它电子零件。另外，金属薄膜的图案可根据所安装的半导体元件及电子零件等的形式而适当自由地设计。
导电性罩54利用电阻率小的金属材料形成为罩状，在下表面形成有用于收纳半导体元件53等的空间。在导电性罩54下端部的整个一周形成有大致水平延伸的凸缘70。
导电性罩54以覆盖半导体元件53等的方式载置于基板52之上，凸缘70的下表面通过导电性接合部件71而与接地电极57接合固定，并且，通过导电性接合部件71的导电性而与接地电极57电连接。因此，导电性罩54成为与下表面的背面侧接地图案63同电位(接地电位)。作为导电性接合部件71，使用导电性环氧树脂(例如，含有银填充剂的环氧树脂)及焊锡等材料。
另外，在所安装的半导体元件53是音响传感器的情况下，也可以在导电性罩54的顶部等开设用于使音响振动通过的孔(未图示)。另外，由导电性罩54和基板52构成的封装也可以根据收纳的半导体元件53的种类而构成密闭结构。例如，在只要遮蔽来自外部的灰尘、光等即可的情况下，只要用封装覆盖半导体元件53等即可，未必要求气密性，但是，在需要耐湿性、耐药品性的情况下，优选封装具有气密性。
但是，根据该电子零件51，由接地的导电性罩54和具有接地的背面侧接地图案63及表面侧接地图案58、59的基板构成法拉第罩，因此，能够将半导体元件53自外部的高频干扰阻断，能够降低半导体元件53受到的外部干扰的影响。
另外，基板52的表面背面的任一面全部由导电图案覆盖，故而能够防止温度变化等造成的基板52的翘曲。
另外，在装片用焊盘55中，在除外周部及内周部之外的区域涂敷有抗焊料剂67。硅酮等装片树脂68相对于抗焊料剂67的粘接强度比其相对于Cu的导电图案部61a及镀Au的无机材料61b的粘接强度更高，因此，通过在装片用焊盘55的一部分涂敷抗焊料剂67，能够提高装片树脂68对半导体元件53的粘接强度。
另外，装片用焊盘55的外周部及内周部通过镀Au等无机材料61b形成，故而能够防止装片树脂68向装片用焊盘55的内侧及外侧流出。通过图7～图11说明其理由。
作为装片树脂68，为了缓和来自外部的冲击等特性变动原因而使用柔软的树脂，尤其是可使用硅酮等，其容易流动。该硅酮等树脂相对于相同的有机材料即抗焊料剂的润湿性良好，接触角减小。而且，抗焊料剂的端面不易形成直角而容易形成倒角。因此，如图8所示，在由抗焊料剂67覆盖装片用焊盘55整个面时，涂敷装片树脂68时的接触角θ变小，其结果是，涂敷的装片树脂68容易从装片用焊盘55向外侧或内侧流出，一旦装片树脂68流出，其流出量随时间的增加而增加。
对此，硅酮等树脂相对于Au及Cu等无机材料的润湿性差，接触角变大。与抗焊料剂相比，端面容易形成直角。因此，如图7所示的本实施方式，在装片用焊盘55的边缘成为无机材料61b的情况下，涂敷装片树脂68时的接触角θ变大，在装片用焊盘55的边缘，装片树脂68形成球面状，因此，涂敷的装片树脂68不易从装片用焊盘55向外侧或内侧流出。
但是，即使在装片树脂68的润湿性差、装片用焊盘55边缘的接触角θ大的情况下，也有时装片树脂68不成为图7所示那样的球面状(凸曲面)，如图9所示，装片树脂68在装片通过焊盘55的边缘成为凹曲面。在装片树脂68相对于半导体元件53的润湿性比相对于无机材料61b的润湿性更好的情况下，更容易产生图9这样的润湿情况。
另外，如图10所示，涂敷于邻接的导电图案(表面侧接地图案58、59)的抗焊料剂67到达装片用焊盘55的端面时，装片树脂68在装片用焊盘55的端部与抗焊料剂67接触时，装片树脂68容易从装片用焊盘55流出。
对此，如图7所示的本实施方式，在邻接的导电图案与装片用焊盘55之间形成槽60，若涂敷于邻接的导电图案的抗焊料剂67不与装片用焊盘55接触，由于上述理由，则装片树脂68不易从装片用焊盘55向外侧或内侧流出。
这样，阻止装片树脂68从装片用焊盘55流出时，能够防止流出的装片树脂68覆盖接地电极57的一部分而妨碍导电性罩54向接地电极57接合、使高频干扰的遮蔽性降低的现象。
另外，装片树脂68从装片用焊盘55流出时，伴随流出量的增加，半导体元件53与装片用焊盘55之间的装片树脂68的厚度变薄，但是，根据本实施方式，能够防止装片树脂68的流出，因此，通过管理装片树脂68的涂敷量能够减小装片树脂68的厚度偏差。其结果是，能够使半导体元件53的接合强度均匀化，空洞53a的容积均匀，另外，装片树脂68的弹性变得均匀，电子零件51的品质稳定。
另外，根据本实施方式，能够防止装片树脂68的流出，故而能够增大半导体元件53下表面的装片树脂68的厚度。图11(a)～(c)为说明其理由的图。图11(a)表示将在下表面转印有装片树脂68的半导体元件53向装片用焊盘55压靠的形态。此时，通过施加于半导体元件53的按压力和半导体元件53的自重而按压装片树脂68，如图11(b)所示，装片树脂68从半导体元件53与装片用焊盘55间的间隙被向外挤压，半导体元件53下表面的厚度逐渐变薄。
但是，在本实施方式的电子零件51中，流出的装片树脂68如图11(c)所示到达装片用焊盘55的端部时，装片树脂68在装片用焊盘55(无机材料61b)的一端被阻止，因此，阻止装片树脂68从半导体元件53的下表面流出。其结果，被抑制自半导体元件53下表面流出而无处可去的装片树脂68滞留在半导体元件53的下表面，故而与由抗焊料剂67覆盖到装片用焊盘55的端部的情况相比，半导体元件53下表面的装片树脂68的厚度增大。
由无机材料61b形成装片用焊盘55的端部时，除了能够减小装片树脂68的厚度偏差的效果之外，还有能够增大半导体元件53下方的装片树脂68的厚度的效果。其结果是，由装片树脂68遮断余力的效果进一步增强。
另外，在装片用焊盘55的下表面残余有导电图案(导电图案部61a、表面侧接地图案58)，因此，也不会如现有例那样地使基板52的强度降低，或导致电子零件51的成本增加。
(第一实施方式的变形例)
图12是表示本发明第一实施方式的电子零件的变形例的剖面图，表示与图5对应的部位的截面。在该变形例中，在装片用焊盘55之上不设置抗焊料剂67。即，由镀Au等无机材料61b覆盖导电图案部61a的整个上表面，在其之上通过装片树脂68接合固定半导体元件53的下表面。在这样的结构中，在进行装片时，装片树脂68也不会向装片用焊盘55的内周侧及外周侧流出。另外，由于装片树脂68不会流出，故而能够减小半导体元件53的下表面与装片用焊盘55之间的装片树脂68的厚度偏差，能够使电子零件的特性稳定。
另外，作为其它变形例，可以在从抗焊料剂67露出的装片用焊盘55的外周部及内周部不设置镀Au的无机材料61b，而使Cu的导电图案部61a保持露出的状态。这是由于，将Cu与抗焊料剂67相比较，其与装片树脂68的润湿性也更差，能够增大装片树脂68的接触角。
另外，作为又一变形例，在安装下表面中央部没有空洞部的半导体元件53的情况下，装片用焊盘55只要也与其对应而形成矩形即可。另外，导电图案部61a为Cu之外的材料的情况下，也可以在其外周部及内周部镀Au及镀Cu。

Claims (3)

1.一种电子零件，在基板的上表面设有装片用焊盘，该装片用焊盘的表面的至少外周部由无机材料形成，并且使该外周部的无机材料露出，通过装片树脂将半导体元件粘接在所述焊盘之上，其特征在于，
通过空隙将与所述装片用焊盘邻接的导电图案和所述装片用焊盘之间分离，覆盖所述导电图案的覆盖部件不与所述装片用焊盘接触，
所述基板为印刷基板，所述装片用焊盘的导电图案部由与印刷基板的导电图案相同的材料形成。
2.一种电子零件，在基板的上表面设有装片用焊盘，该装片用焊盘的表面的至少外周部由无机材料形成，并且使该外周部的无机材料露出，通过装片树脂将半导体元件粘接在所述焊盘之上，其特征在于，
通过空隙将与所述装片用焊盘邻接的导电图案和所述装片用焊盘之间分离，覆盖所述导电图案的覆盖部件不与所述装片用焊盘接触，
所述装片用焊盘的导电图案部由Cu形成，其表面的至少外周部由所述无机材料即Au形成。
3.一种电子零件，在基板的上表面设有装片用焊盘，该装片用焊盘的表面的至少外周部由无机材料形成，并且使该外周部的无机材料露出，通过装片树脂将半导体元件粘接在所述焊盘之上，其特征在于，
通过空隙将与所述装片用焊盘邻接的导电图案和所述装片用焊盘之间分离，覆盖所述导电图案的覆盖部件不与所述装片用焊盘接触，
在所述装片用焊盘的表面，在除所述外周部之外的区域涂敷有覆盖部件。
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US9162303B2 (en) * 2011-07-21 2015-10-20 Blackberry Limited Grooved circuit board accommodating mixed-size components
JP5917613B2 (ja) * 2014-07-01 2016-05-18 株式会社フジクラ 接着方法、及び構造物の製造方法
US10916520B2 (en) * 2015-06-10 2021-02-09 Mitsubishi Electric Corporation Semiconductor device, and method of manufacturing the same
US9793231B2 (en) * 2015-06-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under bump metallurgy (UBM) and methods of forming same
US9870967B2 (en) * 2016-03-10 2018-01-16 Analog Devices, Inc. Plurality of seals for integrated device package
JP7508322B2 (ja) * 2020-09-29 2024-07-01 株式会社日立製作所 電力変換ユニットおよび電力変換装置、電力変換ユニットの検査方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604363A (en) * 1994-09-06 1997-02-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor pressure sensor with package
CN1122304C (zh) * 1997-02-10 2003-09-24 松下电器产业株式会社 树脂封装型半导体装置的制造方法
CN101186792A (zh) * 2006-11-24 2008-05-28 日东电工株式会社 半导体装置制造用耐热性胶粘带

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3694796B2 (ja) * 1994-12-12 2005-09-14 イビデン株式会社 プリント配線板及びその製造方法
JP3432982B2 (ja) * 1995-12-13 2003-08-04 沖電気工業株式会社 表面実装型半導体装置の製造方法
JPH09262915A (ja) 1996-03-29 1997-10-07 Mitsubishi Heavy Ind Ltd シングルフェーサ用段ロール及びその製造方法
JP3417247B2 (ja) * 1996-05-28 2003-06-16 株式会社デンソー 樹脂封止型電子装置の製造方法
JP3443406B2 (ja) * 1997-02-10 2003-09-02 松下電器産業株式会社 樹脂封止型半導体装置
US5907189A (en) * 1997-05-29 1999-05-25 Lsi Logic Corporation Conformal diamond coating for thermal improvement of electronic packages
US7166910B2 (en) 2000-11-28 2007-01-23 Knowles Electronics Llc Miniature silicon condenser microphone
DE102005008512B4 (de) * 2005-02-24 2016-06-23 Epcos Ag Elektrisches Modul mit einem MEMS-Mikrofon
JP5001542B2 (ja) * 2005-03-17 2012-08-15 日立電線株式会社 電子装置用基板およびその製造方法、ならびに電子装置の製造方法
JP2008109649A (ja) * 2006-09-27 2008-05-08 Yamaha Corp マイクロフォンパッケージ
JP2008147266A (ja) * 2006-12-07 2008-06-26 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604363A (en) * 1994-09-06 1997-02-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor pressure sensor with package
CN1122304C (zh) * 1997-02-10 2003-09-24 松下电器产业株式会社 树脂封装型半导体装置的制造方法
CN101186792A (zh) * 2006-11-24 2008-05-28 日东电工株式会社 半导体装置制造用耐热性胶粘带

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