CN101740498B - Semiconductor device with contact etching stop layer and forming method thereof - Google Patents
Semiconductor device with contact etching stop layer and forming method thereof Download PDFInfo
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- CN101740498B CN101740498B CN 200810227173 CN200810227173A CN101740498B CN 101740498 B CN101740498 B CN 101740498B CN 200810227173 CN200810227173 CN 200810227173 CN 200810227173 A CN200810227173 A CN 200810227173A CN 101740498 B CN101740498 B CN 101740498B
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Abstract
The invention discloses a method for forming a semiconductor device with a contact etching stop layer, which comprises the following steps of: providing a substrate on which at least one grid structure is formed; putting the substrate in a settling chamber to carry out the settlement of the contact etching stop layer; oxidizing the contact etching stop layer in situ to form an oxide film on the surface of the contact etching stop layer; taking out the substrate on which the oxide film is formed; and forming an interlayer dielectric layer on the oxide film by high-density plasma chemical vapour deposition equipment. The invention also discloses the semiconductor device with the contact etching stop layer. The semiconductor device with the contact etching stop layer and the forming method thereof of the invention can effectively prevent damages which are caused by using the high-density and large-power plasma in the step of settling the interlayer dielectric layer to a gate oxide layer and voids phenomena of device performance drift, device reliability reduction and the like.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of semiconductor device and forming method thereof with contact etching stop layer.
Background technology
The making of semiconductor integrated circuit is extremely complicated process, and purpose is various electronic building bricks and circuit that particular electrical circuit is required, dwindles on the wafer that is produced on small size.Wherein, each assembly must electrically connect by suitable internal connecting line, the competence exertion desired function.
Because the making of integrated circuit is to very lagre scale integrated circuit (VLSIC) (ULSI, Ultra Large ScaleIntegration) development, its inner current densities is increasing, along with contained number of elements in the chip constantly increases, has in fact just reduced the free space of surperficial line.This way to solve the problem is to adopt the design of multiple layer metal lead.Wherein, the contact hole of the metal carbonyl conducting layer of bottom by forming in interlayer dielectric layer is connected with the conductive region of the metal-oxide semiconductor (MOS) that is positioned at its lower floor (MOS, Metal-Oxide Semiconductor) device.
Fig. 1 to Fig. 4 is the device profile schematic diagram of the existing contact hole formation method of explanation.Fig. 1 is the device profile schematic diagram behind the formation MOS device in the prior art, as shown in Figure 1, on substrate 101, form the MOS device, be included in substrate 101 interior form, the fleet plough groove isolation structures between each device (STI, Shallow Trench Isolation) 102; Be positioned at the gate oxide 103 (Gate Oxide) on the substrate 101, be positioned at the polysilicon gate 104 on the gate oxide 103; Be positioned at the gate lateral wall layer 105 on each gate lateral wall; And the source/ drain doping region 107 and 108 that in substrate 101, forms, be positioned at the grid both sides.
Fig. 2 is the device profile schematic diagram behind the formation etching stop layer in the prior art.As shown in Figure 2; cover one deck contact etching stop layer (CESL at the substrate surface that forms the MOS device; ContactEtch Stop Layer) 110; this contact etching stop layer 110 is compared with the interlayer dielectric layer that forms later; has much lower etch rate; prevent over etching when the etching interlayer dielectric layer is with formation contact hole opening in the back, the conductive region surface that protection is positioned under it does not sustain damage.
Fig. 3 is the device profile schematic diagram behind the deposition interlayer dielectric layer in the prior art.As shown in Figure 3, cover one deck interlayer dielectric layer 120 again on contact etching stop layer 110 surfaces.Can be uneven on this interlayer dielectric layer 120 back substrate surface of deposition, need also that generally it is carried out cmp and handle, make it planarization (being the result after the planarization among this figure).
After the critical size of device has been contracted to 90nm, need fill a large amount of small-sized gaps when depositing this interlayer dielectric layer 120, for reaching filling effect preferably, this interlayer dielectric layer 120 often needs to adopt high density plasma chemical vapor deposition (HDP-CVD, High density plasmachemical vapor deposition) method to form.This method is what to deposit with etching simultaneously, and it needs higher plasma density and more powerful radio-frequency power supply, and used radio-frequency power can be greater than 4000W usually.
Plasma density height, power used when utilizing the HDP method to form interlayer dielectric layer 120 are big, often in the actual production find that it has caused damage to grid structure.As shown in Figure 3, when HDP technology formed interlayer dielectric layer 120, defective 150 had been brought out in the damage that high density, powerful plasma bring (PID, Plasma Induced Damage) in gate oxide 102.This defective 150 can cause the device reliability variation, and makes grid leakage current obviously increase.
Fig. 4 is the device profile schematic diagram behind the formation contact hole opening in the prior art.As shown in Figure 4, utilize photoetching and lithographic technique to form contact hole opening 130 in the corresponding position of silicon chip.Then, in this contact hole opening 130, fill metal again, formed the contact hole that connects metal carbonyl conducting layer and MOS device conductive region.
The Chinese patent that September 1, disclosed publication number was CN1525539 in 2004 discloses a kind of barrier layer that prevents by the method for overetch.The protective effect that should rise can not be played in the barrier layer when this method formed contact hole in order to solve etching; be prone to the problem that over etching makes that contact hole is etched; (being etching stop layer) conformally deposited one deck protective dielectric layer with the inter-level dielectric interlayer and on the barrier layer; to slow down the problem of barrier layer thickness attenuation in subsequent boron phosphorosilicate glass steam step, improved the formation quality of contact hole.But this method can not effectively solve above-mentioned when the deposition interlayer dielectric layer on the one hand, because of high density, high power plasma cause damage to gate oxide, and the problem of drift takes place in the device performance that causes, it need increase by a process steps on the other hand, can extend manufacture cycle, strengthen production cost.
Summary of the invention
The invention provides a kind of semiconductor device and forming method thereof, to improve the phenomenon of easy damaged gate oxide in the existing semiconductor device forming process with contact etching stop layer.
For achieving the above object, a kind of formation method with semiconductor device of contact etching stop layer provided by the invention comprises step:
The substrate that forms at least one grid structure is provided;
Described substrate is put into the deposition that the settling chamber carries out contact etching stop layer;
Original position is carried out oxidation processes to described contact etching stop layer, forms oxide film on described contact etching stop layer surface;
Taking-up has formed the described substrate behind the oxide film;
Utilize high density plasma CVD equipment on described oxide film, to form interlayer dielectric layer.
The present invention has a kind of semiconductor device with contact etching stop layer of identical or relevant art feature, described semiconductor device comprises substrate, at least one grid structure that forms on the described substrate, the source/drain region that is positioned at described grid structure both sides, be covered in the contact etching stop layer on the described grid structure, be covered in the interlayer dielectric layer on the described contact etching stop layer, and pass the metallic conducting wire structure that described interlayer dielectric layer is connected with described grid structure, source/drain region, wherein, described contact etching stop layer surface also has oxide film.
Compared with prior art, the present invention has the following advantages:
Semiconductor device with contact etching stop layer of the present invention and forming method thereof, after forming contact etching stop layer, original position utilizes oxygen-containing gas that it is handled, formed oxide film thereon, this oxide film has certain extinction coefficient, can be at the follow-up photon that absorbs when carrying out the high density plasma deposition interlayer dielectric layer.Prevented that effectively this deposition interlayer dielectric layer step middle-high density, high power plasma from causing damage to gate oxide, avoided the appearance of phenomenons such as device performance drift and device reliability variation.
Description of drawings
Fig. 1 to Fig. 4 is the device profile schematic diagram of the existing contact hole formation method of explanation;
Fig. 5 is the electric performance test result who utilizes the semiconductor device of conventional method formation;
Fig. 6 utilizes traditional HDP method to form the electric performance test distribution of results figure of the semiconductor device of interlayer dielectric layer;
Fig. 7 is for utilizing no plasma method and the HDP method electric performance test distribution of results figure in conjunction with the semiconductor device that forms interlayer dielectric layer;
Fig. 8 is the flow chart of the formation method of the semiconductor device that has contact etching stop layer in the specific embodiment of the invention;
Fig. 9 to Figure 12 is the device profile schematic diagram that the formation method of the semiconductor device that has contact etching stop layer in the specific embodiment of the invention is described;
Figure 13 is according to the profile of method in the specific embodiment of the invention after the silicon nitride layer surface forms oxide film;
Figure 14 is the electric performance test result who utilizes the semiconductor device of tradition and the formation of specific embodiment of the invention method;
Figure 15 is the semiconductor device generalized section with contact etching stop layer of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Processing method of the present invention can be widely used in the every field; and can utilize many suitable material; be to be illustrated below by specific embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
When making semiconductor device, need utilize HDP technology growth interlayer dielectric layer, and used high density, the powerful plasma of this technology easily causes damage to gate oxide, causes the device performance variation.Be to confirm this point,, and utilize the grow electrical property of semiconductor device of interlayer dielectric layer of no plasma method to test respectively to utilizing the semiconductor device of HDP technology growth interlayer dielectric layer.
Fig. 5 is the electric performance test result who utilizes the semiconductor device of conventional method formation, as shown in Figure 5, its abscissa is the negative of the log value of grid leakage current (Ig), and ordinate is device detection result's a distribution probability (CDF, Cumulative Distribution Function).The condition of this test is 1.1 times operating voltage, i.e. 1.1 * 2.5=2.75V.And this test result should be to keep right better and better, distributes vertical more well more.
Figure intermediate cam figurate number strong point 501 forms for utilizing the HDP method in the conventional method
The device electrical performance result who records during interlayer dielectric layer, diamond data points 502 and Square Number strong point 503 are to utilize no plasma method to form earlier
Interlayer dielectric layer utilizes the HDP method to form again
The device electrical performance result who records during interlayer dielectric layer.Can see that the test result at diamond data points 502, Square Number strong point 503 is far better, promptly the semiconductor device that adopts no plasma mode and high-density plasma combination to form can be significantly improved aspect grid leakage current.This has also confirmed directly to utilize in the existing method HDP method to form interlayer dielectric layer can cause certain damage to component grid oxidizing layer really, and causes the device electrical performance variation.
Fig. 6 utilizes traditional HDP method to form the electric performance test distribution of results figure of the semiconductor device of interlayer dielectric layer, as shown in Figure 6, is to utilize traditional HDP method to form shown in the figure
A wafer of interlayer dielectric layer on the test result distribution map of electrical property (negative of the log value of grid leakage current) of each semiconductor device.Its test condition is 1.1 times operating voltage, i.e. 1.1 * 2.5=2.75V.The value of negative under 0.1% probability of each regional listed data log value that is grid leakage current wherein, this value is big more to show that device electrical performance is best.By seeing among the figure, adopt traditional HDP method to form on the wafer of interlayer dielectric layer, there is the electric leakage of the grid properties of flow of subregion not good, show that its gate oxide has been subjected to damage.
Fig. 7 as shown in Figure 7, is to utilize no plasma method to form earlier shown in the figure for utilizing no plasma method and the HDP method electric performance test distribution of results figure in conjunction with the semiconductor device that forms interlayer dielectric layer
Interlayer dielectric layer utilizes the HDP method to form again
The test result distribution map of the electrical property of each semiconductor device on the wafer of interlayer dielectric layer (negative of the log value of grid leakage current).Its test condition is 1.1 times operating voltage, i.e. 1.1 * 2.5=2.75V.The value of negative under 0.1% probability of each regional listed data log value that is grid leakage current wherein, it is big more best.By seeing among the figure, because it is to utilize no plasma mode to form near the part interlayer dielectric layer of grid, its gate oxide is not subjected to the injury of high density, high power plasma, and the grid electrical property of the semiconductor device on the wafer that forms with this kind mode has kept characteristic preferably.
By above test, confirmed to utilize the deposition of the interlayer dielectric layer that high density, high power plasma carry out to cause certain damage to gate oxide really, and then caused the device electrical performance variation.But, if do not adopt fill the space ability preferably the HDP mode form interlayer dielectric layer, or adopt and above-mentionedly will not have plasma method and form interlayer dielectric layer with the mode that the HDP method combines, will cause the interlayer dielectric layer between each grid to have a large amount of spaces, unfavorable equally to the performance and the reliability of the semiconductor device that forms.
For this reason, the invention provides a kind of new semiconductor device of contact etching stop layer and forming method thereof that has, comprise step:
The substrate that forms at least one grid structure is provided;
Described substrate is put into the deposition that the settling chamber carries out contact etching stop layer;
Original position is carried out oxidation processes to described contact etching stop layer, forms oxide film on described contact etching stop layer surface;
Taking-up has formed the described substrate behind the oxide film;
Utilize high density plasma CVD equipment on described oxide film, to form interlayer dielectric layer.
Wherein, described oxidation processes utilizes the plasma of oxygen-containing gas to realize that described oxygen-containing gas is N
2O, O
2, O
3, CO or CO
2In the gas any or combination in any, and the flow of described oxygen-containing gas is between 1000sccm to 8000sccm.
Wherein, described oxidation processes utilizes radio-frequency power supply to introduce energy, and the power of described radio-frequency power supply is between 100W to 500W.Also added gas carrier in the described oxidation processes, and described gas carrier is in helium or the argon gas any.And the flow of described gas carrier is between 1000sccm to 8000sccm.
Wherein, described contact etching stop layer is formed by silicon nitride material.
The present invention also correspondingly provides a kind of semiconductor device with contact etching stop layer, described semiconductor device comprises substrate, at least one grid structure that forms on the described substrate, the source/drain region that is positioned at described grid structure both sides, be covered in the contact etching stop layer on the described grid structure, be covered in the interlayer dielectric layer on the described contact etching stop layer, and pass the metallic conducting wire structure that described interlayer dielectric layer is connected with described grid structure, source/drain region, wherein, described contact etching stop layer surface also has oxide film.
Wherein, described contact etching stop layer is a silicon nitride layer, and the thickness of described contact etching stop layer exists
Extremely
Between.
Wherein, the thickness of described oxide film exists
Extremely
Between.
Wherein, described interlayer dielectric layer is the silicon dioxide layer of mixing phosphorus that utilizes the high density plasma deposition mode to form.
Can see that in method provided by the present invention and the device, after forming contact etching stop layer, original position utilizes oxygen-containing gas that this contact etching stop layer is carried out oxidation processes, forms oxide film.This oxide film has certain extinction coefficient, can absorb the photon of its generation when later use HDP method deposition interlayer dielectric layer.Prevented that effectively this deposition interlayer dielectric layer step middle-high density, high power plasma from causing damage to gate oxide, avoided the appearance of problems such as above-mentioned device performance drift and device reliability variation.
Fig. 8 is the flow chart of the formation method of the semiconductor device that has contact etching stop layer in the specific embodiment of the invention, Fig. 9 to Figure 12 is the device profile schematic diagram that the formation method of the semiconductor device that has contact etching stop layer in the specific embodiment of the invention is described, below in conjunction with Fig. 8 to Figure 12 specific embodiments of the invention is described in detail.
Step 801: substrate is provided.
This substrate can be for not forming the substrate of any structure, also can be for forming the substrate of metal oxide semiconductor transistor (MOS), and the substrate that is provided in the present embodiment is for having formed the substrate of at least one grid structure.
The generalized section of the substrate that provides in the specific embodiment of the invention is provided Fig. 9, as shown in Figure 9, substrate 901 in the present embodiment has formed at least one grid structure, comprise the gate oxide 903 (Gate Oxide) that is positioned on the substrate 901, be positioned at the polysilicon gate 904 on the gate oxide 903 and be positioned at gate lateral wall layer 905 on each gate lateral wall; In addition, in substrate 901, also formed the fleet plough groove isolation structure (STI, Shallow Trench Isolation) 902 between each device, and the source/ drain doping region 907 and 908 that in substrate 901, forms, be positioned at the grid both sides.
In the present embodiment also at the top of each grid and the region surface that need conduct electricity of source, drain region formed self aligned metal silicide layer (this is not shown), with further improve its with position metal carbonyl conducting layer (basis is not shown) thereon between contact electrical characteristics.
Step 802: described substrate is put into the deposition that the settling chamber carries out contact etching stop layer.
Used film deposition equipment is plasma enhanced chemical vapor deposition (PECVD in the present embodiment, Plasma Enhanced Chemical Vapor Deposition) equipment, the PECVD settling chamber that in this step substrate is put into correspondence carries out the deposition of contact etching stop layer.
Figure 10 is the device profile schematic diagram behind the formation etching stop layer in the specific embodiment of the invention.As shown in figure 10, covered one deck contact etching stop layer 910 at the substrate surface that forms grid structure.
Contact etching stop layer 910 in the present embodiment has been selected silicon nitride material for use; it is compared with the interlayer dielectric layer that forms later (often being silica material); has much lower etch rate; play the effect of etching stopping when the etching interlayer dielectric layer is with formation contact hole opening in the back; make etching stop in this contact etching stop layer 910 comparatively uniformity; prevent over etching, the conductive region surface below protecting is injury-free.
Select for use the common process condition to deposit this silicon nitride layer in the present embodiment,, under the temperature about 400 ℃, utilize plasma to form silicon nitride layer in wafer surface as selecting for use silane and ammonia as reacting gas.
Step 803: original position is carried out oxidation processes to described contact etching stop layer, forms oxide film on described contact etching stop layer surface.
Figure 11 is the device profile schematic diagram behind the formation oxide film in the specific embodiment of the invention.As shown in figure 11, by oxidation processes, on contact etching stop layer 910, formed one deck oxide film 950.
In the present embodiment, contact etching stop layer is silicon nitride material (SiN), through after the above-mentioned oxidation processes, changes silicon oxy-nitride material (SiON) at its surperficial oxide film that forms.The thickness of this silicon oxynitride film can
Extremely
About, as be
Or
Deng.
The extinction coefficient of silicon nitride material originally is 0, the photon that its article on plasma body produces does not have absorption, when the high density of utilizing the HDP mode, high power plasma deposition interlayer dielectric layer, the photon that is produced easily passes silicon nitride layer and arrives gate oxide, and the damage gate oxide, cause device electrical performance to drift about.
In the present embodiment, formed oxide film (SiON) again on this silicon nitride material, its extinction coefficient is 0.4, and photon is had absorption.Like this, in the high density of later use HDP mode, when high power plasma deposits interlayer dielectric layer, the photon that is produced can part be absorbed by this oxide film, has reduced its damage to gate oxide, has also effectively prevented the drift of device electrical performance.
Oxidation processes performing step in the present embodiment is as follows:
After having deposited silicon nitride layer, it is motionless in the settling chamber to keep wafer, feeds oxygen-containing gas in chamber, utilizes the plasma of this oxygen-containing gas to achieve a butt joint and touches the oxidation processes of etching stop layer, forms oxide film on described contact etching stop layer surface.Wherein, used oxygen-containing gas can be N
2O, O
2, O
3, CO or CO
2In the gas any or its combination has selected for use legibility from, N that toxicity is little in the present embodiment
2O gas.
Can be in this step with N
2The O flow set as is 1000,2000,5000,6000 or 8000sccm etc. between 1000 to 8000sccm.Also utilize radio-frequency power supply to introduce energy in this step oxidation processes, the power of this radio-frequency power supply can be arranged between the 100W to 500W, as is 100W, 300W, 400W or 500W etc.In addition, also can be arranged between 0.2 to 0.5 inch, to reach preferably oxidation effectiveness uniformly the slide holder of wafer and the distance between the plasma inlet are set.Used identical when being provided with temperature and chamber pressure with front cvd nitride silicon thin film.
In this step oxidation processes, can also feed gas carrier simultaneously, used gas carrier can be helium, argon gas etc., used gas carrier is a helium in the present embodiment, and its flow can be arranged between 1000 to 8000sccm, as is 1000,2000,5000,6000 or 8000sccm etc.
Figure 13 is according to the profile of method in the specific embodiment of the invention after the silicon nitride layer surface forms oxide film, as shown in figure 13, has formed oxide film 1301 on silicon nitride layer 1302, confirms that the present embodiment method therefor is feasible.
Step 804: taking-up has formed the described substrate behind the oxide film.
After the oxidation processes, stop to feed N
2O gas stops energy and introduces.Change into and feed a large amount of inert gases,, make the settling chamber identical with atmospheric pressure, open the settling chamber again, take out substrate with pressure as argon gas, nitrogen etc.
Step 805: utilize high density plasma CVD equipment on described oxide film, to form interlayer dielectric layer.
Figure 12 is the device profile schematic diagram behind the formation interlayer dielectric layer in the specific embodiment of the invention.As shown in figure 12, utilize the HDP method to cover one deck interlayer dielectric layer 920 again on contact etching stop layer 910 surfaces.Interlayer dielectric layer in the present embodiment is a silicon oxide layer, this interlayer dielectric layer 920 both can be on electricity isolating device and metal carbonyl conducting layer, can physically impurity sources such as device and removable particle be kept apart again.Can be uneven in these interlayer dielectric layer 920 back wafer surface of deposition, need also that generally this interlayer dielectric layer 920 is carried out cmp and handle, make it planarization (being the result after the planarization among this figure).
After forming interlayer dielectric layer 920, utilize photoetching and lithographic technique in this layer, to form the contact hole opening again.Then, in this contact hole opening, fill metal again, formed and between the conductive region (generally including grid structure top and source, drain region) of metal carbonyl conducting layer and MOS device, realized the contact hole structure that is electrically connected.
Though the interlayer dielectric layer in the present embodiment still directly utilizes the HDP method to form, what it was used still is high density, powerful plasma, but has the oxide film that absorbs the photon effect owing to formed on the contact etching stop layer surface in the present embodiment, the damage that the photon that has prevented from effectively to be produced causes gate oxide in the process of this HDP deposition interlayer dielectric layer.
Figure 14 is the electric performance test result who utilizes the semiconductor device of tradition and the formation of specific embodiment of the invention method, as shown in figure 14, its abscissa is the negative of the log value of grid leakage current (Ig), ordinate is device detection result's a distribution probability (CDF, Cumulative DistributionFunction).The condition of this test is 1.1 times operating voltage, i.e. 1.1 * 2.5=2.75V.And this test result should be keep right better and better, distribute vertical more good more.
In addition, the value of negative under 0.1% probability of log value of grid leakage current to the two compares, the semiconductor device that adopts conventional method to form is 11.7417, the semiconductor device that adopts present embodiment to form is 12.7384, after also further having confirmed employing present embodiment method from the concrete numerical value, device has had tangible improvement in the electrical property method.
The present invention also provides corresponding a kind of semiconductor device with contact etching stop layer.Figure 15 is the semiconductor device generalized section with contact etching stop layer of the present invention, as shown in figure 15, this semiconductor device comprises substrate 1501, at least one grid structure that on described substrate, forms, be positioned at the source/drain region of described grid structure both sides, be covered in the contact etching stop layer 1510 on the described grid structure, be covered in the interlayer dielectric layer 1520 on the described contact etching stop layer 1510, and pass described interlayer dielectric layer 1520 and described grid structure, the metallic conducting wire structure that source/drain region is connected, (not shown), wherein, also has oxide film 1550 on described contact etching stop layer 1510 surfaces.
Wherein, described contact etching stop layer 1510 can be silicon nitride layer, its thickness usually can
Extremely
Between, the thickness of the oxide films 1550 that this contact etching stop layer 1510 surfaces form can
Extremely
Between, as be
Or
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the formation method with semiconductor device of contact etching stop layer is characterized in that, comprises step:
The substrate that forms at least one grid structure is provided, and the grid structure both sides form active/drain region;
Described substrate is put into the deposition that the settling chamber carries out contact etching stop layer;
It is motionless in the settling chamber to keep substrate, and original position is carried out oxidation processes to described contact etching stop layer, forms oxide film on described contact etching stop layer surface;
Taking-up has formed the described substrate behind the oxide film;
Utilize high density plasma CVD equipment on described oxide film, to form interlayer dielectric layer.
2. formation method as claimed in claim 1 is characterized in that: described oxidation processes utilizes the plasma of oxygen-containing gas to realize.
3. formation method as claimed in claim 2 is characterized in that: described oxygen-containing gas is N
2O, O
2, O
3, CO or CO
2In the gas any or combination in any.
4. formation method as claimed in claim 2 is characterized in that: the flow of described oxygen-containing gas is between 1000sccm to 8000sccm.
5. formation method as claimed in claim 2 is characterized in that: described oxidation processes utilizes radio-frequency power supply to introduce energy, and the power of described radio-frequency power supply is between 100W to 500W.
6. formation method as claimed in claim 2 is characterized in that: also added gas carrier in the described oxidation processes, and described gas carrier is in helium or the argon gas any.
7. formation method as claimed in claim 6 is characterized in that: the flow of described gas carrier is between 1000sccm to 8000sccm.
8. formation method as claimed in claim 1 is characterized in that: described contact etching stop layer is formed by silicon nitride material.
9. as claim 1 or 8 described formation methods, it is characterized in that: the thickness of described contact etching stop layer exists
Extremely
Between.
10. formation method as claimed in claim 1 is characterized in that: the thickness of described oxide film exists
Extremely
Between.
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| US6720213B1 (en) * | 2003-01-15 | 2004-04-13 | International Business Machines Corporation | Low-K gate spacers by fluorine implantation |
| CN1525539A (en) * | 2003-02-28 | 2004-09-01 | 茂德科技股份有限公司 | Method and structure for preventing over etching of barrier layer and application thereof |
| CN101127304A (en) * | 2006-08-14 | 2008-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device making method |
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| US6720213B1 (en) * | 2003-01-15 | 2004-04-13 | International Business Machines Corporation | Low-K gate spacers by fluorine implantation |
| CN1525539A (en) * | 2003-02-28 | 2004-09-01 | 茂德科技股份有限公司 | Method and structure for preventing over etching of barrier layer and application thereof |
| CN101127304A (en) * | 2006-08-14 | 2008-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device making method |
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