KR20010058645A - Method for forming IPO of semiconductor device - Google Patents
Method for forming IPO of semiconductor device Download PDFInfo
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- KR20010058645A KR20010058645A KR1019990065998A KR19990065998A KR20010058645A KR 20010058645 A KR20010058645 A KR 20010058645A KR 1019990065998 A KR1019990065998 A KR 1019990065998A KR 19990065998 A KR19990065998 A KR 19990065998A KR 20010058645 A KR20010058645 A KR 20010058645A
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- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000010408 film Substances 0.000 claims abstract description 82
- 239000011229 interlayer Substances 0.000 claims abstract description 38
- 239000010409 thin film Substances 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000005380 borophosphosilicate glass Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체장치의 층간절연막 형성방법에 관한 것으로, 이 방법은 도전패턴이 형성된 반도체기판의 구조물에 얇은 질화물을 증착하여 식각정지막을 형성하고, 식각정지막 상부에 고밀도 플라즈마 방식으로 SiH4, O2및 Ar을 주입해서 산화물을 얇게 증착하여 버퍼박막을 형성한 후에, 버퍼박막 상부에 고밀도 플라즈마 방식으로 SiH4, O2및 He을 주입해서 도전패턴 사이에 매립되도록 산화물을 증착하여 층간절연막을 형성한다. 그러므로, 본 발명은 질화막과 고밀도 플라즈마 산화막 사이의 스트레스를 줄일 수 있으며 좁은 반도체소자의 간격의 갭필 특성을 양호하게 한다.The present invention relates to a method for forming an interlayer insulating film of a semiconductor device. The method includes forming a etch stop film by depositing thin nitride on a structure of a semiconductor substrate on which a conductive pattern is formed, and forming SiH 4 , O on the etch stop film by a high density plasma method. 2 and Ar are deposited to form a thin film of oxide to form a buffer thin film, and then SiH 4 , O 2 and He are injected into the buffer thin film by a high density plasma to deposit an oxide so as to be interposed between conductive patterns to form an interlayer insulating film. do. Therefore, the present invention can reduce the stress between the nitride film and the high density plasma oxide film and improve the gap fill characteristics of the gap of the narrow semiconductor device.
Description
본 발명은 반도체장치의 층간절연막 형성방법에 관한 것으로서, 특히 질화박막과 고밀도 플라즈마 산화막이 적층된 반도체장치의 층간절연막에서 증착 불량과 패턴사이에 채워지는 고밀도 플라즈마 산화막의 보이드(void)를 제거하여 반도체소자의 수율 및 전기적 특성을 향상시킬 수 있는 반도체장치의 층간절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device. In particular, in the interlayer insulating film of a semiconductor device in which a nitride film and a high density plasma oxide film are stacked, a void of a high density plasma oxide film filled between a deposition defect and a pattern is removed. A method of forming an interlayer insulating film of a semiconductor device capable of improving the yield and the electrical characteristics of the device.
반도체장치가 고집적화됨에 따라, 배선의 넓이(width) 뿐만 아니라 배선과 배선 사이의 간격(space)도 현저하게 감소하는 추세에 있다. 더욱이 여러층의 도전층을 사용하는 고집적 반도체 메모리 장치에서는 층간절연막에 의해 도전층과 도전층 사이의 높이가 더욱 높아져서, 도전층들 사이의 콘택홀 마진이 점차 감소하고 있는 추세이다. 이에, 콘택형성에 따른 식각깊이가 높아지는 경우 콘택의 하부구조물의 손상이 많아 누설전류가 크게 발생하는 문제점이 있었다.As semiconductor devices are highly integrated, not only the width of the wiring but also the space between the wiring and the wiring tend to decrease significantly. Furthermore, in the highly integrated semiconductor memory device using multiple conductive layers, the height between the conductive layer and the conductive layer is further increased by the interlayer insulating film, and the contact hole margin between the conductive layers is gradually decreasing. Thus, when the etching depth according to the contact formation is increased, there is a problem in that the leakage current is generated largely due to the damage of the lower structure of the contact.
한편, 반도체장치의 층간절연막으로서는 갭필 특성이 양호한 BPSG(Boro Phospho Silicate Glass)를 사용하는데, 이때 하부 구조물에 콘택홀 식각시 식각 정지역할을 하는 물질로서 질화박막을 추가하게 된다.Meanwhile, BPSG (Boro Phospho Silicate Glass) having good gap fill characteristics is used as an interlayer insulating film of a semiconductor device. In this case, a nitride film is added to the lower structure as a material to etch the contact hole during etching.
하지만, 이 BPSG는 증착 후에 고온의 플로우(flow) 공정이 필요한데, 게이트전극의 고속화 및 저저항성을 위해 금속 재료를 채택할 경우 후속 열공정에 의해 열적 한계를 드러낸다.However, this BPSG requires a high temperature flow process after deposition, which reveals thermal limitations by subsequent thermal processes when metal materials are employed for the high speed and low resistance of the gate electrode.
이를 위해서 층간절연막은 BPSG 대신에 저온 증착이 가능한 고밀도 플라즈마 (high density plasma) 방식의 산화막을 사용하기도 한다.For this purpose, the interlayer insulating film may use an oxide film of a high density plasma method capable of low temperature deposition instead of BPSG.
그러나, 고밀도 플라즈마 산화막의 경우에는 하부의 질화박막의 두께에 따라리프팅 현상이 일어난다. 즉, 질화박막의 두께가 얇지 않으면 고밀도 플라즈마 산화막과의 스트레스에 의해 리프팅이 발생하게 된다. 반대로, 질화박막의 두께가 얇게 증착되면 리프팅 현상은 방지할 수 있으나 게이트전극 사이에 고밀도 플라즈마 산화막이 매립될 때 보이드(void)를 유발하게 되어 이후 콘택 전극 제조 공정의 수율을 저하시키는 문제점이 있었다.However, in the case of the high density plasma oxide film, the lifting phenomenon occurs depending on the thickness of the lower nitride film. That is, when the thickness of the nitride film is not thin, lifting occurs due to stress with the high density plasma oxide film. On the contrary, when the thickness of the thin nitride film is thinly deposited, the lifting phenomenon can be prevented, but when the high density plasma oxide film is buried between the gate electrodes, voids are caused, thereby lowering the yield of the contact electrode manufacturing process.
본 발명의 목적은 식각 정지용 질화박막과 고밀도 플라즈마 산화막으로 이루어진 층간절연막 제조 공정시 질화박막 상부에 고밀도 플라즈마 방식으로 SiH4, O2및 Ar을 주입해서 산화물을 얇게 증착하여 버퍼박막을 형성하고 그 위에 고밀도 플라즈마 방식으로 SiH4, O2및 He을 주입해서 고밀도 플라즈마 산화막을 형성함으로써 질화막과 고밀도 플라즈마 산화막 사이의 스트레스로 인한 리프팅 현상을 막을 수 있으며 좁은 반도체소자의 간격의 갭필 특성을 양호하게 하는 반도체장치의 층간절연막 형성방법을 제공하는데 있다.An object of the present invention is to inject a thin film of SiH 4 , O 2 and Ar in a high-density plasma method in the interlayer insulating film manufacturing process consisting of an etch stop nitride film and a high-density plasma oxide film to form an oxide thin film to form a buffer thin film thereon By injecting SiH 4 , O 2 and He in a high density plasma method to form a high density plasma oxide film, it is possible to prevent the lifting phenomenon due to stress between the nitride film and the high density plasma oxide film and to improve the gap fill characteristics of the narrow semiconductor device spacing. The present invention provides a method for forming an interlayer insulating film.
도 1 내지 도 4는 본 발명에 따른 반도체장치의 층간절연막 형성방법의 일예를 나타낸 공정 순서도.1 to 4 are process flowcharts showing one example of a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 실리콘 기판 12: 필드 산화막10 silicon substrate 12 field oxide film
14: 게이트산화막 16: 도프트 폴리실리콘14: gate oxide film 16: doped polysilicon
18: 하드 마스크 20: 스페이서18: hard mask 20: spacer
22: 소스/드레인 영역 24: 식각정지막22: source / drain area 24: etch stop film
26: 버퍼박막 28: 층간 절연막26: buffer thin film 28: interlayer insulating film
30: 콘택전극30: contact electrode
상기 목적을 달성하기 위하여 본 발명은 질화박막과 고밀도 플라즈마 산화막이 적층된 반도체장치의 층간절연막 형성방법에 있어서, 도전패턴이 형성된 반도체기판의 구조물에 얇은 질화물을 증착하여 식각정지막을 형성하는 단계와, 식각정지막 상부에 고밀도 플라즈마 방식으로 SiH4, O2및 Ar을 주입해서 산화물을 얇게 증착하여 버퍼박막을 형성하는 단계와, 버퍼박막 상부에 고밀도 플라즈마 방식으로 SiH4, O2및 He을 주입해서 도전패턴 사이에 매립되도록 산화물을 증착하여 층간절연막을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method for forming an interlayer insulating film of a semiconductor device in which a thin nitride film and a high density plasma oxide film are stacked, the method comprising: forming an etch stop film by depositing thin nitride on a structure of a semiconductor substrate on which a conductive pattern is formed; Injecting SiH 4 , O 2 and Ar in a high density plasma method on the etch stop layer to form a thin film of oxide to form a buffer thin film, Injecting SiH 4 , O 2 and He by high density plasma method on the buffer thin film And depositing an oxide so as to be interposed between the conductive patterns to form an interlayer insulating film.
본 발명의 제조방법에 있어서, 상기 식각정지막의 두께는 100Å미만, 버퍼박막의 두께는 100Å미만이 되도록 한다. 그리고, 상기 층간절연막의 두께는 2000∼3000Å이 되도록 한다.In the manufacturing method of the present invention, the thickness of the etch stop film is less than 100 GPa, the thickness of the buffer thin film is less than 100 GPa. The thickness of the interlayer insulating film is 2000 to 3000 kPa.
또한, 본 발명의 제조방법에 있어서, 상기 층간절연막을 형성하기 전에 웨이퍼 온도를 550∼650℃로 히팅시키되, 히팅 조건은 Ar을 주가스로 사용하고 상기 온도를 유지시키기 위하여 RF 소스 전력을 4000W이상으로 하는 것이 바람직하다.In addition, in the manufacturing method of the present invention, the wafer temperature is heated to 550 ~ 650 ℃ before forming the interlayer insulating film, the heating conditions are using the Ar source as the main gas and RF source power to 4000W or more to maintain the temperature It is preferable to set it as.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따른 반도체장치의 층간절연막 형성방법의 일 예를 나타낸 공정 순서도로서, 이를 참조하면 본 발명의 일 실시예는 모스 트랜지스터가 형성된 기판의 층간절연막 제조공정에 관한 것이다.1 to 4 are process flowcharts showing an example of a method for forming an interlayer insulating film of a semiconductor device according to the present invention. Referring to this, an embodiment of the present invention relates to an interlayer insulating film manufacturing process of a substrate on which a MOS transistor is formed.
우선, 도 1에 도시된 바와 같이, 필드산화막(12)이 형성된 반도체기판(10)에 게이트산화막(14)과, 도전체막으로서 도프트 폴리실리콘(16) 및 절연 물질로 된 하드 마스크(18)를 순차 적층한 후에 게이트 마스크를 이용한 사진 및 식각 공정을진행하여 이들 막(18,16)을 패터닝하여 게이트전극을 형성하고 게이트산화막(14)을 식각한다.First, as shown in FIG. 1, a gate oxide film 14 is formed on a semiconductor substrate 10 on which a field oxide film 12 is formed, a doped polysilicon 16 as a conductor film, and a hard mask 18 made of an insulating material. After sequentially stacking the photoresist and etching process using a gate mask, these films 18 and 16 are patterned to form gate electrodes, and the gate oxide film 14 is etched.
그 다음, 게이트전극 측벽에 절연 물질로서 질화막로 이루어진 스페이서(20)를 형성하고, 도전형 불순물 이온 주입 공정을 실시하여 기판내에 소스/드레인 영역(22)을 형성한다.Next, a spacer 20 made of a nitride film as an insulating material is formed on the sidewall of the gate electrode, and a source / drain region 22 is formed in the substrate by conducting a conductive impurity ion implantation process.
그 다음, 본 발명에 따른 층간절연막 제조 공정을 진행하기에 앞서, 도 2에 도시된 바와 같이, 반도체기판의 구조물에 화학기상증착법으로 얇은 질화물을 증착하여 식각정지막(24)을 형성한다. 이때, 식각정지막(24)의 두께는 100Å미만이 되도록 한다.Next, prior to the process of manufacturing the interlayer insulating film according to the present invention, as shown in FIG. 2, a thin nitride is deposited on the structure of the semiconductor substrate by chemical vapor deposition to form an etch stop layer 24. At this time, the thickness of the etch stop layer 24 is less than 100Å.
그 다음, 도 3에 도시된 바와 같이, 식각정지막(24) 상부에 고밀도 플라즈마(high density plasma) 방식으로 SiH4, O2및 Ar을 주입해서 산화물을 얇게 증착하여 버퍼박막(26)을 형성한다. 이때, 고밀도 플라즈마 방식에 의한 버퍼박막(26)의 형성은 바이어스를 가하지 않은 상태에서 이루어진다. 그리고, 버퍼박막(26)의 두께는 이후 형성될 고밀도 플라즈마 방식의 층간절연막 증착시 갭필에 방해가 되지 않도록 가능한 얇게 증착하는데, 바람직하게는 100Å미만이 되도록 한다. 이와 같이, 본 발명에서는 고밀도 플라즈마 방식의 층간 절연막을 형성하기전에 동일 챔버에서 버퍼박막(26)을 형성하기 때문에 식각정지막과 고밀도 플라즈마 방식의 층간절연막사이에서의 스트레스를 줄일 수 있다.Next, as shown in FIG. 3, SiH 4 , O 2, and Ar are injected into the etch stop layer 24 in a high density plasma manner to deposit a thin oxide to form a buffer thin film 26. do. At this time, the formation of the buffer thin film 26 by the high density plasma method is performed in a state where no bias is applied. In addition, the thickness of the buffer thin film 26 is deposited as thin as possible so as not to interfere with the gap fill during the deposition of the interlayer insulating film of the high density plasma method to be formed thereafter, preferably to be less than 100 μs. As described above, in the present invention, since the buffer thin film 26 is formed in the same chamber before the interlayer insulating film of the high density plasma method is formed, the stress between the etch stop film and the interlayer insulating film of the high density plasma method can be reduced.
계속해서, 버퍼박막(26) 상부에 고밀도 플라즈마 방식으로 SiH4, O2및 He을주입해서 산화물을 증착하여 층간절연막(28)을 형성한다. 이때, 층간절연막(28)의 두께는 2000∼3000Å이 되도록 한다.Subsequently, SiH 4 , O 2 and He are injected into the buffer thin film 26 in a high density plasma manner to deposit an oxide to form an interlayer insulating film 28. At this time, the thickness of the interlayer insulating film 28 is set to 2000 to 3000 kPa.
통상적인 고밀도 플라즈마 공정에 의한 산화막 증착시 SiH4, O2, 및 Ar를 반응 가스로 사용하였지만, 본 발명에서는 고밀도 플라즈마 방식의 산화막 증착시 SiH4, O2및 He을 사용하여 막의 스트레스를 줄인다. 즉, 고밀도 플라즈마공정에 의해 산화막 증착시 반응 가스로서 Ar을 사용하였을때보다 He을 사용할 때 막의 스트레스가 낮아서 식각정지막(24)과의 리프팅을 방지할 수 있고 좁은 게이트전극 사이의 갭필이 유리하다.In the present invention, SiH 4 , O 2 , and Ar were used as reaction gases in the deposition of the oxide film by the conventional high density plasma process. However, in the present invention, SiH 4 , O 2, and He are used in the deposition of the oxide film of the high density plasma method to reduce the stress of the film. That is, the stress of the film is lower when He is used than when Ar is used as the reaction gas during the deposition of the oxide film by the high density plasma process, thereby preventing lifting with the etch stop layer 24, and the gap fill between the narrow gate electrodes is advantageous. .
그리고, 본 발명은 층간 절연막 형성을 위한 고밀도 플라즈마 공정시 반응 가스로서 He을 사용하기 때문에 증착 초기에 웨이퍼의 온도를 알맞게 유지하기 위하여 히팅시켜야만 한다. 이때, 히팅 조건은 층간절연막을 형성하기 전에 Ar을 주가스로 사용하고 웨이퍼 온도를 550∼650℃로 히팅시키되, 상기 온도를 유지시키기 위하여 RF 소스 전력을 4000W이상으로 하는 것이 바람직하다. Ar을 사용하는 이유는 He보다 이온 충격효과가 커서 단시간내에 설정 온도까지 히팅하는데 유리하기 때문이다.In addition, since the present invention uses He as a reaction gas in a high-density plasma process for forming an interlayer insulating film, it must be heated to maintain the temperature of the wafer at the initial stage of deposition. At this time, in the heating conditions, Ar is used as the main gas and the wafer temperature is heated to 550 to 650 ° C. before the interlayer insulating film is formed. In order to maintain the temperature, the RF source power is preferably 4000 W or more. The reason for using Ar is that the ion bombardment effect is greater than that of He, which is advantageous for heating to a set temperature in a short time.
그 다음, 도 4에 도시된 바와 같이 연마 공정으로 상기 층간 절연막(28)을 연마한 후에, 콘택 마스크를 이용한 사진 및 식각 공정으로 상기 적층된 층간절연막(28), 버퍼박막(26) 및 식각정지막(24)을 식각하여 소오스 또는 드레인 접합(20)이 콘택홀(도시하지 않음)을 형성한다. 그리고, 콘택홀에 도전물질로서 도프트 폴리실리콘을 매립하여 콘택전극(30)을 형성한다.Then, after polishing the interlayer insulating film 28 by a polishing process, as shown in Figure 4, the laminated interlayer insulating film 28, the buffer thin film 26 and the etch stop in a photo and etching process using a contact mask The film 24 is etched to form a source or drain junction 20 with contact holes (not shown). Then, the contact electrode 30 is formed by filling doped polysilicon as a conductive material in the contact hole.
상기한 바와 같이, 본 발명은 질화물의 식각 정지막 상부에 고밀도 플라즈마 방식으로 SiH4, O2및 Ar을 주입해서 산화물을 얇게 증착하여 버퍼박막을 형성하고 그 위에 고밀도 플라즈마 방식으로 SiH4, O2및 He을 주입해서 산화물을 증착해서 층간절연막을 형성함으로써 상기 버퍼박막에 의해 질화막과 고밀도 플라즈마 산화막 사이의 스트레스를 줄여 접착 불량으로 인한 리프팅 현상을 막을 수 있으며 좁은 반도체소자의 간격의 갭필 특성을 향상시킬 수 있다. 이에 따라, 본 발명은 층간 절연막의 콘택홀 식각 공정에서 식각 불균일을 막을 수 있어 콘택전극의 전기적 측성 저하를 방지하여 반도체소자의 수율을 높일 수 있다.As described above, the present invention injects SiH 4 , O 2, and Ar in a high density plasma method on the etch stop layer of nitride to form a thin film of oxide to form a buffer thin film on the SiH 4 , O 2 And He to deposit an oxide to form an interlayer insulating film, thereby reducing the stress between the nitride film and the high-density plasma oxide film by the buffer thin film to prevent the lifting phenomenon due to poor adhesion, and improve the gap fill characteristics of the narrow semiconductor device spacing. Can be. Accordingly, the present invention can prevent the etching unevenness in the contact hole etching process of the interlayer insulating film, thereby preventing the electrical side of the contact electrode from deteriorating and increasing the yield of the semiconductor device.
Claims (6)
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| KR1019990065998A KR20010058645A (en) | 1999-12-30 | 1999-12-30 | Method for forming IPO of semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004031744A1 (en) * | 2004-06-30 | 2006-07-27 | Advanced Micro Devices, Inc., Sunnyvale | A technique for making a dielectric interlayer over a structure with closely spaced leads |
| KR100607820B1 (en) * | 2004-12-29 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method of forming interlayer insulating film of semiconductor device |
| KR100647391B1 (en) * | 2004-04-20 | 2006-11-23 | 주식회사 하이닉스반도체 | Gap Fill Method in Semiconductor Device Manufacturing Process |
| KR100724574B1 (en) * | 2006-01-10 | 2007-06-04 | 삼성전자주식회사 | A semiconductor device having an etch stop layer and a method of manufacturing the same |
| KR100929458B1 (en) * | 2007-11-26 | 2009-12-02 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
-
1999
- 1999-12-30 KR KR1019990065998A patent/KR20010058645A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100647391B1 (en) * | 2004-04-20 | 2006-11-23 | 주식회사 하이닉스반도체 | Gap Fill Method in Semiconductor Device Manufacturing Process |
| DE102004031744A1 (en) * | 2004-06-30 | 2006-07-27 | Advanced Micro Devices, Inc., Sunnyvale | A technique for making a dielectric interlayer over a structure with closely spaced leads |
| KR100607820B1 (en) * | 2004-12-29 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method of forming interlayer insulating film of semiconductor device |
| KR100724574B1 (en) * | 2006-01-10 | 2007-06-04 | 삼성전자주식회사 | A semiconductor device having an etch stop layer and a method of manufacturing the same |
| KR100929458B1 (en) * | 2007-11-26 | 2009-12-02 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
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