CN101483633B - A Synchronization Method for Orthogonal Frequency Division Multiplexing - Google Patents

Abstract

The invention relates to an OFDM synchronization method, and belongs to the technical field of wireless data transmission. The method comprises: establishing a data connection between a PC and an FPGA, an FPGA synchronization adjustment module receiving an unsynchronized baseband OFDM symbol stream, and performing sampling point counting on the data; the PC sends an interception sampling control signal to the FPGA, so that the FPGA intercepts the sampling data of a specified range in the OFDM symbol stream that has been synchronously adjusted, and transmits the sampling point count value at the interception moment back to the PC; the PC performs synchronization detection on the returned data according to the current synchronization state, and sends a synchronization adjustment control signal to the FPGA to make it perform synchronization adjustment, and at the same time updates the synchronization state, updates the interception range in the interception sampling control signal, and completes a synchronization cycle; the synchronization cycle is continuously performed, and finally outputs a synchronized pilot and data-separated OFDM symbol stream. The method is adopted to transfer the complex calculation part of the OFDM synchronization method from the FPGA to the PC, so that the implementation of the OFDM synchronization method becomes relatively easy.

Description

A Synchronization Method for Orthogonal Frequency Division Multiplexing

technical field

The invention belongs to the technical field of wireless data transmission, in particular to an OFDM system synchronization method based on the combination of a general-purpose computer and a field programmable gate array,

Background technique

Orthogonal frequency division multiplexing (OFDM) technology is actually a kind of multi-carrier modulation, which has the characteristics of high spectrum utilization and anti-multipath interference. The main idea is to divide the channel into several orthogonal sub-channels, convert high-speed data signals into parallel low-speed sub-data streams, and modulate them for transmission on each sub-channel. The signal bandwidth on the sub-channel is smaller than the relevant bandwidth of the channel, so each sub-channel can be regarded as flat fading, so OFDM can effectively resist the frequency selective fading of the channel. And since the bandwidth of each sub-channel is only a small part of the original channel bandwidth, channel equalization becomes relatively easy.

The structure and working process of the communication system using OFDM technology are shown in Figure 1. The input data stream is coded, modulated, inverse fast Fourier transform (IFFT), and cyclic prefix (CP) is inserted to form data OFDM symbols, and then every fixed number The data OFDM symbol is inserted into a pilot OFDM symbol with known fixed content to form a continuous baseband OFDM symbol stream in time, and then converted to radio frequency (RF) through digital/analog conversion (D/A) and sent to the air. The sent signal reaches the receiving end through wireless channel transmission. The RF signal received by the receiving end is converted to the baseband and undergoes analog/digital conversion (A/D) to obtain a baseband unsynchronized OFDM symbol stream, and the synchronized OFDM symbol stream is recovered through OFDM synchronization, and then the pilot OFDM symbol is separated, The data OFDM symbols, in which the pilot OFDM symbols are sent for channel estimation, the data OFDM symbols are removed from the CP, and the fast Fourier transform (FFT) uses the results of channel estimation for demodulation and decoding, and finally generates an output data stream.

OFDM technology has its own shortcomings, which are mainly reflected in its sensitivity to the synchronization deviation between the receiving end and the sending end, so it is required to perform more accurate synchronization at the receiving end, that is, to control the sampling clock and carrier clock between the receiving end and the sending end. The deviation is within the accuracy range required by the OFDM communication system, and each OFDM symbol is correctly divided.

There are two main reasons for the synchronization deviation between the receiving end and the sending end. One is the sampling frequency deviation and phase deviation caused by the incomplete matching of the sampling clock crystal oscillators at the receiving end and the sending end, which will aggravate the OFDM inter-symbol The other is the carrier frequency deviation and carrier phase deviation caused by the incomplete matching of the carrier clock crystal oscillator between the receiving end and the transmitting end, which will destroy the orthogonality between each sub-channel and aggravate OFDM inter-subcarrier interference.

So far, there have been many OFDM synchronization methods, and they have been well applied in some actual OFDM communication systems. However, with the continuous growth of communication system capacity, the transmission rate of OFDM communication systems continues to increase, and the requirements for data processing speed are getting higher and higher. At the same time, the requirements for synchronization accuracy are becoming more and more stringent. In order to meet the high-speed data processing speed requirements of the communication system, the Field Programmable Logic Array (FPGA), which is easy to carry out parallel design and has the characteristics of high speed, is usually used in the hardware synchronization of the communication system. However, because FPGA is not suitable for complex calculations, the existing OFDM synchronization methods are either too complicated to implement in hardware in high-speed data processing, or too simple to meet the accuracy requirements. The OFDM synchronization method is more difficult.

Contents of the invention

The purpose of the present invention is to solve the problem that the synchronization method of the receiving end encountered when adopting OFDM technology in the communication system realized by FPGA is difficult to realize in FPGA, proposes a kind of orthogonal frequency division multiplexing synchronization method, in FPGA and PC The transmission interface of data sampling and synchronous control signal is established between them, and the synchronous detection method that requires more complex calculations is transferred to the PC, which makes the implementation of OFDM synchronous method relatively easy.

A kind of OFDM synchronous method that the present invention proposes, carries out OFDM synchronously based on PC and Field Programmable Logic Array, it is characterized in that, the method comprises the following steps:

1) In the Field Programmable Logic Array, the receiving end starts to receive the signal sent by the sending end, and converts the signal into a stable unsynchronized OFDM symbol stream, adjusts the symbol stream synchronously and The synchronously adjusted OFDM symbol stream is sampled and counted; the data transmission interface between the PC and the field programmable logic array is connected; the PC is set to intercept the interception sampling control signal of the field programmable logic array sampling data range, and the initialization synchronization state is unsynchronized state;

2) The PC sends the interception sampling control signal to the field programmable logic array;

3) During the sampling and counting process of the synchronously adjusted OFDM symbol stream, the field programmable logic array intercepts the current OFDM symbol stream according to the interception range of the interception sampling control signal received. A piece of sampling data is stored, and then the data and the current sampling count value are sent back to the PC;

4) The PC performs synchronous detection on the latest data sent back by the field programmable logic array or several times according to the current synchronization state, and sends a synchronization adjustment control signal to the field programmable logic array, and simultaneously updates the synchronization state and updates the interception sampling control The range of interception in the signal;

5) The field programmable logic array performs corresponding synchronous adjustments to the current OFDM symbol stream according to the synchronous adjustment control signal sent by the PC, so as to reduce the current OFDM signal flow between the receiving end and the transmitting end. Symbol stream synchronization deviation, and extract pilot and data OFDM symbols for the current OFDM symbol stream; turn back to step 2);

6) Repeat steps 2)-step 5) in a synchronous cycle, so that the synchronization deviation is controlled within the accuracy range set by the OFDM communication system, and finally the OFDM symbol flow between transceivers is accurate Synchronize.

The features of the present invention are:

Establish a data transmission interface between the PC and the FPGA to realize the transmission protocol of the OFDM baseband sampling data and synchronous control signals between the PC and the FPGA, so that the PC can intercept and receive a part of the OFDM baseband OFDM symbol stream in the FPGA for analysis and calculate The synchronization deviation between the receiving end and the sending end controls the FPGA to make corresponding adjustments. In this way, the complex synchronization calculation is transferred from the FPGA to the PC with powerful computing capabilities. The FPGA only retains the necessary sampling clock and carrier clock adjustment modules, which greatly simplifies the design and implementation of the OFDM communication system in the FPGA.

Experiments have proved that, adopting the OFDM synchronization method combining PC and FPGA proposed by the present invention, the synchronization adjustment speed can exceed the sampling clock and carrier clock deviation between the receiving end and the sending end. Precise synchronization of clock and carrier clock.

Description of drawings

FIG. 1 is a schematic diagram of an OFDM communication system in the prior art.

Fig. 2 is a schematic flowchart of an OFDM synchronization method combining a PC and an FPGA proposed by the present invention.

FIG. 3 is a schematic diagram of the transfer process of the synchronization state in the PC synchronization detection embodiment of the synchronization method proposed by the present invention.

FIG. 4 is a schematic diagram of implementing FPGA synchronization adjustment of the synchronization method proposed by the present invention.

Detailed ways

The OFDM synchronization method combining PC and FPGA proposed by the present invention will be described in detail below in conjunction with the accompanying drawings and a specific OFDM communication system embodiment.

The present invention proposes a method for OFDM synchronization, based on the combination of PC and FPGA to carry out OFDM synchronization, the method and, as shown in Figure 2, includes the following steps:

1) In the FPGA, the receiving end starts to receive the signal sent by the sending end, and converts the signal into a stable unsynchronized OFDM symbol stream, performs synchronous adjustment on the symbol stream, and performs synchronous adjustment on the synchronously adjusted OFDM symbol stream Sampling and counting; connect the data transmission interface between the PC and the FPGA, initialize and set the interception sampling control signal for the PC to intercept the FPGA sampling data range, and initialize the synchronization state to an unsynchronized state;

In an embodiment of the present invention, the system sampling clock frequency is Fs (can be selected according to the system capacity and the baseband signal processing method adopted by the system, Fs=40.96MHz in this embodiment), the sampling clock frequency of the receiving end is Fsr, and the sampling clock frequency of the transmitting end is Fsr. The clock frequency is Fst, (Fsr and Fst are as close as possible to Fs, according to the actual sampling clock accuracy and stability, the variation range of Fsr/Fst is between 1±df, df=0.000001 in the present embodiment), each OFDM symbol length For F (can be selected according to the number of subcarriers and the multipath fading situation in the wireless channel, F=256+16=272 in the present embodiment), every Sn data OFDM symbols insert a pilot OFDM symbol, called a pilot OFDM symbol Together with the subsequent Sn (can be selected according to the wireless channel change speed, Sn=256 in this embodiment) data OFDM symbols are one frame, the frame length SF=F*(Sn+1) (SF=69904 in this embodiment), The time length of one frame is St=SF/Fst (St=1.707ms in the present embodiment); The sample counting of the present embodiment is set as two-stage cycle counting, and the first stage is called counting in the frame, and the second stage is called the frame number Counting, the intra-frame counting cycle period is equal to SF, the intra-frame counting frequency is equal to Fsr, the intra-frame counting cycle is once, the frame number is counted once, and the frame number counting cycle period is Sc (according to the structure design of the loop counter and the clock constraints of the FPGA Select, in this embodiment Sc=1024), the sampling length of the frame number counting period is Lc=Sc*SF (Lc=71581696 in this embodiment), and the frame number counting time period is Lt=Lc/Fsr (in this embodiment Lt=1.747s);

In the present embodiment, establish the maximum frame number interval dc (can be selected according to the real-time performance of the PC computing power, the PC response data transmission and the data transmission capability between the PC and the FPGA, of controlling the FPGA to intercept the sampling twice in succession by the PC. In the present embodiment, dc=6), maximum time interval Tc=dc*St (in the present embodiment, Tc=10.24ms), and Tc＜Lt; FPGA can store the maximum length of sampling data to be Mn (according to FPGA available Storage resource size selection, Mn=4096 in this embodiment);

The interception sampling control signal includes the interception sampling start position k and the interception sampling length n, k is initialized as Ki (the value range of Ki is between 0 and SF-1, Ki=0 in this embodiment), and n is initialized as Ni ;

2) The PC sends the interception sampling control signal to the FPGA;

3) During the process of sampling and counting the synchronously adjusted OFDM symbol stream, the FPGA intercepts and stores a segment of sampling data in the current OFDM symbol stream according to the interception range of the received interception sampling control signal, and then stores the intercepted The sampling data and the current sampling count value are sent back to the PC;

The method for intercepting sampling data of the above-mentioned FPGA is to start when counting in the frame is equal to k, intercepting a section of data with a length of n in the synchronously adjusted OFDM symbol stream; Data transmission speed, so the intercepted sampling data needs to be stored first and then sent back to the PC;

The current sampling count value returned above is n=c*SF+k, where c is the frame number count value of the FPGA when the sampling is started, since the count value in the frame is equal to the k set by the PC when the sampling is intercepted, the FPGA only The frame number count value c needs to be sent back to the PC, and the PC can calculate the sampling count value n; the purpose of FPGA returning the current sampling count value is that the PC uses the sampling count values n1 and n2 of the sampling data intercepted twice in a row Determine the time interval dt between two interception samples: dt=(n2-n1)/Fsr when n1<n2, dt=(n2+Lc-n1)/Fsr when n1>n2.

4) The PC performs synchronous detection on the sampling data returned by the FPGA one or more times according to the current synchronization state, and sends a synchronous adjustment control signal to the FPGA, and updates the synchronization state at the same time, and updates the interception range in the interception sampling control signal.

Synchronous detection in above-mentioned step 4) comprises utilizing existing method to carry out pilot frequency tracking, sample tracking and carrier tracking; PC machine carries out synchronous detection and needs the data that FPGA sends back one or more times recently, and number of times t depends on OFDM communication system to synchronous Accuracy requirements, the computing power of the PC used and the content and algorithm of concrete synchronous detection (calculate the phase deviation requirement t of sampling clock or carrier clock in the present embodiment t＞=1, calculate the frequency deviation requirement t＞= of sampling clock or carrier clock 2).

The above pilot tracking method is:

The PC uses the known pilot signal and the received data to perform correlation calculations with the intercepted sampling data at various positions to find the correlation peak; set the correlation peak value/the pilot autocorrelation value after the known quantization to v, if v is low Based on the preset threshold Tv (which can be selected according to the ratio of the power of the useful signal in the received signal to the power of the interference signal and the automatic gain control (AGC) performance before the synchronous adjustment of the receiving end, the present embodiment takes Tv=0.4), then it is considered Does not contain a pilot; otherwise, it is considered to contain a pilot, and the pilot position is the intra-frame count value p corresponding to the correlation peak position.

The above sample tracking method is:

According to the pilot frequency extracted from the latest t interception sampling data and the sampling count value at the time of interception, the PC calculates the sampling clock deviation (including the frequency deviation and phase deviation ); use the existing method to generate a sampling clock adjustment control signal 2 according to the sampling clock deviation, and send 2 to the FPGA.

The above carrier tracking method is:

The PC calculates the carrier clock deviation (including frequency deviation and phase deviation ); Utilize the existing method to generate the carrier clock adjustment control signal 3 according to the carrier clock deviation, and send 3 to the FPGA.

Above-mentioned step 4) in the PC, according to the current synchronization state, the transfer process embodiment of the synchronous state of the data that the latest t times of the FPGA is sent back synchronously detects is shown in Figure 3, the meaning of each synchronous state in the figure and the PC in this state Synchronization detection operations performed include:

Unsynchronized state A: The PC only performs pilot tracking, and outputs the interception sampling control signal 4; in this state, the PC does not know the position of the pilot, and cannot determine whether the sampling data intercepted by the control FPGA contains a complete pilot. The sampling clock deviation and carrier clock deviation between the receiving end and the sending end are also unknown;

Frame synchronization state B: The PC performs pilot tracking and sampling tracking, and outputs the interception sampling control signal 4 and the sampling clock adjustment control signal 2; in this state, the PC knows the pilot position, and the sampling data intercepted by the control FPGA will contain Complete pilot, but the sampling clock deviation and carrier clock deviation between the receiving end and the sending end are still unknown;

Sampling synchronization state C: PC performs pilot tracking, sampling tracking and carrier tracking, and outputs intercept sampling control signal 4, sampling clock adjustment control signal 2 and carrier clock adjustment control signal 3; in this state, the PC knows the pilot frequency Position, and adjust the sampling timing by controlling the FPGA to lock the sampling phase deviation between the receiving end and the transmitting end within the set accuracy range, and control the sampling data intercepted by the FPGA to contain not only the complete pilot frequency, but also the pilot frequency The position will be within a set accuracy around a fixed integer sample position, but the magnitude of the carrier clock skew between the receiver and transmitter is still unknown;

Final synchronization state D: PC performs pilot tracking, sampling tracking and carrier tracking, and outputs intercept sampling control signal 4, sampling clock adjustment control signal 2, carrier clock adjustment control signal 3 and OFDM symbol extraction control signal 6; in this state, The PC knows the pilot position, and adjusts the sampling timing by controlling the FPGA to lock the sampling phase deviation between the receiving end and the sending end within the set accuracy range, and the sampling data intercepted by the control FPGA will not only contain the complete The pilot frequency, and the pilot frequency position will be within the set accuracy range near a fixed integer sampling position. In addition, by controlling the FPGA to adjust the carrier clock, the carrier clock deviation between the receiving end and the sending end will be locked at the set Within the accuracy range, OFDM synchronization is completed when entering this state, and the FPGA synchronization adjustment module outputs the synchronized OFDM symbol stream.

The transition conditions between the above states A-D include:

Transition condition a2: At least one of the last three consecutive times, it is found that the intercepted sampling data does not contain pilots;

Transition condition a3: the intercepted sampling data does not contain pilot frequency;

Transition condition b1: It is found that the intercepted sampling data contains pilot frequency for three consecutive times recently;

Transition condition b2: the intercepted sampling data contains pilot frequency, and at least one of the latest three consecutive sampling clock phase deviations is not less than Tps;

Transition condition b3: the intercepted sampling data contains pilot frequency, and the sampling clock phase deviation is not less than Tps;

Transition condition c1: The intercepted sampling data contains pilot frequency, and the phase deviation of the latest three consecutive sampling clocks is less than the threshold Tps;

Transition condition c2: The intercepted sampling data contains pilot frequency, the phase deviation of the sampling clock is less than Tps, and at least one carrier clock phase deviation is not less than the threshold Tpc in the last 3 consecutive times;

Transition condition c3: the intercepted sampling data contains pilot frequency, the phase deviation of the sampling clock is less than Tps, and the phase deviation of the carrier clock is not less than Tpc;

Transition condition d1: The intercepted sampling data contains pilot frequency, the phase deviation of the sampling clock is less than Tps, and the phase deviation of the carrier clock is less than Tpc for the last three consecutive times;

Transition condition d2: the intercepted sampling data contains pilot frequency, the phase deviation of the sampling clock is less than Tps, and the phase deviation of the carrier clock is less than Tpc.

The value range of the sampling clock phase deviation threshold Tps in each of the above-mentioned transition conditions is 0 to π (the specific value can be selected according to the stability of the sampling clock and step 2)-step 5) synchronous cycle performance, Tps=2π/ 100), the value range of the carrier clock phase deviation threshold Tpc is 0 to π (the specific value is selected according to the carrier clock stability and step 2)-step 5) synchronous cycle performance, in this embodiment Tpc=2π/100).

When the above-mentioned different transition conditions are met, the transition process between states A-D includes:

When transition condition a2 or a3 is met: transition to state A;

When the transition condition b1 or b2 or b3 is satisfied: transition to state B;

When the transition condition c1 or c2 or c3 is satisfied: transition to state C;

When the transition condition d1 or d2 is met: transition to state D.

The method for updating the interception range in the interception sampling control signal in the above-mentioned step 4) is:

The interception sampling range of the interception sampling data that returns from FPGA at present is k, n, does not contain pilot frequency as interception sampling data, updates k=(k+Ls)%FS, n=Ni, obtains new interception sampling control signal; Otherwise Update k=(p-G)%SF according to pilot frequency position p, if synchronous state is A, update n=Ni, otherwise update n=N, obtain new intercept sampling control signal; Wherein, Ls is to intercept for finding pilot frequency position The distance that the sampling position slides backwards (the value range of Ls is between 0 and n-F-dL, wherein n is the current intercepted sampling length, not the value after the update. The larger the value of Ls, the better. In this embodiment, Ls =3823), dL=SF*dc*df (dL=0.42 in the present embodiment); G is the advance amount (G=1 in the present embodiment) of intercepting sampling data relative to the pilot position, G＞dL; N and Ni The value range of is between F+2*G and Mn (the larger the value range of Ni, the better, and the smaller the value of N, the better, in this embodiment, Ni=4096, N=274).

5) According to the synchronization adjustment control signal sent by the PC, the FPGA performs corresponding synchronization adjustments on the current OFDM symbol stream to reduce the synchronization deviation of the current OFDM symbol stream between the receiving end and the sending end, and extracts the pilot frequency from the OFDM symbol stream and data OFDM symbols; go back to step 2).

Above-mentioned step 5) in FPGA according to the synchronous adjustment control signal that PC sends to the embodiment concrete process that current OFDM symbol flow is carried out corresponding synchronous adjustment as shown in Figure 4, comprises the following steps:

51) Input baseband unsynchronized OFDM symbol stream 1;

52) According to the sampling clock adjustment control signal 2 transmitted by the PC, the sampling clock adjustment is performed on the OFDM symbol stream 1 that is not synchronized to the input baseband;

53) Carrier clock adjustment is carried out to the OFDM symbol stream output in step 52) according to the carrier clock adjustment control signal 3 transmitted by the PC;

54) sampling and counting the OFDM symbol stream output in 53), intercepting the sampling data according to the intercepting sampling control signal 4 transmitted by the PC, and sending back to the PC 5 together with the frame number cycle count value at the time of intercepting the sampling data;

55) dividing each OFDM symbol according to the OFDM symbol extraction control signal 6 transmitted by the PC, and distinguishing the pilot OFDM symbol and the data OFDM symbol;

56) Output OFDM symbol stream 7.

In the above step 54), the counting period of the intra-frame sampling of the OFDM symbol stream by the FPGA is the number of intra-frame sampling points (the number of intra-frame OFDM symbols multiplied by the symbol length of the OFDM with CP in the time domain). Steps 2) to 5) are performed in a synchronization loop so that when the synchronization state is D, the OFDM symbol stream 7 is an OFDM symbol stream that meets the synchronization accuracy requirements of the OFDM system.

6) Repeat steps 2)-step 5) in a synchronous cycle, so that the synchronization deviation is controlled within the accuracy range set by the OFDM communication system, and finally the OFDM symbol flow between transceivers is accurate Synchronize.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention. within the scope of protection.

Claims (2)

1. method that OFDM is synchronous, it is synchronous to combine to carry out OFDM with FPGA based on PC, it is characterized in that this method may further comprise the steps:

1) at the scene in the programmable logic array; Receiving terminal begins to receive the signal that is sent by transmitting terminal; And this conversion of signals become stable not synchronous OFDM symbol stream, this symbols streams is adjusted and to carrying out sample count through the OFDM symbols streams of adjustment synchronously synchronously; Connect the data transmission interface between PC and the FPGA; The intercepting sampling control signal of PC intercepting FPGA sampled data scope is set, and the initialization synchronous regime is synchronous regime not;

2) PC sends the intercepting sampling control signal to FPGA;

3) FPGA is in the sample count process that the OFDM symbol through adjustment is synchronously flowed; According to one section sampled data in the current OFDM symbol of the intercepting scope intercepting of the intercepting sampling control signal that the receives stream and store, pass the sampled data and the current sample count value of this intercepting back PC then;

4) PC sampled data the last to FPGA according to current synchronous regime or that repeatedly pass back is carried out synchronous detecting; And send and adjust control signal synchronously to FPGA; Upgrade synchronous regime simultaneously, upgrade the intercepting scope in the intercepting sampling control signal;

5) the synchronous adjustment control signal sent according to PC of FPGA is carried out the corresponding synchronous adjustment to current OFDM symbol stream; Current OFDM symbol to reduce between receiving terminal and the transmitting terminal flows synchronism deviation, and current OFDM symbol stream is extracted pilot tone and data OFDM symbol; Go back to step 2);

6) synchronous circulation carry out step 2 repeatedly)-step 5), synchronism deviation is controlled within the accuracy rating of orthogonal FDM communication system setting, the final OFDM symbol stream precise synchronization that realizes between the transmitting-receiving;

The FPGA of said step 5) carries out the corresponding synchronous adjustment according to the synchronous adjustment control signal that PC is sent to current OFDM symbol stream, may further comprise the steps:

51) the not synchronous OFDM symbol stream of input base band;

52) according to the sampling clock adjustment control signal of PC transmission the not synchronous OFDM symbol stream of input base band is carried out the sampling clock adjustment;

53) according to the carrier clock adjustment control signal of PC transmission to step 52) the OFDM symbol stream of output carries out the carrier clock adjustment;

54) pair of orthogonal frequency division multiplexing symbol stream carries out the cycle count of sampling in the frame in a frame, and the frame number of each frame is carried out the frame number cycle count; Pass back together to PC according to sampling cycle count state intercepting sampled data and intercepting sampled data frame number loop count constantly in the intercepting sampling control signal of PC transmission and the frame;

55) the OFDM symbol extraction control signal according to the PC transmission marks off each OFDM symbol, and distinguishes pilot tone OFDM symbol and data OFDM symbol;

56) output OFDM symbols streams.

2. the method for claim 1 is characterized in that, the synchronous regime that PC data the last to FPGA according to current synchronous regime or that repeatedly pass back are carried out in the synchronous detecting in the said step 4) comprises:

Synchronous regime A:PC machine does not only carry out the pilot tone tracking, output intercepting sampling control signal;

Frame synchronization state B:PC machine carries out the pilot tone tracking and sampling is followed the tracks of, output intercepting sampling control signal and sampling clock adjustment control signal;

Sample-synchronous state C:PC machine carries out the pilot tone tracking, sampling is followed the tracks of and carry out carrier track, and output intercepting sampling control signal, sampling clock adjustment control signal and carrier clock are adjusted control signal;

Final synchronous regime D:PC machine carries out pilot tone to be followed the tracks of, samples and follow the tracks of and carrier track, output intercepting sampling control signal, sampling clock adjustment control signal, carrier clock adjustment control signal and OFDM symbol extraction control signal;

Jump condition between the said state A-D comprises:

Jump condition a2: at least once find not contain in the intercepting sampled data pilot tone in nearest continuous 3 times;

Jump condition a3: do not contain pilot tone in the intercepting sampled data;

Jump condition b1: all find to contain pilot tone in the intercepting sampled data for continuous 3 times recently;

Jump condition b2: contain pilot tone in the intercepting sampled data, and at least sampling clock phase deviation is not less than sampling clock phase deviation thresholding Tps in nearest continuous 3 times;

Jump condition b3: contain pilot tone in the intercepting sampled data, and the sampling clock phase deviation is not less than Tps;

Jump condition c1: contain pilot tone in the intercepting sampled data, and nearest continuous 3 sampling clock phase deviations are all less than thresholding Tps;

Jump condition c2: contain pilot tone in the intercepting sampled data, the sampling clock phase deviation is less than Tps, and at least one subcarrier clock phase deviation is not less than thresholding Tpc in nearest continuous 3 times;

Jump condition c3: contain pilot tone in the intercepting sampled data, the sampling clock phase deviation is less than Tps, and the carrier clock phase deviation is not less than Tpc;

Jump condition d1: contain pilot tone in the intercepting sampled data, the sampling clock phase deviation is less than Tps, and nearest continuous 3 subcarrier clock phase deviations are less than Tpc;

Jump condition d2: contain pilot tone in the intercepting sampled data, the sampling clock phase deviation is less than Tps, and the carrier clock phase deviation is less than Tpc;

Transfer process between the state A-D that satisfies under the said different jump condition comprises:

When satisfying jump condition a2 or a3: be transferred to state A;

When satisfying jump condition b1 or b2 or b3: be transferred to state B;

When satisfying jump condition c1 or c2 or c3: be transferred to state C;

When satisfying jump condition d1 or d2: be transferred to state D.

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