CN101483174A - 包括具有模制器件的基板的管芯封装 - Google Patents
包括具有模制器件的基板的管芯封装 Download PDFInfo
- Publication number
- CN101483174A CN101483174A CNA2009100029615A CN200910002961A CN101483174A CN 101483174 A CN101483174 A CN 101483174A CN A2009100029615 A CNA2009100029615 A CN A2009100029615A CN 200910002961 A CN200910002961 A CN 200910002961A CN 101483174 A CN101483174 A CN 101483174A
- Authority
- CN
- China
- Prior art keywords
- attached
- die package
- package
- mold substrate
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 23
- 238000000465 moulding Methods 0.000 claims description 15
- 230000005693 optoelectronics Effects 0.000 claims description 14
- 230000003287 optical effect Effects 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims 2
- 238000013517 stratification Methods 0.000 claims 2
- 239000012778 molding material Substances 0.000 abstract description 27
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 1
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 1
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 1
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/8506—Containers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/855—Optical field-shaping means, e.g. lenses
- H10H20/856—Reflecting means
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
- Led Device Packages (AREA)
Abstract
公开了一种封装。该封装包括具有引线框结构、附连到引线框结构的第一器件、以及覆盖引线框结构和第一器件的至少一部分的制模材料的预模制基板。它还包括附连到预模制基板的第二器件。本发明公开的是包括具有模制器件的基板的管芯封装。
Description
背景技术
光耦合器包含至少一个通过光学透射介质光耦合到光接收器件的光发射器件。此安排使信息能通过包含光发射器件的一个电路传递到包含光接收器件的另一电路。两个电路之间保持高度电绝缘。因为信息跨越绝缘间隙光学地传递,所以传送是单向的。例如,光接收器件不能修改包含光发射器件的电路的操作。此特征是合乎需要的,因为例如发射器可由使用微处理器或逻辑门的低压电路驱动,而输出光接收器件可以是高压直流或交流负载电路的一部分。光隔离还防止由相对抗的输出电路引起的对输入电路的损伤。
图1示出常规光耦合器封装10的侧视图。所示出的光耦合器10包括基板24以及基板24上的焊球18。包括光发射器表面16(a)的LED(发光二极管)器件16和光电晶体管器件12(包括光接收器表面12(a))在基板24上并被光学透射介质22覆盖。
由于光电晶体管12器件的低效,光电晶体管(二极管)器件12所生成的输出电流较低(例如,约几nA,与噪声同一水平),从而接收非常有限的由LED发射的光。光电晶体管12的光接收器表面12(a)不面对LED器件16的光发射器表面16(a)。结果,来自LED器件16的光线20射向光接收器件12以及光电晶体管(或二极管)的光接收器表面12(a)少于10%的时间。
此外,LED器件16和光电晶体管12的位置由基板24中形成的焊盘限定。这可限制形成具有不同器件配置的光耦合器封装的能力。
将IC驱动器器件、LED器件、光电晶体管器件(或二极管器件)与跨阻放大器组合成一个封装(微耦合器—SIP或系统级封装)是可能的。一种将各部件配置成封装的方法是将它们全部放置在单个引线框结构上、执行引线接合工艺、且然后执行制模工艺。然而,此封装配置可能不是最有效的配置,因为这三个器件在引线框结构上相互横向有间隔。例如,如果此排列是在SOIC型封装中,则封装将具有约4 x 5mm2的大小以及约3.6mm的厚度。侧引线跨度将约为6mm。这对于一些应用而言可能太大了。
本发明的各实施例单独地和共同地解决这个问题及其它问题。
发明内容
本发明的各实施例涉及光耦合器封装、光耦合器组件、及其制造方法。
本发明的一个实施例涉及包括预模制(pre-molded)基板的管芯封装,该预模制基板包括引线框结构、附连到引线框结构的第一器件、以及覆盖引线框结构和第一器件的至少一部分的制模材料。第一器件优选是诸如驱动器IC之类的控制器件。第二器件被附连到预模制基板。第二器件优选是诸如发光二极管器件(或LED器件)之类的光电子器件。
本发明的另一实施例涉及用于形成封装的方法。该方法包括形成具有引线框结构、附连到引线框结构的第一器件、以及覆盖引线框结构和第一器件的至少一部分的制模材料的预模制基板。在预模制基板形成之后,第二器件被附连到预模制基板。
本发明的另一实施例涉及管芯封装,其包括含有引线框结构的基板、附连到引线框结构的第一器件、以及附连到基板的第二器件,其中第一器件与第二器件是叠层关系,并且其中第一和第二器件中的至少一个是光电子器件。
以下参考附图更详细地描述本发明的这些及其它实施例。
附图说明
图1示出常规光耦合器封装的侧视图。
图2示出根据本发明的实施例的光耦合器封装的顶部透视图。
图3示出根据本发明的实施例的光耦合器封装的底部透视图。
图4-5示出图2中的光耦合器封装的顶部透视图,且一些内部部件被示出。
图6示出图2中所示的光耦合器封装的底部立体图,且一些内部部件被示出。
图7示出图2中所示的光耦合器封装的俯视图,且一些内部封装部件被示出。
图8示出图2中所示的光耦合器封装的仰视图,且一些内部封装部件被示出。
图9示出图2中所示的光耦合器封装的侧视图,且一些内部封装部件被示出。
图10示出预模制基板的侧视图,且一些内部封装部件被示出。
图11(a)-11(i)示出在形成根据本发明的实施例的光耦合器封装时形成的前体。
图12-13示出本发明的实施例的另一光耦合器封装的顶部透视图,且一些内部部件被示出。
图14示出图12中所示的光耦合器封装的底部透视图。
图15示出图13中所示的光耦合器封装的一部分的近视图。
图16示出图13中所示的光耦合器封装的侧视图。
图17(a)-17(e)示出在形成根据本发明的实施例的光耦合器封装时形成的前体。
在附图中,相同的附图标记指示相同的元件,且一些元件的描述可能不会在一些实例中重复。
具体实施方式
本发明的各个实施例涉及包括诸如IC驱动器、以及引线框基板之类的预模制器件的封装、及其制造方法。在一优选实施例中,装配的方法包括在包括诸如IC驱动器件之类的控制器件和引线框结构的预模制基板上层叠LED器件和光电晶体管器件。本发明的其他实施例涉及可用来定向LED器件以使它将光直接发射到光电器件的接收器表面上的附连结构。在本发明的各实施例中附连结构和预模制基板可被组合。本发明的其他实施例可涉及凝胶圆顶(geldome)产生和模制工艺。
本发明的各实施例提供微耦合器SIP(系统级封装)方案,其可以基于包括器件和引线框结构的预模制基板的概念。在一个实施例中,LED器件和/或光电晶体管器件可被叠加在预模制基板中的控制器件上。在另一实施例中,LED器件可被置于附连结构上,以使它被定向为相对光电晶体管器件的光接收表面成某一角度。
本发明的各实施例具有许多优点。第一,本发明的各实施例可通过使定向的LED发射表面能部分地或全部地面对光耦合器中的光电晶体管器件(或二极管器件)的接收器表面来改进LED器件与光电器件(或二极管)之间的光电转换率。第二,本发明的各实施例可具有标准的LGA(接点栅格阵列)引脚输出。第三,相比平面SOIC-8型封装,根据本发明的实施例的封装的大小可被减小56%,从4 x 5mm2减小到2.5 x 3.5mm2。封装的厚度在第一设计实施例中也被减小约65%,从约3.6mm减小到约1.2mm,且针对第二设计实施例被减小约55%,从3.6mm减小到1.60mm。
本发明的一个实施例涉及包括预模制基板的管芯封装,该预模制基板包括引线框结构、附连到引线框结构的第一器件、以及覆盖引线框结构和第一器件的至少一部分的制模材料。第一器件优选是诸如驱动器IC(集成电路)之类的控制器件。第二器件被附连到预模制基板。第二器件优选是诸如发光二极管器件(或LED器件)之类的光电子器件。在本发明各实施例中使用的这些器件可以是半导体管芯的形式。
在这里所描述的各个具体实施例中,第一和第二器件分别优选是控制和光电子器件。示例性光电子器件可包括电学以及光学性质(例如电输入和光输出或反之亦然)。然而,可以理解,本发明的各个实施例可应用于可具有纯粹的电特性(例如在没有光透射的情况下)的封装。例如,第一和第二器件中的一个或两个在本发明的其他实施例中可以是诸如MOSFET之类的纯粹电气器件。
图2示出根据本发明的实施例的封装100的顶部透视图。封装100包括具有引线框结构120(a)和第一制模材料120(b)的预模制基板120。第二制模材料140在预模制基板120上形成。第一制模材料120(b)和第二制模材料140可以是相同或不同的。在任一种情况下,第一制模材料120(b)和第二制模材料140之间可以有平坦界面,因为第一制模材料120(b)和第二制模材料140在不同时间模制。
在图2中,L可约为3.5mm,W可约为2.5mm,T1可约为0.4mm,而T2可约为1.20mm。当然,本发明的各实施例不限于这些大小,且适当封装的尺寸可以大于或小于这些尺寸。
图3示出图2中所示的封装100的底部透视图。图3示出底部焊盘120(a)-1和侧面连接条120(a)-2。底部焊盘在示出的示例中包括以下标记:NC(未连接);Vo(输出数据);GND2(输出接地);VDD1(输入电源电压),VDD2(输出供电电压),Vin(输入数据),GND1(输入接地),以及阳极。可以理解,本发明的各实施例不限于图3中所示的具体焊盘标记。
图4和5分别示出图1中所示的封装100的顶部透视图,且一些内部部件被示出。
图4示出在预模制基板120上形成的第二制模材料140。透光材料190存在于第二制模材料140和预模制基板120之间。预模制基板120的引线框结构120(a)包括多个用于引线接合的导电焊盘区120(a)-2。各引线184、193(a)、193(b)、193(c)穿入透光材料,并且接合到各导电焊盘区120(a)-2。在封装100内部的导电焊盘区120(a)-2的表面与在封装100内部但在基板120外部的制模材料120(b)的表面基本共面。
图5示出安装在引线框结构120(a)的第一管芯附连焊盘120(c)-1上的光发射器件112,以及安装在第二管芯附连焊盘120(c)-2上的光接收器件116。诸如焊料之类的导电粘合剂可被用来将光接收器件116和光发射器件112连接到引线框结构120的管芯附连焊盘120(c)-1和120(c)-2。引线184将光发射器件112的上表面连接到焊盘区之一120(a)-2。三条接合引线193(a)、193(b)、193(c)还将光接收器件116的上表面的输入和/或输出连接到其他焊盘区120(a)-2。光发射器件112和光接收器件116如图4所示地被透光材料190覆盖,以使光信号可从光发射器件112传递到光接收器件116。在一些情况下透光材料190也可被称为“光耦合凝胶”。
图6示出图2中所示的封装100的下侧。如图所示,控制器件56被安装到焊盘120(c)-1的与光发射器件112附连到其上的表面相反的表面。如图所示,多条接合引线58、59使焊盘区120(a)-2与控制器件56的外表面连接。在图5中,管芯附连焊盘120(c)-2的与使光接收器件116安装到其上的表面相反的表面没有器件安装于其上。然而,在本发明的其他各实施例中器件可被安装于其上。
图7示出图2中所示的光耦合器封装的俯视图,且一些内部封装部件被示出。图8示出图2中所示的光耦合器封装的仰视图,且一些内部封装部件被示出。图9示出图2中所示的光耦合器封装的侧视图,且一些内部封装部件被示出。以上已描述了图7-9中的各部件。然而,如图7-9所示,封装100具有矩形的侧面轮廓和顶部轮廓。它还可被表征为“无引线”封装,因为引线没有伸出第二制模材料140的侧面。虽然示出了无引线封装,但可以理解本发明的各实施例还可包括有引线封装。
图10示出预模制基板120的侧视图,且一些内部封装部件被示出。如图所示,引线框结构120(a)的外表面与第一制模材料120(b)的外表面基本共面。
本发明的其他实施例可涉及用于制造类似上述的光耦合器封装的方法。本发明的一个实施例涉及包括形成预模制基板的方法,该预模制基板包括引线框结构、附连到引线框结构的第一器件(例如诸如驱动器IC之类的控制器件)、以及覆盖引线框结构和第一器件的至少一部分的制模材料。在预模制基板形成之后,第二器件(例如诸如LED器件之类的光发射器件)以及第三器件(例如诸如光电晶体管器件之类的光接收器件)被附连到预模制基板。器件到基板的附连可通过包括附连结构和导电粘合剂的各种结构完成。
图11(a)-11(i)示出在形成根据本发明的实施例的光耦合器封装时形成的前体。
图11(a)示出引线框结构120(a)。引线框结构120(a)可通过蚀刻、冲压或任何其他适当的工艺获得。用于引线框结构的适当材料包括铜、铝及其合金。在一些实施例中,可使用可焊金属或其他类型的金属(例如Ni、Pd等)电镀引线框结构。此外,引线框结构可形成为连续或不连续的金属部件。
如图所示,引线框结构120(a)可包括管芯附连焊盘120(c)-1、120(c)-2以及接合焊盘区120(a)-2和焊盘120(a)-1。如图所示,接合焊盘区120(a)-2可从各个焊盘120(a)-1横向地在两个或三个方向上延伸。一些区域可被部分地蚀刻(例如半蚀刻)以帮助将制模材料锁定到第二引线框结构120(a)。
在图11(b),控制器件56(例如驱动器IC)被安装到引线框结构120的第一管芯附连焊盘120(c)-1。如图所示,引线框结构120中的第二管芯附连焊盘120(c)-2与第一管芯附连焊盘120(c)-1分离。可使用包括焊料的任何适当的导电粘合剂将控制器件56安装到第一管芯附连焊盘120(c)-1。
图11(c)示出使控制器件56的外表面与接合焊盘区120(a)-2连接的多条接合引线58。可使用任何适当的常规引线接合工艺。此外,适当的接合引线可包括铜、金、或包括涂覆有贵金属的铜引线的合成物。
图11(d)示出模制之后的预模制基板120。第一制模材料120(b)被模制在引线框结构120(a)的周围。如图所示,焊盘表面120(a)-1通过第一制模材料120(b)暴露,并与制模材料120(b)的外表面基本共面。通过引用完整结合于此的美国专利No.7,061,077公开了其他适当的预模制工艺。
图11(e)示出倒装的预模制基板120。管芯附连焊盘120(c)-1、120(c)-2的表面以及接合焊盘区120(a)-2的表面通过第一制模材料120暴露,并且与第一制模材料120的外表面基本共面。
在倒装基板120之后,如图11(f)所示,光发射器件112和光接收器件116可被附连到预模制基板120的管芯附连焊盘120(c)-1、120(c)-2。包括焊料的任何适当的导电粘合剂可被用来将光发射器件112和光接收器件116附连到预模制基板120的管芯附连焊盘120(c)-1和120(c)-2。
在将光发射器件112和光接收器件116接合到预模制基板120的管芯附连焊盘120(c)-1、120(c)-2之后,如图11(g)所示,引线184、193(a)、193(b)、193(c)可被用来使光发射器件112和光接收器件116与接合焊盘区120(a)-2引线接合。
在引线接合之后,如图11(h)所示,透光材料190可被沉积在基板120与光发射器件112和光接收器件116上。透光材料190然后可被固化、或被部分凝固。如果需要,光反射涂层可被沉积在透光材料190上以阻止光在透光材料190内从光发射器件112传输到光接收器件116。
在基板120上沉积透光材料190之后,可在基板120上形成第二制模材料140以形成封装100。可使用任何适当的制模工艺,包括使用具有模压的模制工具的常规模制工艺。在模制之后,可执行单片化工艺来使所形成的封装与封装阵列中的其他封装分离。
图12-13示出本发明的另一光耦合器封装实施例的顶部透视图,且一些内部部件被示出。图14示出图11中所示的光耦合器封装的底部透视图。图15示出图11中所示的光耦合器封装的一部分的近视图。以上描述了图12-15中的许多部件,并且无需重复这些描述。
图13具体地示出包括用于垂直安装光发射器件112的侧面安装焊盘的附连结构192。图15示出附连到基板120的附连结构192,以及附连到附连结构192的焊盘的垂直定向光发射器件112。
图16示出图11中所示的光耦合器封装的侧视图。附图标记88示出附连结构192的部分蚀刻(例如半蚀刻)区。该部分蚀刻区使第二制模材料140更易于锁定到附连结构190。此外,距离T3可约为0.45mm。因为光发射器件112的发射表面至少部分地面对光接收器件116的接收表面,所以光从光发射器件112到光接收器件的传输比在图1中所示的常规封装中更有效率。
附连结构192安装到基板120、以及管芯封装100的后续形成在图17(a)-17(e)中示出。如图17(a)所示,附连结构192首先通过蚀刻、冲压或者任何其他适当的工艺获得。它可由铜或任何其他适当的导电材料制成。附连结构192可包括第一部件192(a)和第二部件192(b)。第一部件192(a)可包括第一基板接合部分192(a)-1,第二和第三垂直中间部分192(a)-2、192(a)-3,以及第四引线接合部分192(a)-4。第二部件192(a)可包括第一基板接合部分192(b)-1,第二和第三垂直中间部分192(b)-2、192(b)-3,以及第四器件接合部分192(b)-4。横向连接条178还从第一和第二部件横向地向外延伸。连接条178可使用其他附连结构将各部件结合到外框。
在获得附连结构192之后,光发射器件112可被安装到第四器件接合部分192(b)-4。在光发射器件112被安装到第四器件接合部分192(b)-4之后,引线可被接合到第四接合部分192(a)-4,如图17(b)所示。
如图17(c)所示,图17(b)中所示的前体然后被附连到预模制基板120。包括焊料的任何适当的粘合剂可被用来将附连结构192附连到基板120。以上参考图11(a)-11(f)描述了预模制基板120的形成、以及后续光接收器件116的安装。引线可从192(a)-1被接合到120(a)-2。
如图17(c)所示,第四器件接合部分192(b)-4可定向光发射器件112,以使它(以及从而其发光表面)可被定向为相对安装在预模制基板120上的光接收器件116的光接收表面成某一角度(例如基本垂直地)。
图17(d)示出沉积透光材料190。透光材料190然后可被固化、或被部分凝固。如果需要,光反射涂层可被沉积在透光材料190上以阻止光在透光材料190内从光发射器件112传输到光接收器件116。
在基板120上沉积透光材料190之后,可在基板120上形成第二制模材料140以形成封装100。可使用任何适当的制模工艺,包括使用具有模压的模制工具的常规模制工艺。
上述光耦合器封装可在包括电路基板的电气组件、以及可由蜂窝电话和计算机体现的系统中使用。
虽然上述涉及本发明的某些优选实施例,但可在不背离本发明的基本范围的情况下设计本发明的其他和进一步的实施例。这些替换实施例旨在被包括在本发明的范围内。此外,本发明的一个或多个实施例的特征可与本发明的其他实施例的一个或多个特征组合,而不背离本发明的范围。
Claims (21)
1.一种管芯封装,包括:
预模制基板,所述预模制基板包括引线框结构、附连到所述引线框结构的第一器件、以及覆盖所述引线框结构和所述第一器件的至少一部分的制模材料;以及
附连到所述预模制基板的第二器件。
2.如权利要求1所述的管芯封装,其特征在于,所述第二器件包括光电子器件。
3.如权利要求1所述的管芯封装,其特征在于,所述第一器件包括控制器件。
4.如权利要求1所述的管芯封装,其特征在于,进一步包括第三器件,其中所述第三器件被安装在所述预模制基板上。
5.如权利要求1所述的管芯封装,其特征在于,进一步包括第三器件,其中所述第三器件被安装在所述预模制基板上,其中所述第二器件和所述第三器件包括光电子器件且其中所述第一器件包括控制器件。
6.如权利要求1所述的管芯封装,其特征在于,所述引线框结构包括管芯附连焊盘,其中所述第一管芯被安装在所述管芯附连焊盘的第一表面上且其中所述第二管芯被安装在所述管芯附连焊盘的第二表面上。
7.如权利要求1所述的管芯封装,其特征在于,所述管芯封装是光耦合器封装。
8.如权利要求1所述的管芯封装,其特征在于,所述制模材料是第一制模材料,且其中所述管芯封装进一步包括第三器件,其中所述第三器件被安装在所述预模制基板上,其中所述第二器件和所述第三器件包括光电子器件且其中所述第一器件包括控制器件,且其中所述管芯封装进一步包括覆盖所述第二器件和所述第三器件的第二模制材料。
9.如权利要求1所述的管芯封装,其特征在于,进一步包括附连结构,其中所述附连结构包括垂直结构,且其中所述第一器件被附连到所述垂直结构,且其中所述附连结构被附连到所述预模制基板。
10.如权利要求9所述的管芯封装,其特征在于,所述第一器件是控制器件。
11.一种方法,包括:
形成预模制基板,所述预模制基板包括引线框结构、附连到所述引线框结构的第一器件、以及覆盖所述引线框结构和所述第一器件的至少一部分的制模材料;以及
将第二器件附连到所述预模制基板。
12.如权利要求11所述的方法,其特征在于,所述第二器件包括光电子器件。
13.如权利要求11所述的方法,其特征在于,所述第一器件包括控制器件。
14.如权利要求11所述的方法,其特征在于,进一步包括将第三器件附连到所述预模制基板。
15.如权利要求11所述的方法,其特征在于,进一步包括将第三器件附连到所述预模制基板,且其中所述第二器件和所述第三器件包括光电子器件且其中所述第一器件包括控制器件。
16.如权利要求11所述的方法,其特征在于,所述引线框结构包括管芯附连焊盘,其中所述第一管芯被安装在所述管芯附连焊盘的第一表面上且其中所述第二管芯被安装在所述管芯附连焊盘的第二表面上。
17.如权利要求11所述的方法,其特征在于,管芯封装在将所述第二器件附连到所述预模制基板之后形成,且其中所述管芯封装是光耦合器封装。
18.如权利要求11所述的方法,其特征在于,所述制模材料是第一制模材料,且其中所述方法进一步包括在所述第二器件上模制第二制模材料。
19.如权利要求11所述的方法,其特征在于,进一步包括将所述第二器件附连到附连结构,然后将所述附连结构附连到所述预模制基板。
20.如权利要求11所述的方法,其特征在于,所述第一器件包括控制器件且所述第二器件包括光电子器件。
21.一种管芯封装,包括:
包括引线框结构、附连到所述引线框结构的第一器件的基板;以及
附连到所述基板的第二器件,其中所述第一器件与所述第二器件是叠层关系,且其中所述第一和所述第二器件中的至少一个是光电子器件。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/971,556 | 2008-01-09 | ||
US11/971,556 US8106406B2 (en) | 2008-01-09 | 2008-01-09 | Die package including substrate with molded device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101483174A true CN101483174A (zh) | 2009-07-15 |
Family
ID=40843903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2009100029615A Pending CN101483174A (zh) | 2008-01-09 | 2009-01-09 | 包括具有模制器件的基板的管芯封装 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8106406B2 (zh) |
CN (1) | CN101483174A (zh) |
TW (1) | TW200941654A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106783833A (zh) * | 2016-12-30 | 2017-05-31 | 深圳市富友昌科技股份有限公司 | 一种化合物电池发光装置 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7973393B2 (en) * | 2009-02-04 | 2011-07-05 | Fairchild Semiconductor Corporation | Stacked micro optocouplers and methods of making the same |
TW201133949A (en) * | 2010-03-16 | 2011-10-01 | Ying-Chia Chen | Light emitting diode package and lamp with the same |
US8577190B2 (en) | 2010-03-23 | 2013-11-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Optocoupler |
US8571360B2 (en) * | 2010-03-23 | 2013-10-29 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Optocoupler with light guide defining element |
US8412006B2 (en) * | 2010-03-23 | 2013-04-02 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | Optocoupler |
USD644191S1 (en) * | 2010-09-29 | 2011-08-30 | Kabushiki Kaisha Toshiba | Portion of a light-emitting diode |
TWD143605S1 (zh) * | 2010-09-29 | 2011-11-01 | 東芝股份有限公司 | 發光二極體 |
TWD143606S1 (zh) * | 2010-09-29 | 2011-11-01 | 東芝股份有限公司 | 發光二極體 |
US8421204B2 (en) | 2011-05-18 | 2013-04-16 | Fairchild Semiconductor Corporation | Embedded semiconductor power modules and packages |
FR2977714B1 (fr) * | 2011-07-08 | 2013-07-26 | St Microelectronics Grenoble 2 | Boitier electronique optique |
US8563337B2 (en) * | 2011-10-24 | 2013-10-22 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Simultaneous silicone dispension on coupler |
USD728491S1 (en) * | 2012-12-12 | 2015-05-05 | Nichia Corporation | Light emitting diode |
USD731987S1 (en) * | 2012-12-28 | 2015-06-16 | Nichia Corporation | Light emitting diode |
USD763206S1 (en) * | 2015-01-29 | 2016-08-09 | Advanced Optoelectronic Technology, Inc. | Light emitting diode package |
JP6325471B2 (ja) | 2015-03-02 | 2018-05-16 | 株式会社東芝 | 光結合装置および絶縁装置 |
JP6371725B2 (ja) * | 2015-03-13 | 2018-08-08 | 株式会社東芝 | 半導体モジュール |
CN105514055B (zh) * | 2015-12-01 | 2019-03-19 | 世亿盟科技(深圳)有限公司 | 自发电且可光谱侦测的芯片模组及其设备 |
DE102018100946A1 (de) * | 2018-01-17 | 2019-07-18 | Osram Opto Semiconductors Gmbh | Bauteil und verfahren zur herstellung eines bauteils |
DE102019127783A1 (de) | 2019-10-15 | 2021-04-15 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches bauelement und verfahren zur herstellung eines solchen |
Family Cites Families (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3956821A (en) * | 1975-04-28 | 1976-05-18 | Fairchild Camera And Instrument Corporation | Method of attaching semiconductor die to package substrates |
US4058899A (en) * | 1976-08-23 | 1977-11-22 | Fairchild Camera And Instrument Corporation | Device for forming reference axes on an image sensor array package |
US4680613A (en) * | 1983-12-01 | 1987-07-14 | Fairchild Semiconductor Corporation | Low impedance package for integrated circuit die |
US4751199A (en) * | 1983-12-06 | 1988-06-14 | Fairchild Semiconductor Corporation | Process of forming a compliant lead frame for array-type semiconductor packages |
US4772935A (en) * | 1984-12-19 | 1988-09-20 | Fairchild Semiconductor Corporation | Die bonding process |
US5148243A (en) | 1985-06-25 | 1992-09-15 | Hewlett-Packard Company | Optical isolator with encapsulation |
US4890153A (en) * | 1986-04-04 | 1989-12-26 | Fairchild Semiconductor Corporation | Single bonding shelf, multi-row wire-bond finger layout for integrated circuit package |
US4720396A (en) * | 1986-06-25 | 1988-01-19 | Fairchild Semiconductor Corporation | Solder finishing integrated circuit package leads |
US4791473A (en) * | 1986-12-17 | 1988-12-13 | Fairchild Semiconductor Corporation | Plastic package for high frequency semiconductor devices |
US4839717A (en) * | 1986-12-19 | 1989-06-13 | Fairchild Semiconductor Corporation | Ceramic package for high frequency semiconductor devices |
US4731701A (en) * | 1987-05-12 | 1988-03-15 | Fairchild Semiconductor Corporation | Integrated circuit package with thermal path layers incorporating staggered thermal vias |
US4796080A (en) * | 1987-07-23 | 1989-01-03 | Fairchild Camera And Instrument Corporation | Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate |
US5327325A (en) * | 1993-02-08 | 1994-07-05 | Fairchild Space And Defense Corporation | Three-dimensional integrated circuit package |
US5545893A (en) * | 1994-12-23 | 1996-08-13 | Motorola, Inc. | Optocoupler package and method for making |
JP3638328B2 (ja) * | 1994-12-30 | 2005-04-13 | 株式会社シチズン電子 | 表面実装型フォトカプラ及びその製造方法 |
US5646446A (en) * | 1995-12-22 | 1997-07-08 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
US6133067A (en) * | 1997-12-06 | 2000-10-17 | Amic Technology Inc. | Architecture for dual-chip integrated circuit package and method of manufacturing the same |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
US6424035B1 (en) * | 1998-11-05 | 2002-07-23 | Fairchild Semiconductor Corporation | Semiconductor bilateral switch |
KR100335480B1 (ko) * | 1999-08-24 | 2002-05-04 | 김덕중 | 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지 |
KR100335481B1 (ko) * | 1999-09-13 | 2002-05-04 | 김덕중 | 멀티 칩 패키지 구조의 전력소자 |
US6720642B1 (en) * | 1999-12-16 | 2004-04-13 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package and method of manufacture thereof |
US6344687B1 (en) * | 1999-12-22 | 2002-02-05 | Chih-Kung Huang | Dual-chip packaging |
US6489653B2 (en) * | 1999-12-27 | 2002-12-03 | Kabushiki Kaisha Toshiba | Lateral high-breakdown-voltage transistor |
US6989588B2 (en) | 2000-04-13 | 2006-01-24 | Fairchild Semiconductor Corporation | Semiconductor device including molded wireless exposed drain packaging |
US6556750B2 (en) * | 2000-05-26 | 2003-04-29 | Fairchild Semiconductor Corporation | Bi-directional optical coupler |
KR100370231B1 (ko) * | 2000-06-13 | 2003-01-29 | 페어차일드코리아반도체 주식회사 | 리드프레임의 배면에 직접 부착되는 절연방열판을구비하는 전력 모듈 패키지 |
KR100403608B1 (ko) * | 2000-11-10 | 2003-11-01 | 페어차일드코리아반도체 주식회사 | 스택구조의 인텔리젠트 파워 모듈 패키지 및 그 제조방법 |
KR100374629B1 (ko) * | 2000-12-19 | 2003-03-04 | 페어차일드코리아반도체 주식회사 | 얇고 작은 크기의 전력용 반도체 패키지 |
US6469384B2 (en) * | 2001-02-01 | 2002-10-22 | Fairchild Semiconductor Corporation | Unmolded package for a semiconductor device |
US6891257B2 (en) * | 2001-03-30 | 2005-05-10 | Fairchild Semiconductor Corporation | Packaging system for die-up connection of a die-down oriented integrated circuit |
US6645791B2 (en) * | 2001-04-23 | 2003-11-11 | Fairchild Semiconductor | Semiconductor die package including carrier with mask |
US6893901B2 (en) * | 2001-05-14 | 2005-05-17 | Fairchild Semiconductor Corporation | Carrier with metal bumps for semiconductor die packages |
US7061080B2 (en) * | 2001-06-11 | 2006-06-13 | Fairchild Korea Semiconductor Ltd. | Power module package having improved heat dissipating capability |
US6683375B2 (en) * | 2001-06-15 | 2004-01-27 | Fairchild Semiconductor Corporation | Semiconductor die including conductive columns |
US6633030B2 (en) * | 2001-08-31 | 2003-10-14 | Fiarchild Semiconductor | Surface mountable optocoupler package |
US6774465B2 (en) * | 2001-10-05 | 2004-08-10 | Fairchild Korea Semiconductor, Ltd. | Semiconductor power package module |
US6891256B2 (en) * | 2001-10-22 | 2005-05-10 | Fairchild Semiconductor Corporation | Thin, thermally enhanced flip chip in a leaded molded package |
US6674157B2 (en) * | 2001-11-02 | 2004-01-06 | Fairchild Semiconductor Corporation | Semiconductor package comprising vertical power transistor |
US6566749B1 (en) * | 2002-01-15 | 2003-05-20 | Fairchild Semiconductor Corporation | Semiconductor die package with improved thermal and electrical performance |
US6867489B1 (en) * | 2002-01-22 | 2005-03-15 | Fairchild Semiconductor Corporation | Semiconductor die package processable at the wafer level |
US6830959B2 (en) * | 2002-01-22 | 2004-12-14 | Fairchild Semiconductor Corporation | Semiconductor die package with semiconductor die having side electrical connection |
DE10392377T5 (de) * | 2002-03-12 | 2005-05-12 | FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) | Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer |
US7122884B2 (en) * | 2002-04-16 | 2006-10-17 | Fairchild Semiconductor Corporation | Robust leaded molded packages and methods for forming the same |
US6836023B2 (en) * | 2002-04-17 | 2004-12-28 | Fairchild Semiconductor Corporation | Structure of integrated trace of chip package |
KR100843737B1 (ko) * | 2002-05-10 | 2008-07-04 | 페어차일드코리아반도체 주식회사 | 솔더 조인트의 신뢰성이 개선된 반도체 패키지 |
US7061077B2 (en) * | 2002-08-30 | 2006-06-13 | Fairchild Semiconductor Corporation | Substrate based unmolded package including lead frame structure and semiconductor die |
US6777800B2 (en) * | 2002-09-30 | 2004-08-17 | Fairchild Semiconductor Corporation | Semiconductor die package including drain clip |
US6943434B2 (en) * | 2002-10-03 | 2005-09-13 | Fairchild Semiconductor Corporation | Method for maintaining solder thickness in flipchip attach packaging processes |
KR100958422B1 (ko) * | 2003-01-21 | 2010-05-18 | 페어차일드코리아반도체 주식회사 | 고전압 응용에 적합한 구조를 갖는 반도체 패키지 |
US7217594B2 (en) * | 2003-02-11 | 2007-05-15 | Fairchild Semiconductor Corporation | Alternative flip chip in leaded molded package design and method for manufacture |
US7271497B2 (en) * | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
US6867481B2 (en) * | 2003-04-11 | 2005-03-15 | Fairchild Semiconductor Corporation | Lead frame structure with aperture or groove for flip chip in a leaded molded package |
US7315077B2 (en) * | 2003-11-13 | 2008-01-01 | Fairchild Korea Semiconductor, Ltd. | Molded leadless package having a partially exposed lead frame pad |
US7196313B2 (en) * | 2004-04-02 | 2007-03-27 | Fairchild Semiconductor Corporation | Surface mount multi-channel optocoupler |
US7242076B2 (en) * | 2004-05-18 | 2007-07-10 | Fairchild Semiconductor Corporation | Packaged integrated circuit with MLP leadframe and method of making same |
US7256479B2 (en) * | 2005-01-13 | 2007-08-14 | Fairchild Semiconductor Corporation | Method to manufacture a universal footprint for a package with exposed chip |
US7285849B2 (en) * | 2005-11-18 | 2007-10-23 | Fairchild Semiconductor Corporation | Semiconductor die package using leadframe and clip and method of manufacturing |
US7371616B2 (en) * | 2006-01-05 | 2008-05-13 | Fairchild Semiconductor Corporation | Clipless and wireless semiconductor die package and method for making the same |
US7408245B2 (en) * | 2006-12-22 | 2008-08-05 | Powertech Technology Inc. | IC package encapsulating a chip under asymmetric single-side leads |
US7791084B2 (en) | 2008-01-09 | 2010-09-07 | Fairchild Semiconductor Corporation | Package with overlapping devices |
US7825502B2 (en) | 2008-01-09 | 2010-11-02 | Fairchild Semiconductor Corporation | Semiconductor die packages having overlapping dice, system using the same, and methods of making the same |
US20090194857A1 (en) | 2008-02-01 | 2009-08-06 | Yong Liu | Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same |
US7915721B2 (en) | 2008-03-12 | 2011-03-29 | Fairchild Semiconductor Corporation | Semiconductor die package including IC driver and bridge |
US8018054B2 (en) | 2008-03-12 | 2011-09-13 | Fairchild Semiconductor Corporation | Semiconductor die package including multiple semiconductor dice |
US7768108B2 (en) | 2008-03-12 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die package including embedded flip chip |
-
2008
- 2008-01-09 US US11/971,556 patent/US8106406B2/en active Active
-
2009
- 2009-01-06 TW TW098100177A patent/TW200941654A/zh unknown
- 2009-01-09 CN CNA2009100029615A patent/CN101483174A/zh active Pending
-
2011
- 2011-09-27 US US13/246,682 patent/US8525192B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106783833A (zh) * | 2016-12-30 | 2017-05-31 | 深圳市富友昌科技股份有限公司 | 一种化合物电池发光装置 |
Also Published As
Publication number | Publication date |
---|---|
US20090174048A1 (en) | 2009-07-09 |
TW200941654A (en) | 2009-10-01 |
US8106406B2 (en) | 2012-01-31 |
US20120012993A1 (en) | 2012-01-19 |
US8525192B2 (en) | 2013-09-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101483174A (zh) | 包括具有模制器件的基板的管芯封装 | |
US7659531B2 (en) | Optical coupler package | |
CN100590779C (zh) | 表面贴装多通道光耦合器 | |
US7705468B2 (en) | Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same | |
US8981550B2 (en) | Semiconductor package with alternating thermal interface and adhesive materials and method for manufacturing the same | |
US20070090508A1 (en) | Multi-chip package structure | |
CN102341899A (zh) | 具有多种ic封装构造的无引线阵列塑料封装 | |
US7973393B2 (en) | Stacked micro optocouplers and methods of making the same | |
TW202113991A (zh) | 形成具有導電的互連框的半導體封裝之方法及結構 | |
US20100140786A1 (en) | Semiconductor power module package having external bonding area | |
US7589338B2 (en) | Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice | |
US8318548B2 (en) | Method for manufacturing semiconductor device | |
TW200729429A (en) | Semiconductor package structure and fabrication method thereof | |
US9041170B2 (en) | Multi-level semiconductor package | |
US7667306B1 (en) | Leadframe-based semiconductor package | |
US7791084B2 (en) | Package with overlapping devices | |
US20090140266A1 (en) | Package including oriented devices | |
US20130009294A1 (en) | Multi-chip package having leaderframe-type contact fingers | |
KR102016019B1 (ko) | 고열전도성 반도체 패키지 | |
US9184149B2 (en) | Semiconductor device with an interlocking wire bond | |
US20080073772A1 (en) | Stacked semiconductor package and method of manufacturing the same | |
CN106601694B (zh) | 堆叠结构及其制造方法 | |
CN104576904B (zh) | 发光二极管封装结构及其制造方法 | |
CN101281903B (zh) | 多重封装的封装结构 | |
KR19990026494A (ko) | 듀얼 적층패키지 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20090715 |