[go: up one dir, main page]

CN101414565B - 形成预成型引线框的方法 - Google Patents

形成预成型引线框的方法 Download PDF

Info

Publication number
CN101414565B
CN101414565B CN2007101802438A CN200710180243A CN101414565B CN 101414565 B CN101414565 B CN 101414565B CN 2007101802438 A CN2007101802438 A CN 2007101802438A CN 200710180243 A CN200710180243 A CN 200710180243A CN 101414565 B CN101414565 B CN 101414565B
Authority
CN
China
Prior art keywords
lead frame
band
moulding compound
lead
mould
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007101802438A
Other languages
English (en)
Other versions
CN101414565A (zh
Inventor
徐雪松
白志刚
许南
姚晋钟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Freescale Carle Semiconductor (china) Co Ltd
Original Assignee
Freescale Carle Semiconductor (china) Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Carle Semiconductor (china) Co Ltd filed Critical Freescale Carle Semiconductor (china) Co Ltd
Priority to CN2007101802438A priority Critical patent/CN101414565B/zh
Priority to US12/126,943 priority patent/US7723163B2/en
Publication of CN101414565A publication Critical patent/CN101414565A/zh
Application granted granted Critical
Publication of CN101414565B publication Critical patent/CN101414565B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种形成增加括脚的预成型引线框的方法，该方法包括以下步骤：将第一带附接到引线框的第一面和将第二带附接到引线框的第二面。将附接了带的引线框放进模具中，并开始模塑料的第一流。该模塑料的第一流填进第一带和模具的上模套之间的空间。然后，开始模塑料的第二流。该模塑料的第二流填进引线框的管芯焊盘和引线之间的空间。接着，将第一带和第二带从引线框中移走。由于模塑料的第一流压低了第一带，所以提供了增大的括脚。

Description

形成预成型引线框的方法
技术领域
[01]本发明涉及集成电路(IC)的封装，尤其涉及一种形成预成型引线框的方法，该预成型引线框用于形成半导体封装。
背景技术
[02]引线框是向半导体管芯提供电互连的结构。也就是说，将管芯附接到引线框上，接着，通常通过引线接合工艺用导线将管芯的焊盘电连接到引线框的引线上。然后，利用塑性模塑料(mold compound)对管芯、引线框和导线进行封装。引线的暴露区向管芯提供电互连。
[03]为了向其它器件提供优良的电连接，必须使引线的一些部分充分暴露。如果该引线区域由模塑料覆盖、或者未被充分暴露、或者不易接触到，就会出现诸如引线与衬底或印刷电路板(PCB)的可焊性问题。
[04]图1-4图解说明了半导体封装工艺的步骤。图1示出了一对包括半蚀刻部分12的引线框10。集成电路14附接到引线框10的台板(flag)16处。通常通过引线接合工艺用导线18将集成电路14电连接到引线框10的引线20。在附图中，两个引线框10是引线框的条的部分，该引线框条被安装到带22上。图2示出了放置在模套(mold chase)24中的引线框10。箭头表示模流的方向。图3示出了注入模套24中的模塑料26。模塑料26覆盖了引线框10、集成电路14和导线18。
[05]图4是引线框10之一的接触区的放大视图，其具体为台板16和引线20的半蚀刻部分。注意，模塑料26填进了台板16和引线20之间的空间，此外，模塑料26和引线框的底部表面是平坦的。能增加引线框和模塑料之间的括脚(stand-off)是有益的。
附图说明
[06]当结合附图阅读时，能更好地理解以下本发明的优选实施例的详细描述。通过示例来说明本发明，而附图不限制本发明，其中，相同的附图标记表示相同的元素。应该明白：为了便于理解本发明，附图未按比例且被简化。
[07]图1是其上被附接有管芯的传统引线框条的放大截面视图；
[08]图2是放置在模套中的、图1的引线框的放大截面视图；
[09]图3是其中注入模塑料的图2的模套中的引线框的放大截面视图；
[10]图4是从模套中移走后的、图1的引线框的部分的放大截面视图；
[11]图5-9是图解说明根据本发明实施例的形成预成型引线框的方法的放大截面视图；和
[12]图10是图解说明根据本发明实施例的封装半导体集成电路的方法的放大截面视图。
具体实施方式
[13]以下结合附图给出的详细说明旨在描述本发明的当前优选实施例，而并不代表可实施本发明的唯一形式。应该理解：通过被认为包括在本发明的精神和范围内的不同实施例可实现相同的和等同的功能。在附图中，相同的附图标记始终表示相同的元素。
[14]在一实施例中，本发明提供了一种形成预成型引线框的方法，该方法包括以下步骤：将第一带附接到引线框的第一面，该引线框包括引线和管芯焊盘，而将第二带附接到所述引线框的相反的第二面。将附接了带的引线框装入模具，而将模塑料的第一流注入模具，使得该模塑料流进第一带和上模套之间的空间。开始将模塑料的第二流注入模具，并且该模塑料流进第一带和第二带之间(即，引线框的引线和管芯焊盘之间)的空间。将引线框从模具中移走，且将第一带和第二带移走，使得引线和管芯焊盘暴露。或者，可将第二带移走，而留下第一带以进行进一步处理。
[15]在另一实施例中，本发明提供了一种预成型多个引线框的方法。除了给多个引线框附接带并放置在模具中，该方法类似于上述方法。引线框可以条或阵列形式来提供，随后利用单切处理而将其分开。
[16]在本发明的又一实施例中，提供了一种封装半导体集成电路的方法。该方法包括：将第一带附接到引线框的第一面，该引线框包括引线和管芯焊盘；将第二带附接到引线框的相反的第二面；将引线框装入模具；开始将模塑料的第一流注入模具，其中，该模塑料流进第一带和模具的上模套之间的空间；开始将模塑料的第二流注入模具，其中，该模塑料流进第一带和第二带之间的空间；将引线框从模具中移走；和将第二带从引线框移走，从而使得引线框的引线和管芯焊盘暴露。接着，将半导体集成电路附接到管芯焊盘，并执行引线接合工艺以将导线附接在集成电路的焊盘和引线框的引线之间。用模塑料对所述引线框、集成电路和导线进行封装，然后，将第一带从引线框的第一面移走，从而提供封装好的半导体集成电路。模塑料的第一流压低引线和管芯焊盘之间的第一带，使得在移走第一带时形成括脚。
[17]现在将参考附图5-9来描述一种形成预成型引线框的方法。
[18]现在参考附图5，提供了一个或多个引线框100(在该示例中，示出了两个)。引线框100包括可环绕相应的管芯焊盘104的引线102。引线框100可由侧条106界定。通过切割、压印或蚀刻片料(sheet stock)可将引线框100形成条或阵列形式。形成引线框100的片料是如铜或铝的导电金属，然而，可以使用和涂敷其它金属或合金。在一实施例中，导电材料片102由诸如铜箔的裸金属形成，并且约0.5mm厚。然而，金属片102的特定材料、大小或厚度不限制本发明。在现有技术中，众所周知引线框，并且众所周知这样的引线框的材料厚度和强度等。引线框被广泛用于半导体工业并可容易地从许多商业提供商处获得。引线框100的第一面或顶面已被蚀刻，使得引线102和管芯104之间的空间增加，如108所示。
[19]将第一带110设置在引线框100的第一表面。优选地，第一带110从侧条106中的一个几乎延伸到与侧条106相对的另一个，并且覆盖引线框100的蚀刻面。第一带110覆盖引线框100的第一面大约95％。将第二带112设置在引线框100的第二面。第二面与附接了第一带110的第一面相反。优选地，第二带112从一侧条106延伸到另一侧条106。第一带110和第二带112由坚固并有弹性的耐高温材料制成。这样的带众所周知并在半导体工业中可容易地通过商业获得。
[20]参考图6，在引线框100的两个面附接到带之后，将引线框100装进模具120。也就是说，将引线框100在上模套122和下模套124的边沿之间夹紧，使得能将模塑料注入上模套122和下模套124之间的槽126内。根据本发明，将模塑料的第一流开始注入模具120，使得模塑料流进第一带110和上模套122之间的空间，如粗水平箭头所示。将模塑料的第二流也开始注入模具120。模塑料的第二流流进第一带和第二带之间的空间，即，流进侧条106和引线框100之间的空间以及引线102和管芯焊盘104之间的空间，如细箭头所示。
[21]图7示出了流进模腔126时的模塑料128。如图所示，在第一带110上的模塑料128的第一流压低引线102和管芯焊盘104之间的扩大空间上的第一带110上，使得形成增大的括脚(参看图9)。模塑料128的第二流流进第一带110和侧条106(图中的右侧条)之间的空间，使得模塑料流进引线102和管芯焊盘104之间的空间。在本发明的一实施例中，在开始注入第二模流之前，模塑料128的第一流已基本填满上模套122和第一带110之间的空间。模塑料128的第一流的速度大于模塑料的第二流的速度。
[22]在模塑料128填满模具120之后，将引线框100从模具中移走，如图8所示。如图所示，第一带110下降到引线102和管芯焊盘104之间的空间。图9示出了在通过解带处理而移走第一带110使得引线102和管芯焊盘104的表面暴露后的引线框100。在移走了第一带110的情况下，能够看到以130所示的增加的括脚。
[23]参考图10，在一实施例中，在从模具120中移走引线框100后，移走第二带112，而将第一带110留在引线框100上。注意，置于引线和管芯焊盘104之间的模塑料128留了下来。将半导体集成电路132附接到管芯焊盘104的暴露部分，然后执行引线接合工艺以将导线134附接在集成电路132上的焊盘和相应的引线102之间。集成电路132可以是诸如数字信号处理器(DSP)的处理器、微控制器、诸如存储地址发生器的专用功能电路或执行任何其它类型功能的电路。集成电路132不限于诸如CMOS的特定技术，或源自任何特定的晶片技术。此外，如将被本领域的技术人员所理解的，本发明能适应各种管芯大小。典型的示例是具有约6mm×6mm大小的闪存器件。
[24]然后，将组件放置在诸如模具120的模具中，并围绕集成电路132和导线134注入更多模塑料。在从模具120中移走后，沿着以虚线A-A、B-B和C-C表示的锯开通道执行单切或切割处理来形成独立封装的器件。在图10中，封状的器件包括四方扁平无引线型(QFN)器件。然而，上述形成预成型引线框的方法不限于QFN型引线框。
[25]根据上述讨论显而易见，本发明提供了增大引线括脚的预成型引线框。为了说明和描述，已经呈现了本发明优选实施例的描述，但不企图是详尽的或限制本发明到所描述的形式。本发明的技术人员将理解在不偏离其宽的发明原理的情况下能够对上述实施例做出改变。因此，可以理解，本发明不限于所公开的特定实施例，但涵盖在如所附权利要求限定的本发明的精神和范围内的修改。

Claims (9)

1.一种预成型引线框的方法，包括：
将第一带附接到引线框的第一面，该引线框包括引线和管芯焊盘；
将第二带附接到所述引线框的相反的第二面；
将所述引线框装入模具；
开始将模塑料的第一流注入所述模具，其中，该模塑料流进所述第一带和所述模具的上模套之间的空间；
开始将所述模塑料的第二流注入所述模具，其中，该模塑料流进所述第一带和所述第二带之间的空间；
将所述引线框从所述模具中移走；以及
将所述第一带和所述第二带从所述引线框移走，从而使得所述引线框的所述引线和管芯焊盘暴露，
其中，所述模塑料的所述第一流压低所述引线和所述管芯焊盘之间的所述第一带，使得在移走所述第一带时形成括脚。
2.如权利要求1所述的预成型引线框的方法，其中，所述模塑料的所述第一流的速度大于所述模塑料的所述第二流的速度。
3.如权利要求1所述的预成型引线框的方法，其中，在开始所述模塑料的第二流之前，所述模塑料的第一流基本上填满了所述上模套和所述第一带之间的所述空间。
4.如权利要求1所述的预成型引线框的方法，其中，所述引线框包括裸金属引线框。
5.如权利要求1所述的预成型引线框的方法，其中，所述引线框包括方形扁平无引线型引线框。
6.一种封装半导体集成电路的方法，该方法包括以下步骤：
将第一带附接到引线框的第一面，该引线框包括引线和管芯焊盘；
将第二带附接到所述引线框的相反的第二面；
将所述引线框装入模具；
开始将模塑料的第一流注入所述模具，其中，该模塑料流入所述第一带和所述模具的上模套之间的空间；
开始将所述模塑料的第二流注入所述模具，其中，该模塑料流入所述第一带和所述第二带之间的空间；
将所述引线框从所述模套中移走；
将所述第二带从所述引线框移走，从而使得所述引线框的所述引线和管芯焊盘暴露，并且其中，所述模塑料的所述第一流压低所述引线和所述管芯焊盘之间的所述第一带，使得在移走所述第一带时形成括脚；
将半导体集成电路附接到所述管芯焊盘上；
执行引线接合工艺，以将导线附接在所述集成电路上的焊盘和所述引线框的所述引线之间；
用模塑料对所述引线框、集成电路和导线进行封装；以及
将所述第一带从所述引线框移走，从而提供封装好的半导体集成电路。
7.如权利要求6所述的封装半导体集成电路的方法，其中，所述模塑料的所述第一流的速度大于所述模塑料的所述第二流的速度。
8.如权利要求6所述的封装半导体集成电路的方法，其中，在开始所述模塑料的第二流之前，所述模塑料的第一流基本上填满了所述上模套和所述第一带之间的所述空间。
9.如权利要求6所述的封装半导体集成电路的方法，其中，所述引线框包括方形扁平无引线型引线框。
CN2007101802438A 2007-10-16 2007-10-16 形成预成型引线框的方法 Expired - Fee Related CN101414565B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2007101802438A CN101414565B (zh) 2007-10-16 2007-10-16 形成预成型引线框的方法
US12/126,943 US7723163B2 (en) 2007-10-16 2008-05-26 Method of forming premolded lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2007101802438A CN101414565B (zh) 2007-10-16 2007-10-16 形成预成型引线框的方法

Publications (2)

Publication Number Publication Date
CN101414565A CN101414565A (zh) 2009-04-22
CN101414565B true CN101414565B (zh) 2012-07-04

Family

ID=40534635

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007101802438A Expired - Fee Related CN101414565B (zh) 2007-10-16 2007-10-16 形成预成型引线框的方法

Country Status (2)

Country Link
US (1) US7723163B2 (zh)
CN (1) CN101414565B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI378518B (en) * 2007-11-21 2012-12-01 Chipmos Technologies Inc Leadframe for leadless package and package structure thereof
CN101853790A (zh) * 2009-03-30 2010-10-06 飞思卡尔半导体公司 Col封装的新工艺流
CN102148168B (zh) * 2010-02-04 2015-04-22 飞思卡尔半导体公司 制造具有改进抬升的半导体封装的方法
US9034697B2 (en) * 2011-07-14 2015-05-19 Freescale Semiconductor, Inc. Apparatus and methods for quad flat no lead packaging
US11291146B2 (en) 2014-03-07 2022-03-29 Bridge Semiconductor Corp. Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1369911A (zh) * 2001-02-14 2002-09-18 松下电器产业株式会社 导线框、使用该导线框的半导体装置及其制造方法
US6696752B2 (en) * 2000-05-22 2004-02-24 Siliconware Precision Industries Co., Ltd. Encapsulated semiconductor device with flash-proof structure
US7173321B2 (en) * 2004-04-16 2007-02-06 Samsung Techwin Co. Ltd. Semiconductor package having multiple row of leads

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5098863A (en) 1990-11-29 1992-03-24 Intel Corporation Method of stabilizing lead dimensions on high pin count surface mount I.C. packages
US5640746A (en) 1995-08-15 1997-06-24 Motorola, Inc. Method of hermetically encapsulating a crystal oscillator using a thermoplastic shell
US5869883A (en) 1997-09-26 1999-02-09 Stanley Wang, President Pantronix Corp. Packaging of semiconductor circuit in pre-molded plastic package
US6097101A (en) 1998-01-30 2000-08-01 Shinko Electric Industries Co., Ltd. Package for semiconductor device having frame-like molded portion and producing method of the same
JPH11233712A (ja) 1998-02-12 1999-08-27 Hitachi Ltd 半導体装置及びその製法とそれを使った電気機器
US6924496B2 (en) 2002-05-31 2005-08-02 Fujitsu Limited Fingerprint sensor and interconnect
US7042071B2 (en) * 2002-10-24 2006-05-09 Matsushita Electric Industrial Co., Ltd. Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6858474B1 (en) 2003-12-01 2005-02-22 Agilent Technologies, Inc. Wire bond package and packaging method
US7221042B2 (en) 2004-11-24 2007-05-22 Agere Systems Inc Leadframe designs for integrated circuit plastic packages
KR101297645B1 (ko) 2005-06-30 2013-08-20 페어차일드 세미컨덕터 코포레이션 반도체 다이 패키지 및 그의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696752B2 (en) * 2000-05-22 2004-02-24 Siliconware Precision Industries Co., Ltd. Encapsulated semiconductor device with flash-proof structure
CN1369911A (zh) * 2001-02-14 2002-09-18 松下电器产业株式会社 导线框、使用该导线框的半导体装置及其制造方法
US7173321B2 (en) * 2004-04-16 2007-02-06 Samsung Techwin Co. Ltd. Semiconductor package having multiple row of leads

Also Published As

Publication number Publication date
US20090098686A1 (en) 2009-04-16
CN101414565A (zh) 2009-04-22
US7723163B2 (en) 2010-05-25

Similar Documents

Publication Publication Date Title
US6797541B2 (en) Leadless semiconductor product packaging apparatus having a window lid and method for packaging
US7781262B2 (en) Method for producing semiconductor device and semiconductor device
US7410834B2 (en) Method of manufacturing a semiconductor device
CN101847584A (zh) 基于引线框架的快闪存储器卡
CN102132402A (zh) 薄箔半导体封装
JP2004500718A5 (zh)
US7402459B2 (en) Quad flat no-lead (QFN) chip package assembly apparatus and method
EP1543556A2 (en) Taped lead frames and methods of making and using the same in semiconductor packaging
CN101414565B (zh) 形成预成型引线框的方法
US20050218499A1 (en) Method for manufacturing leadless semiconductor packages
KR101054540B1 (ko) 반도체 장치 및 그 제조 방법
US20180122731A1 (en) Plated ditch pre-mold lead frame, semiconductor package, and method of making same
CN102738024A (zh) 半导体封装及其引线框
US6979886B2 (en) Short-prevented lead frame and method for fabricating semiconductor package with the same
US9972561B2 (en) QFN package with grooved leads
US20020149090A1 (en) Lead frame and semiconductor package
CN101325190A (zh) 导线架上具有图案的四方扁平无引脚封装结构
KR20130120762A (ko) 반도체 패키지 및 그 제조방법
EP3840040A1 (en) A leadframe for semiconductor devices, corresponding semiconductor product and method
US6501158B1 (en) Structure and method for securing a molding compound to a leadframe paddle
EP4016617A1 (en) Method of manufacturing semiconductor devices, component for use therein and corresponding semiconductor device
CN109904081B (zh) 基于idf引线框架的半导体产品的封装方法
KR100253388B1 (ko) 반도체 패키지의 제조방법
CN104347570A (zh) 无引线型半导体封装及其组装方法
JP2000150761A (ja) 樹脂封止型半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120704

Termination date: 20211016

CF01 Termination of patent right due to non-payment of annual fee