CN101853790A - Col封装的新工艺流 - Google Patents
Col封装的新工艺流 Download PDFInfo
- Publication number
- CN101853790A CN101853790A CN200910130250A CN200910130250A CN101853790A CN 101853790 A CN101853790 A CN 101853790A CN 200910130250 A CN200910130250 A CN 200910130250A CN 200910130250 A CN200910130250 A CN 200910130250A CN 101853790 A CN101853790 A CN 101853790A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- epoxy resin
- plastic packaging
- tube core
- carried out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004033 plastic Substances 0.000 claims abstract description 38
- 239000003822 epoxy resin Substances 0.000 claims abstract description 35
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 35
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 238000007650 screen-printing Methods 0.000 claims abstract description 9
- 238000003466 welding Methods 0.000 claims abstract description 5
- 239000012528 membrane Substances 0.000 claims description 24
- 238000005538 encapsulation Methods 0.000 claims description 17
- 239000003292 glue Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 230000032798 delamination Effects 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract 1
- 239000000725 suspension Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 30
- 238000012536 packaging technology Methods 0.000 description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 239000002002 slurry Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003344 environmental pollutant Substances 0.000 description 2
- 231100000719 pollutant Toxicity 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007499 fusion processing Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002957 persistent organic pollutant Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83053—Bonding environment
- H01L2224/83095—Temperature settings
- H01L2224/83099—Ambient temperature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
- H01L2224/85013—Plasma cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
- H01L2924/35121—Peeling or delaminating
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明公开一种COL封装的新工艺流。其中,提供一种形成引线上芯片封装的方法,包括以下步骤:安装且锯切晶片,以提供多个单个的管芯;在引线框上进行第一次塑封操作;通过丝网印刷工艺在引线框上淀积环氧树脂;通过环氧树脂在引线框上贴装单个管芯之一,其中该管芯贴装是在室温下进行的;以及通过固化炉来固化所述环氧树脂。本发明成功解决了现有COL封装中的瓶颈工艺,即,本发明中不再存在热管芯贴装问题,由此提高了UPH。可选地,在丝线键合和第二次塑封之前进行等离子清洗步骤,从而改善了丝线键合球压焊性能。此外,由于在形成环氧树脂之前进行了第一次塑封,避免环氧树脂悬空的问题,从而避免了环氧树脂与管芯之间的分层风险。
Description
技术领域
本发明总体上涉及半导体封装工艺,更具体地,涉及引线框管脚上芯片(COL)封装的新工艺。
背景技术
中国发明专利申请公布说明书CN101312177A(申请号200710105030.9)中公开了一种半导体器件的引线框及一种封装半导体器件的方法。其中引线框包括至少一行接触端子、用于容纳集成电路管芯的管芯座、以及连接接触端子和管芯座的聚合隔离材料。将集成电路管芯安装到管芯座的上表面,然后电连接集成电路管芯的键合焊盘到各个相应的接触端子,以塑封胶密封管芯、电连接以及接触端子的至少上表面。在此,将其全文引入作为本申请公开的一部分。应该注意的一点是,该封装方法不是发生在封装工艺内部,而是发生在引线框生产供应商一方的工艺。本申请与CN101312177A的不同之处将在下文以及具体实施方式中详细描述。
引线框管脚上芯片封装或引线上芯片封装,简写为COL封装,是将管芯通过非传导性环氧树脂而直接安装到引线框的管脚或引线指(lead finger)上。随后将产品丝线键合并塑封到标准封装配置中。例如,可参看图1所示。
COL封装技术具有如下的优点:在现有封装中引入更大尺寸的管芯;无需晶片冲压工艺;具有可比性的热性能;以及具有符合标准的产品。
现有技术的COL封装流程如图2中所示。在步骤207,在晶片上进行环氧树脂丝网印刷。接着,在步骤209,进行B阶段环氧树脂固化。在步骤211,将晶片进行安装和锯切。引入引线框之后,在步骤201,对引线框进行上胶膜。针对安装并锯切后的晶片以及上胶膜之后的引线框,在步骤213,进行热管芯贴装。由于在B阶段环氧树脂固化步骤中对银浆进行了固化,在热管芯贴装步骤中要对其再次熔化,从而要进行伴随一定温度的热管芯贴装。接着,在步骤215,进行环氧炉固化。然后,在步骤219,进行丝线键合。在丝线键合之后,在步骤221,进行塑封。接着是在步骤223的标印(marking)工艺。然后是步骤205的去胶膜。再进行剩余的标准封装工艺,即封装工艺后道工序,如步骤225所示。
在现有的COL封装工艺中,如前面所提及的,由于在该工艺中,需要对B阶段环氧树脂银浆进行固化,所以需要在加热区域停留几秒钟的时间对银浆进行固化,因此,在管芯贴装方面,现有COL封装工艺具有较低的每小时产能(UPH)。
此外,在现有的COL封装工艺中,在完成环氧树脂固化之后再完成下方的塑封胶。也就是说,回过来参看图1,在完成灰色区域的环氧树脂之后,由于还未完成黑色倒T型区域的塑封胶,该环氧树脂在倒T型区域是悬空的,因此,在环氧树脂和管芯之间会存在潜在的分层(delamination)风险。
另外,管芯表面和引线框表面可能存在有机污染物,如果对其进行清洗,将对键合工艺有很大的改善。然而在现有工艺中,由于进行了上胶膜,如果进行清洗的话,胶膜表面的胶层也会发生反应,反而会引入新的污染源。
因此,需要一种新的COL封装工艺来解决现有技术中存在的上述缺陷。
发明内容
为解决上文中提到的各种缺陷,本发明提供一种COL封装的新工艺流。
根据本发明,提供一种形成引线上芯片封装的方法,包括如下步骤:安装且锯切晶片,以提供多个单个的管芯;在引线框上进行第一次塑封操作;通过丝网印刷工艺在引线框上淀积环氧树脂;通过环氧树脂在引线框上贴装单个管芯之一,其中该管芯贴装是在室温下进行的;以及通过固化炉来固化所述环氧树脂。
在本发明的方法中,进一步包括如下步骤:在第一次塑封操作之前对引线框上胶膜;以及在第一次塑封操作之后对引线框去胶膜。
在本发明的方法中,进一步包括如下步骤:将所述管芯通过丝线键合电连接到所述引线框;进行第二次塑封操作,以便用塑封胶覆盖所述引线框和所述管芯。
在本发明的方法中,进一步包括如下步骤:对管芯表面及引线框表面进行等离子清洗。
优选地,所述等离子清洗步骤是在所述丝线键合步骤之前进行的。
优选地,在本发明的方法中,进一步包括如下步骤:对管芯表面进行标印。
优选地,所述第一次塑封操作是在丝网印刷和管芯贴装步骤之前进行的;以及所述第二次塑封操作是在所述丝线键合步骤之后进行的。
优选地,所述的电连接的步骤包括将管芯的键合焊盘通过丝线键合连接到引线框的接触端子。
通过以上的技术方案,本发明成功解决了现有COL封装中的瓶颈工艺,即,本发明中不再存在热管芯贴装问题,由此提高了每小时的产能(UPH)。而且,可选地,在丝线键合和第二次塑封之前进行等离子清洗步骤,从而改善了丝线键合球压焊(ball bond)性能。此外,由于在形成环氧树脂之前进行了第一次塑封,避免环氧树脂悬空的问题,从而避免了环氧树脂与管芯之间的分层风险。
附图说明
图1图示说明了COL封装的结构。
图2是现有技术形成COL封装的流程图。
图3是根据本发明实施例的形成COL封装的流程图。
具体实施方式
下面结合附图的图示来详细地描述本发明的实施例,以使本领域普通技术人员能够理解本发明及其优势之所在。
图3是根据本发明实施例的形成引线框上芯片(COL)封装的流程图。
引入引线框之后,在步骤301,对引线框上胶膜(tape)。
然后,在步骤303,对引线框进行一次塑封(molding),为了与后一次塑封相区别,这里称之为第一次塑封操作,即在管芯贴装之前的塑封。
该第一次塑封操作是在丝网印刷(步骤307)之前进行的。参看图1,如在背景技术及发明内容中所提及的,对于现有技术来说,先完成灰色区域的环氧树脂,然后再完成下方的黑色倒T型区域的塑封胶(compound)。而在根据本发明的COL封装方法中,先完成了第一次塑封操作,就已经形成了下方黑色倒T型区域的塑封胶,然而再完成灰色区域的环氧树脂。也就是说,按照现有技术的流程,在完成环氧树脂后,在倒T型区域上方的环氧树脂是悬空的,这样很容易产生环氧树脂与管芯之间的分层风险;本发明则避免了这一风险。
在步骤305,对引线框去胶膜(de-tape)。
在现有工艺中,直到进行了标印之后,才进行去胶膜的工艺。由于贴在引线框背面的胶膜的可接受的最大温度不能超过170℃(供应商提供的使用条件),所以在对带有胶膜的引线框进行键合的时候,最高的温度不能超过170℃;然而,如果将胶膜去掉,引线框的键合温度将可以提高到200℃左右。从这个意义上来说,本发明的工艺相比现有工艺中针对具有胶膜的引线框进行键合,可以获得更高温度的键合。
另外,对带有胶膜的引线框进行键合的时候,由于塑封工艺对键合工艺的限制,使得键合工艺可使用的参数窗口过于狭窄,不然键合后在塑封工艺会产生大量的溢胶缺陷。有鉴于此,按照本发明的实施例,在键合工艺之前事先就把胶膜去除掉,从而回避了上述问题。这样,键合工艺的参数窗口得以扩展。
此外,如果带着胶膜进行加热,会在引线框的背面或多或少留有一些残留物,偶尔有时候会对可焊性(solderability)有非常严重的负面影响。本发明在加热之前去除胶膜,从而消除了可能存在的负面影响。
在步骤307,通过丝网印刷工艺在引线框上淀积环氧树脂。
以上都是对引线框的处理流程。下面来看引入晶片之后的操作。
在步骤311,安装且锯切晶片,以提供多个单个的管芯。
在步骤313,在室温下,通过环氧树脂在引线框上贴装单个管芯之一。
应该注意到,这里,管芯贴装是在室温下进行的,明显区别于现有技术中的热管芯贴装。在背景技术中已经提到,由于原有工艺中,需要对B阶段环氧树脂银浆进行固化,所以在热管芯贴装阶段就要对它进行再次熔化,这也就是现有技术中进行“热”管芯贴装时需要伴随一定温度的原因;而在本发明中,不需要这样的熔化过程,也就可以在室温下进行贴装了。具有热管芯贴装工艺的现有技术封装方法需要在加热区域停留几秒钟的时间对银浆进行固化;而在根据本发明的新工艺中,进行室温的管芯贴装,则不需要这段停留时间,由此UPH得以提高。
在进行了管芯贴装之后,在步骤315,通过固化炉来固化所述环氧树脂。
接着,在步骤319,将所述管芯通过丝线键合电连接到所述引线框。具体地说,是将管芯的键合焊盘通过丝线键合连接到引线框的接触端子。
可选地,在步骤319的丝线键合步骤之前可以加入一个等离子清洗的步骤,即步骤317。在步骤317中,对管芯表面及引线框表面进行等离子清洗。
在丝线键合步骤之前对管芯表面及引线框表面的有机污染物进行等离子清洗,对于键合工艺而言,就会有很大的改善。但是如果此时的引线框还没有去除胶膜,即带有胶膜的话(例如现有技术的COL封装),就会对胶膜也进行等离子清洗,胶膜表面的胶层也会发生反应。这样非但不能很好地对管芯表面和引线框表面的有机污染物进行等离子清洗,反而会引入新的污染源。
需要说明的是,在前述的步骤中,例如第一次塑封操作、上胶膜/去胶膜、环氧树脂丝网印刷、等离子清洗等步骤中,可以运用传统的工艺参数,也可运用更有效的工艺参数,本发明无意对这些步骤中的工艺参数做出具体的限制。
在丝线键合之后,在步骤321,进行第二次塑封操作,以便用塑封胶覆盖所述引线框和所述管芯。
在步骤323,对管芯表面进行标印,即,在完成第二次塑封操作后,对管芯表面用激光进行印字的工序。
之后就是封装工艺后道工序,即剩余的标准封装工艺,在图3中标记为步骤325。
尽管在以上的描述中已经说明了本发明的种种优势之处,下面仍将对这些优势进行一些小结:
1、避免了现有技术的瓶颈工艺(热管芯贴装工艺),极大地改善了UPH,大大缩减了循环周期时间。
2、在贴装键合之前就去除引线框上的胶膜,与带有胶膜的情况相比,获得了更高温度的键合以及更宽的键合工艺参数窗口。此外,也避免了胶膜加热后的残留物对可焊性的负面影响。
3、在丝线键合之前进行等离子清洗可以进一步改善键合性能。而对于还未去除胶膜的现有工艺来说,这一改善是绝对不可能得到的。
4、避免了环氧树脂与管芯之间的分层风险。
此外,需要注意的是,本发明与背景技术中所列的CN101312177A相比,采用了不同的封装;而且,CN101312177A的方法不是发生在封装工艺内部,而是发生在引线框生产供应商一方的工艺,而本发明的方法对于装配过程来说则是发生在封装工艺内部。
本领域技术人员应该明白,上述的具体实施例仅仅是对本发明给出了一个可以实施的方式,而并非想把本发明严格限制于这样的具体方式与步骤流程。对本发明的限定应该由权利要求书做出。此外,除非特别说明或明确指出,本发明的实施例的工艺流方法中的各个步骤并非缺一不可,其执行顺序也并非一定如具体实施例所描述的那样。此外,在说明书附图中,附图标记中步骤的标号并不表示这些步骤一定具有其标号从小到大的顺序。本领域技术人员应该理解,在本发明说明书的教导下,在不偏离本发明权利要求的范围的前提下,可以对这些步骤即技术特征,做出一定的增、删、改变或顺序调整。
Claims (8)
1.一种形成引线上芯片封装的方法,包括如下步骤:
安装且锯切晶片,以提供多个单个的管芯;
在引线框上进行第一次塑封操作;
通过丝网印刷工艺在引线框上淀积环氧树脂;
通过环氧树脂在引线框上贴装单个管芯之一,其中该管芯贴装是在室温下进行的;以及
通过固化炉来固化所述环氧树脂。
2.根据权利要求1所述的方法,进一步包括如下步骤:
在第一次塑封操作之前对引线框上胶膜;以及
在第一次塑封操作之后对引线框去胶膜。
3.根据权利要求1或2所述的方法,进一步包括如下步骤:
将所述管芯通过丝线键合电连接到所述引线框;
进行第二次塑封操作,以便用塑封胶覆盖所述引线框和所述管芯。
4.根据权利要求1或2或3所述的方法,进一步包括如下步骤:
对管芯表面及引线框表面进行等离子清洗。
5.根据权利要求4所述的方法,其中所述等离子清洗步骤是在所述丝线键合步骤之前进行的。
6.根据权利要求4所述的方法,进一步包括如下步骤:
对管芯表面进行标印。
7.根据权利要求3所述的方法,其中:
所述第一次塑封操作是在丝网印刷和管芯贴装步骤之前进行的;以及
所述第二次塑封操作是在所述丝线键合步骤之后进行的。
8.根据权利要求3所述的方法,其中所述的电连接的步骤包括将管芯的键合焊盘通过丝线键合连接到引线框的接触端子。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910130250A CN101853790A (zh) | 2009-03-30 | 2009-03-30 | Col封装的新工艺流 |
US12/727,258 US8642395B2 (en) | 2009-03-30 | 2010-03-19 | Method of making chip-on-lead package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200910130250A CN101853790A (zh) | 2009-03-30 | 2009-03-30 | Col封装的新工艺流 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101853790A true CN101853790A (zh) | 2010-10-06 |
Family
ID=42784770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910130250A Pending CN101853790A (zh) | 2009-03-30 | 2009-03-30 | Col封装的新工艺流 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8642395B2 (zh) |
CN (1) | CN101853790A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102779763A (zh) * | 2012-06-05 | 2012-11-14 | 华天科技(西安)有限公司 | 一种基于腐蚀的aaqfn产品的二次塑封制作工艺 |
CN103123903A (zh) * | 2012-10-25 | 2013-05-29 | 南通康比电子有限公司 | 一种整流桥堆dip刷胶工艺 |
CN103474362A (zh) * | 2013-08-27 | 2013-12-25 | 南通富士通微电子股份有限公司 | 多排qfn封装结构和制作方法 |
CN108538730A (zh) * | 2017-03-06 | 2018-09-14 | 中芯国际集成电路制造(上海)有限公司 | 封装方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120279651A1 (en) * | 2011-05-05 | 2012-11-08 | Wei Gu | Epoxy coating on substrate for die attach |
US8525321B2 (en) | 2011-07-06 | 2013-09-03 | Fairchild Semiconductor Corporation | Conductive chip disposed on lead semiconductor package |
US9679831B2 (en) | 2015-08-13 | 2017-06-13 | Cypress Semiconductor Corporation | Tape chip on lead using paste die attach material |
US10056317B1 (en) | 2017-10-20 | 2018-08-21 | Semiconductor Components Industries, Llc | Semiconductor package with grounding device and related methods |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0837252A (ja) * | 1994-07-22 | 1996-02-06 | Nec Corp | 半導体装置 |
KR100216064B1 (ko) | 1996-10-04 | 1999-08-16 | 윤종용 | 반도체 칩 패키지 |
US7061080B2 (en) * | 2001-06-11 | 2006-06-13 | Fairchild Korea Semiconductor Ltd. | Power module package having improved heat dissipating capability |
US7701042B2 (en) * | 2006-09-18 | 2010-04-20 | Stats Chippac Ltd. | Integrated circuit package system for chip on lead |
CN101312177A (zh) | 2007-05-22 | 2008-11-26 | 飞思卡尔半导体(中国)有限公司 | 用于半导体器件的引线框 |
CN101414565B (zh) * | 2007-10-16 | 2012-07-04 | 飞思卡尔半导体(中国)有限公司 | 形成预成型引线框的方法 |
US20090236710A1 (en) | 2008-03-19 | 2009-09-24 | Powertech Technology Inc. | Col semiconductor package |
US7619307B1 (en) | 2008-06-05 | 2009-11-17 | Powertech Technology Inc. | Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package |
US20100087024A1 (en) * | 2008-06-19 | 2010-04-08 | Noureddine Hawat | Device cavity organic package structures and methods of manufacturing same |
-
2009
- 2009-03-30 CN CN200910130250A patent/CN101853790A/zh active Pending
-
2010
- 2010-03-19 US US12/727,258 patent/US8642395B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102779763A (zh) * | 2012-06-05 | 2012-11-14 | 华天科技(西安)有限公司 | 一种基于腐蚀的aaqfn产品的二次塑封制作工艺 |
CN103123903A (zh) * | 2012-10-25 | 2013-05-29 | 南通康比电子有限公司 | 一种整流桥堆dip刷胶工艺 |
CN103123903B (zh) * | 2012-10-25 | 2015-08-26 | 南通康比电子有限公司 | 一种整流桥堆dip刷胶工艺 |
CN103474362A (zh) * | 2013-08-27 | 2013-12-25 | 南通富士通微电子股份有限公司 | 多排qfn封装结构和制作方法 |
CN108538730A (zh) * | 2017-03-06 | 2018-09-14 | 中芯国际集成电路制造(上海)有限公司 | 封装方法 |
CN108538730B (zh) * | 2017-03-06 | 2020-03-13 | 中芯国际集成电路制造(上海)有限公司 | 封装方法 |
Also Published As
Publication number | Publication date |
---|---|
US20100248426A1 (en) | 2010-09-30 |
US8642395B2 (en) | 2014-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101853790A (zh) | Col封装的新工艺流 | |
CN101562191B (zh) | 带腔体的光电封装件及其生产方法 | |
CN101346817A (zh) | 固体摄像元件模块的制造方法 | |
JPH0997888A (ja) | 光学装置およびその製造方法 | |
TW200603420A (en) | Resin sheet for sealing semiconductor and manufacturing method of semiconductor drvice using the same | |
US20080105941A1 (en) | Sensor-type semiconductor package and fabrication | |
WO2007080742A1 (ja) | 光素子の樹脂封止成形方法 | |
CN104900624A (zh) | 一种系统级mems双载体芯片封装件及其生产方法 | |
CN106159106B (zh) | 有机发光显示器及其制法 | |
CN103165794B (zh) | 光学半导体装置用基台、其制造方法以及光学半导体装置 | |
CN104515875A (zh) | 半导体试验夹具和其搬运夹具及使用这些夹具的异物去除方法 | |
CN112951972A (zh) | 一种cob模块修复方法 | |
KR100608185B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US20120196393A1 (en) | Packaging method of wafer level chips | |
CN117410397A (zh) | 芯片巨量转移方法及显示面板 | |
CN103119738A (zh) | 形成用于半导体发光器件的光学透镜的方法 | |
CN116722088A (zh) | COB模组及其封装方法、Mini LED显示装置 | |
CN215220716U (zh) | 多基岛芯片封装结构 | |
CN106057991B (zh) | 一种一体化led光源模组的制作方法 | |
US20090239341A1 (en) | Ic packaging process | |
JP5214356B2 (ja) | 半導体装置の製造方法 | |
CN101131944A (zh) | 半导体器件的制造方法 | |
US9041224B2 (en) | Method for producing a solder joint | |
JP2009152481A (ja) | 撮像用半導体装置および撮像用半導体装置の製造方法 | |
CN111261647A (zh) | 一种透光盖板、光学传感器及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20101006 |