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CN101373751B - 电子器件及电子设备 - Google Patents

电子器件及电子设备 Download PDF

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Publication number
CN101373751B
CN101373751B CN2008101310048A CN200810131004A CN101373751B CN 101373751 B CN101373751 B CN 101373751B CN 2008101310048 A CN2008101310048 A CN 2008101310048A CN 200810131004 A CN200810131004 A CN 200810131004A CN 101373751 B CN101373751 B CN 101373751B
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CN
China
Prior art keywords
electrical connection
resin protrusion
resin
wiring
connection portion
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Expired - Fee Related
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CN2008101310048A
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English (en)
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CN101373751A (zh
Inventor
田中秀一
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明提供一种即便发生温度变化也可以良好地保持导电接触状态并防止恶化的电子器件及电子设备。电子器件(100)具有：半导体装置(1)，其包括形成了电极的半导体芯片(10)、在半导体芯片(10)的形成了所述电极的面上形成为突条的树脂突起(20)、和包含在树脂突起(20)上排列的多个电连接部(32)并与所述电极电连接的布线；和布线基板(2)，其具有布线图案(44)；半导体装置(1)搭载于布线基板(2)上，通过使电连接部(32)与布线图案(44)相接触而电连接，与布线图案(44)相接触的多个电连接部(32)形成为包含向树脂突起(20)的长度方向突出的弯曲或折曲形状。

Description

电子器件及电子设备 
技术领域
本发明涉及在布线基板上装载了半导体装置的电子器件及使用了该电子器件的电子设备。 
背景技术
现有技术中，在各种电子设备上装载的电路基板或液晶显示装置等中，使用了安装半导体IC等电子部件的技术。例如，在液晶显示装置上安装作为驱动液晶面板用的作为半导体装置的液晶驱动用IC芯片。该IC芯片有时直接安装在构成液晶面板的玻璃基板上，此外，有时也安装在液晶面板上所安装的挠性基板(FPC)上。此外，该玻璃基板及挠性基板(FPC)是布线基板的一个示例。将基于前者的安装构造称作COG(ChipOn Glass)构造，将后者称作COF(Chip On FPC)构造。 
在COG构造的液晶显示装置中的液晶驱动用IC芯片的安装工序中，如图12(A)所示，隔着使导电性粒子1222a分散到热固化性树脂1222b中的各向异性导电膜(ACF：Anisotropic Conductive Film)1222，在玻璃基板1011上配置IC芯片1021。然后，通过对两者的加热·加压，使IC芯片1021的凸块(bump)电极1021B、1021B，经由上述导电性粒子1222a，处于在玻璃基板1011上的电极端子1011bx、1011dx的排列部分上导电接触的状态。然后，利用固化后的热固化性树脂1222b来保持该导电接触状态。 
通常，为了提高在凸块电极1021B与电极端子1011bx、1011dx之间的导电连接的可靠性，需要在使介于两者之间的导电性粒子1222a弹性变形的状态下，将IC芯片1021与玻璃基板1011的相对位置进行固定。这是因为，此时即使因温度变化而使热固化性树脂1222b发生热膨胀，也可维持通过导电性粒子1222a的导电接触状态。 
然而，对于细微的导电性粒子1222a，要想确保规定的弹性变形量是 极其困难的。 
因此，提出了如图12(B)所示的，在IC芯片1021的有源面上形成树脂突起1012，并在该树脂突起1012的表面上形成导电膜1020来构成凸块电极1010的发明(例如，参照专利文献1)。此外，预先在IC芯片1021的焊盘1024的表面上形成绝缘膜1026，并通过将该绝缘膜1026的一部分进行开口来形成焊盘1024的连接部1022。然后，对该连接部1022通过延长设置凸块电极1010的导电膜1020，可以使该凸块电极1010作为IC芯片1021的电极端子来发挥功能。 
若将该凸块电极1010按压在玻璃基板1011的端子上，则构成凸块电极1010的树脂突起1012发生弹性变形。此外，由于构成凸块电极1010的树脂突起1012与包含于ACF中的导电性粒子1222a相比足够大，所以能够确保规定的弹性变形量。在该状态下，若利用热固化性树脂1222b将IC芯片1021固定在玻璃基板1011上，则即便因温度变化而使热固化性树脂1222b发生热膨胀，也可维持通过凸块电极1010的导电接触状态。 
[专利文献1]特开平2-272737号公报 
但是，由于构成经由凸块电极1010的导电接触部的玻璃基板1011、树脂突起1012、导电膜1020、热固化性树脂1222b的热膨胀系数不同，所以被加热时的各自的变形量(热膨胀量)将产生参差。尤其，当树脂突起1012为突条，在树脂突起1012的表面上排列有多个导电膜1020时，在树脂突起1012的长度方向的端部附近基于热膨胀的变形量将变大。由于该树脂突起1012的变形量变大，构成部件的变形量的参差将变得更大，从而导电接触状态恶化、并有成为无法导电连接的危险。而且，此时存在无法将IC芯片1021与玻璃基板1011进行导电连接的问题。因此，需要能够耐温度变化的导电连接，成为了电子器件的技术课题。 
发明内容
本发明是用于解决上述课题的至少一部分的发明，可以作为以下的方式或应用例来实现。 
[应用例1]一种电子器件，具有：半导体装置，其包括：形成有电极的半导体芯片、在所述半导体芯片的形成了所述电极的面上形成为突条的树脂突起、和包括在所述树脂突起上排列的多个电连接部并与所述电极电连接的布线；和布线基板，其具有布线图案；所述半导体装置搭载于所述布线基板上，通过使所述电连接部与所述布线图案相接触而电连接，与所述布线图案相接触的多个所述电连接部形成为具有向所述树脂突起的长度方向的端部的方向突出的弯曲或折曲形状。 
根据该构成，与布线图案相接触的多个电连接部形成为具有向树脂突起的长度方向突出的弯曲或折曲形状。通过该弯曲或折曲形状，构成与布线图案相接触的多个电连接部的边的长度变长，因此，与不弯曲或折曲的直线形状相比，能增大导电接触面积。由此，即便构成电子器件的布线基板、树脂突起等的热膨胀存在偏差也可以良好地保持导电接触状态并防止恶化。因此，能提供耐温度变化而维持稳定的导电接触的电子器件。 
[应用例2]在上述电子器件中，与所述布线图案相接触的多个所述电连接部形成为：从该电连接部的在所述树脂突起的宽度方向上的端部到所述树脂突起的长度方向的假想中心线为止的最小尺寸，比从该电连接部的在所述树脂突起的宽度方向上的中央部到所述假想中心线为止的最小尺寸长。 
[应用例3]在上述电子器件中，与所述布线图案相接触的多个所述电连接部形成为：从该电连接部的在所述树脂突起的宽度方向上的端部到所述树脂突起的长度方向的假想中心线为止的最小尺寸，比从该电连接部的在所述树脂突起的宽度方向上的中央部到所述假想中心线为止的最小尺寸短。 
根据该构成，与布线图案相接触的多个电连接部形成为：从树脂突起的宽度方向的端部到树脂突起的长度方向的假想中心线为止的尺寸，比从树脂突起的宽度方向的中央部到假想中心线为止的尺寸长或短(不同的尺寸)。由此，与布线图案相接触的多个电连接部具有向树脂突起的长度方向突出的形状。通过该突出的形状，构成与布线图案相接触的多个电连接部的边的长度变长，因此，与不存在该突出的直线形状相比，能增大导电接触面积。由此，即便构成电子器件的布线基板、树脂突起等的热膨胀存在偏差也可以良好地保持导电接触状态并防止恶化。因此，能提供耐温度变化而维持稳定的导电接触的电子器件。 
[应用例4]在上述电子器件中，与所述布线图案相接触的多个所述电连接部形成为：从该电连接部的在所述树脂突起的宽度方向上的端部到所 述树脂突起的长度方向的假想中心线为止的最小尺寸、与从该电连接部的在所述树脂突起的宽度方向上的中央部到所述假想中心线为止的最小尺寸之差，在所述树脂突起的长度方向的两端部比在所述树脂突起的长度方向的中央部大。 
根据该构成，能使设置为突条的树脂突起的热膨胀所引起的变形最大的长度方向的端部附近处所对应的电连接部的接触面积增大。由此，即使发生温度变化，也能良好地保持由树脂突起的热膨胀引起的变形最大的长度方向的端部附近的电连接部与布线基板的导电接触状态。 
[应用例5]在上述电子器件中，与所述布线图案相接触的多个所述电连接部形成为：从该电连接部的在所述树脂突起的宽度方向上的端部到所述树脂突起的长度方向的假想中心线为止的最小尺寸、与从该电连接部的在所述树脂突起的宽度方向上的中央部到所述假想中心线为止的最小尺寸之差，从所述树脂突起的长度方向的中央部朝向所述树脂突起的长度方向的两端部逐渐增大。 
根据该构成，对应于设置为突条的树脂突起的热膨胀所引起的变形朝向长度方向的端部逐渐增大，使与布线图案相接触的多个电连接部的接触面积增大。由此，即使发生温度变化，也能良好地保持电连接部与布线基板的导电接触状态。 
[应用例6]一种电子设备，具有：上述的电子器件；和控制部，其具有至少使包括所述电子器件的构成部件动作的功能。 
根据该构成，即便因温度变化而构成电子器件的布线基板、树脂突起等的热膨胀存在偏差也可以良好地保持导电接触状态并防止恶化，因此，能提供维持更高可靠性的电子设备。 
附图说明
图1是用于对作为电子器件的液晶显示装置进行说明的概要立体图。 
图2是用于对半导体装置进行说明的图1的A-A剖视图。 
图3(A)～(C)是用于对半导体装置进行说明的概要图。 
图4(A)～(C)是用于对半导体装置的制造方法进行说明的概要图。 
图5(A)～(D)是用于对半导体装置的制造方法进行说明的概要图。 
图6(A)、(B)是用于说明形成布线的工序的一个示例的概要图。 
图7(A)～(D)是说明半导体装置与布线基板的安装工序的概要图。 
图8是图7(D)的P-P视图，且为被按压的电连接部的俯视图。 
图9(A)～(C)是电连接部的形状的应用例的示意图。 
图10是电子设备的一个示例的示意图。 
图11是电子设备的一个示例的示意图。 
图12(A)、(B)是说明作为现有的电子器件的液晶显示装置的剖视图。 
图中：1...半导体装置、2...布线基板、10...作为半导体芯片的液晶驱动用半导体芯片、11...半导体基板、12...电极、14...集成电路、15...面、16...钝化膜、20...树脂突起、20a...长度方向端部、22...上端面、25...树脂材料、30...布线、32...电连接部、32a、32b...宽度方向端部、40...金属层、42...底基板、44...布线图案、50...粘接剂、52...粘接材料、100...作为电子器件的液晶显示装置、110...作为布线基板的液晶面板、2000...作为电子设备的笔记本型个人计算机、3000...作为电子设备的手机。 
具体实施方式
以下，利用作为电子器件的一个示例的电光装置，并参照附图对应用了本发明的实施方式进行说明。 
图1是表示作为电光装置的一种实施方式的液晶显示装置的示意图。图示的液晶显示装置100具有液晶面板110、和包含有作为半导体芯片的液晶驱动用半导体芯片10(以下称为半导体芯片10)的半导体装置1。此外，根据需要，可适当地设置未图示的偏光板、反射片、背光灯等附加部件。 
[电光装置的构造] 
作为布线基板的液晶面板110，具备由玻璃或塑料等形成的底基板42及基板112。底基板42和基板112相互对置配置。通过未图示的密封件等相互粘合。在底基板42与基板112之间封入未图示的作为电光物质的液晶。在底基板42的内面上形成由ITO(Indium Tin Oxide)等透明导电 体构成的电极111a，在基板112的内面上形成与所述电极111a对置配置的电极112a。此外，将电极111a及电极112a以正交的方式配置。然后，将电极111a及电极112a引出到基板伸出部111T，在此端部分别形成电极端子111bx(布线图案44)及电极端子111cx(布线图案44)。此外，在基板伸出部111T的边缘附近形成输入布线111d，且在其内端部还形成端子111dx(布线图案44)。 
在基板伸出部111T上，经由利用未固化状态(A阶段状态)或半固化状态(B阶段状态)的热固化性树脂构成的粘接材料，安装半导体装置1。该半导体装置1例如包括半导体芯片10、后述的电连接部32、以及树脂突起20。在半导体芯片10的下面，形成多个电连接部32，并将这些电连接部32与基板伸出部111T上的端子111bx、111cx、111dx(布线图案44)分别进行导电连接。 
另外，在输入布线111d的外端部上形成的输入端子111dy上，经由各向异性的导电膜124安装挠性布线基板123。输入端子111dy与设置在挠性布线基板123上的分别对应的未图示的布线进行导电连接。然后，从外部经由挠性布线基板123向输入端子111dy供给控制信号、影像信号、电源电位等，并在半导体装置1上产生液晶驱动用的驱动信号，供给到液晶面板110。 
根据如上所述构成的该实施方式的液晶显示装置100，通过经由半导体装置1向电极111a与电极112a之间施加合适的电压，可以使将两电极111a、112a进行对置配置的像素部分的液晶进行再取向来调制光，由此，可以在液晶面板110内的排列了像素的显示区域上形成所希望的图像。 
图2是图1的A-A线的侧面剖视图，且为上述液晶显示装置100的半导体装置1的安装结构的说明图。在半导体芯片10的有源面(图示下面)上设置有：作为半导体侧端子形成为突条的树脂突起20、和在树脂突起20面上所形成的多个电连接部32。 
电连接部32的前端通过与底基板42的端子111bx、111dx压接而直接导电接触。在电连接部32与端子111bx、111dx之间的导电接触部分的周围，填充有将热固化性树脂等粘接材料固化后粘接的粘接剂50。 
[半导体装置1的结构]
以下，对该实施方式的半导体装置1的结构进行说明。此外，图3(A)～图3(C)是用于说明半导体装置1的图。 
半导体装置1如图3(A)～图3(C)所示，包括形成了电极12的半导体芯片10。半导体芯片10例如可以是硅芯片。半导体芯片10中的形成了电极12的面15的外形为矩形(长方形或正方形)。在半导体芯片10上形成有集成电路14。集成电路14的结构并无特别的限定，例如可包括晶体管等有源元件、或电阻、电感、电容等无源元件。 
在半导体芯片10中，如图3(A)及图3(C)所示，形成有电极12。电极12由铝(Al)或铜(Cu)等金属构成。电极12可以与半导体芯片10的内部电连接。电极12也可以与集成电路14电连接。此外，也可包括未与集成电路14电连接的导电体(导电焊盘)称为电极12。电极12也可为半导体芯片10的内部布线的一部分。此时，电极12也可为半导体芯片10内部布线之中用于与外部进行电连接的部分。此外，在电极12的表面也可形成TiN或Ni等帽层。 
半导体芯片10如图3(C)所示，可具有钝化膜16。钝化膜16以露出电极12的方式形成。在钝化膜16上可形成使电极12露出的开口。钝化膜16例如可以是SiO2或SiN等无机绝缘膜、或是聚酰亚胺树脂等有机绝缘膜。 
在该实施方式的半导体装置1中，如图3(A)～图3(C)所示，形成有树脂突起20。树脂突起20形成在半导体芯片10的面15上。树脂突起20如图3(C)所示，也可形成在钝化膜16上。 
树脂突起20的形状并无特别的限定。当面15的外形成为矩形时，树脂突起20也可形成为沿面15的任意一边平行延伸的形状。例如，在面15的外形为长方形时，树脂突起20可形成为沿长方形的长边延伸的形状(突条)(参照图3(A))。此时，树脂突起20可配置于该长边的附近区域。然后，在一个树脂突起20上配置有多个电连接部32。但是，树脂突起20在俯视图中也可形成为成圆形。此时，树脂突起20也可形成为半球状。此时，在一个树脂突起20上，也可仅配置一个电连接部32。 
树脂突起20的材料并无特别限定。可采用已为公知的任意一种材料。例如，树脂突起20可由聚酰亚胺树脂、硅酮改性聚酰亚胺树脂、环氧树 脂、硅酮改性环氧树脂、丙烯树脂、苯酚树脂，硅酮树脂、改性聚酰亚胺树脂、苯环丁烯(BCB：benzocyclobutene)、聚苯并噁唑(PBO：polybenzoxazole)等的树脂形成。 
在该实施方式的半导体装置1中，如图3(A)～图3(C)所示，形成有布线30。布线30与电极12电连接。布线30也可形成为与钝化膜16相接触。布线30也可形成为从电极12上越过树脂突起20到达钝化膜16上。即布线30也可形成为在树脂突起20的两侧与钝化膜16(面15)相接触。 
在布线30上，如图3(A)～3(C)所示，形成有电连接部32。电连接部32是布线30之中配置在树脂突起20上的区域。电连接部32也可是布线30之中配置在树脂突起20的上端面22上的区域(参照图3(C))。此外，所谓电连接部32是布线30之中使用于与其他的电子部件的导电部(布线基板的布线图案等)进行电连接的部分。即，所谓电连接部32可以是布线32之中，与后述的布线图案44对置(接触)的区域。此外，布线30虽以一层的布线层进行了说明，但也可以是多个布线层。 
可适用于布线30的材料并无特别限定。布线30例如可由Au、TiW、Cu、Ni、Pd、A1、Cr、Ti、W、NiV、Ag、无铅焊料等构成。 
[半导体装置1的制作方法] 
其次，对该实施方式的半导体装置1的制造方法进行说明。图4(A)～图4(C)是用于对该实施方式的半导体装置1的制造方法进行说明的图。 
半导体装置1的制造方法包括准备图4(A)～图4(C)所示的半导体基板11。此外，图4(A)是半导体基板11的概要图，图4(B)是半导体基板11的剖面的局部放大图。此外，图4(C)是半导体基板11的俯视图的局部放大图。半导体基板11如图4(A)所示，可为晶片状。但是，也可准备芯片状半导体基板(半导体芯片)来进行以下的工序。半导体基板11如图4(B)及图4(C)所示，具有电极12。半导体基板11还可以具有钝化膜16。 
半导体装置1的制造方法如图5(A)～图5(D)所示，包括形成树脂突起20。以下，对树脂突起20的形成次序进行说明。 
首先，如图5(A)所示，在半导体基板11上设置树脂材料25。此 后，如图5(B)所示，除去树脂材料25的一部分，对树脂材料25进行图案成形。然后，通过使图案成形后的树脂材料25固化(例如热固化)，如图5(C)及图5(D)所示，形成树脂突起20。此外，在该实施方式中，也可通过使树脂材料25熔融后固化来形成树脂突起20。此时，通过调节树脂材料25的熔融条件或固化条件，可对树脂突起20的形状(上面形状)进行控制。例如，通过将树脂材料25以仅熔融表面而不熔融中心的方式(半熔融状态为止)进行加热后使之固化，可形成上面为凸曲面的树脂突起20。通过调节树脂材料25的形状或材料、固化条件等，可对树脂突起20的形状进行控制。 
该实施方式的半导体装置1的制造方法，包括形成布线30。以下，对形成布线30的次序进行说明。此外，图6(A)及图6(B)是用于说明形成布线30的工序的一个示例的图。 
首先，如图6(A)及图6(B)所示，在半导体基板11上形成金属层40。金属层40可形成为覆盖电极12及钝化膜16。金属层40可形成为与电极12电连接。金属层40例如可利用溅射法形成。虽然金属层40的材料并无特别的限定，但将采用电阻值小延展性低的材料(脆性材料)、例如Au来形成。 
然后，通过将金属层40进行图案成形来形成布线30(参照图3(A)～图3(C))。 
然后，再经过切断半导体基板11的工序、或检查工序、或在树脂突起20上除去从布线30露出的区域的一部分的工序等，来形成半导体装置1(参照图3(A)～图3(C))。 
[电子器件的制造方法] 
接着，对作为电子器件的一个示例的液晶显示装置100的制造方法进行说明。图7(A)～图7(D)是用于说明该实施方式的液晶显示装置100的制造方法图。 
该实施方式的液晶显示装置100的制造方法，包括准备布线基板2。以下，对布线基板2的结构进行说明。 
布线基板2包括底基板42和布线图案44。该例的底基板42(布线基板2)由液晶面板110的一部分形成。此外，底基板42可以是其它的电 光面板，例如场致发光面板等的一部分。此时，底基板42，例如，也可以是陶瓷基板或玻璃基板。此外，对布线图案44的材料并无特别限定，例如，可以是ITO(Indium Tin Oxide)、Cr、Al等的金属膜、金属化合物膜、或是由这些材料形成的复合膜。此外，布线图案44也可以电连接于驱动液晶的电极(扫描电极、信号电极、对置电极等)上。但是，布线基板2也可以是树脂基板。 
该实施方式的液晶显示装置100的制造方法，包括准备半导体装置1。半导体装置1可以为已说明的任意一种结构；此外，半导体装置1也可由上述的方法形成。 
该实施方式的液晶显示装置100的制造方法，包括在布线基板2上安装半导体装置1的工序。以下，参照图7(A)～图7(D)对在布线基板2上安装半导体装置1的工序进行说明。 
首先，如图7(A)所示，在布线基板2上配置半导体装置1。在此，将半导体装置1以半导体芯片10的面15朝向布线基板2的方式进行配置。此外，按照使半导体装置1的电连接部32(树脂突起20)与布线基板2的布线图案44对置(重叠)的方式，进行半导体装置1与布线基板2的对位。例如，可利用未图示的夹具(配合工具)来保持半导体装置1，并进行半导体装置1与布线基板2的对位。此时，也可按照使面15与布线基板2平行的方式保持半导体装置1。此外，也可在夹具(配合工具)中内装加热器，并由此对半导体装置1进行加热。通过对半导体装置1进行加热，使电连接部32被加热，从而可以将电连接部32与布线图案44可靠地电连接。 
而且，在半导体装置1与布线基板2之间，如图7(A)所示，可预先设置好粘接材料52。粘接材料52也可以以膏状或模状进行设置。粘接材料52可以是不含导电粒子等的绝缘性材料(NCP、NCF)。粘接材料52例如可以设置在布线基板2上。 
此后，如图7(B)所示，使半导体装置1与布线基板2相接近，并使电连接部32与布线图案44相接近，然后使两者进行电连接。在该工序中，利用半导体芯片10和布线基板2(底基板42)将树脂突起20压扁，如图7(C)所示，使树脂突起20弹性变形。通过将该树脂突起20压扁， 使电连接部32也变形的同时可按压于布线图案44上。对于被按压于布线图案44上的电连接部32的形状将在后面进行详述。由此，因为利用树脂突起20的弹性，可将电连接部32与布线图案44按压在一起，所以能够制造出电连接可靠性高的液晶显示装置100。此外，在该工序中也可一边使粘接材料52流动、一边使半导体装置1与布线基板2接近。 
然后，如图7(D)所示，在半导体装置1与布线基板2之间形成粘接剂50。粘接剂50可通过使粘接材料52固化来形成。利用粘接剂50将半导体装置1与布线基板2粘接(固定)。也可利用粘接剂50来维持半导体芯片10与布线基板2的间隔。即可利用粘接剂50来维持树脂突起20进行弹性变形后的状态。例如，通过在树脂突起20进行弹性变形后的状态下形成粘接剂50，就可维持树脂突起20弹性变形后的状态。由此，能够制造出电连接部32与布线图案44的电连接可靠性高的液晶显示装置100。此外，粘接剂50的材料并无特别限定。粘接剂50例如可由树脂材料形成。而且，粘接材料52也可为热固化性的树脂材料。 
[布线图案44上按压的电连接部32的形状] 
如上所述，对于被按压于布线图案44上的电连接部32的形状依照图8进行详细说明。图8是图7(D)的P-P视图，且为被按压的电连接部的俯视图。 
如图8所示，沿设置为突条的树脂突起20的长度方向(X方向)，以被布线图案44按压的状态设置多个电连接部32。电连接部32与被按压而变形的树脂突起20一起变形，成为规定的形状并与布线图案44相接触。此外，图8表示变形后与布线图案44相接触的电连接部32的形状。电连接部32以树脂突起20的长度方向的假想中心线Q1(以下称为“中心线Q1”)作为标准，朝着相反方向(树脂突起20的长度方向的端部20a)，从电连接部32-1到电连接部32-X分别进行排列。各个电连接部32设置为向树脂突起20的长度方向的端部20a的方向进行弯曲。例如，在电连接部32-1中，从中心线Q1到树脂突起20的宽度方向(Y方向)中央部(中心线Q2的近边)(以下称为“宽度方向中央部”)为止的尺寸L2，比从中心线Q1到树脂突起20的宽度方向端部(以下称为“宽度方向端部”)32a、32b为止的尺寸L1大。此外，在电连接部32-X上，从中心线Q1 到宽度方向中央部为止的尺寸L4比从中心线Q1到宽度32a、32b为止的尺寸L3大。利用此弯曲形状，由于与直线的形状相比，可以使导电接触面积变大，所以各自的电连接部32可以维持更稳定的导电接触。 
另外，在该实施方式中，虽然对将弯曲方向朝着宽度方向端部32a、32b形成凸的示例进行了说明，但并不限于此，即便朝着宽度方向端部32a、32b形成为凹，也可以使接触面积变大而得到相同的效果。 
此外，如图9(A)～(C)所示，电连接部32的形状只要是接触面积变大即可，所以也可以不为上述的弯曲形状，而可以是折曲形状、或弯曲与折曲相组合的形状。 
进而，如图8所示，电连接部32形成为从中心线Q1朝向树脂突起20的长度方向的端部(以下称为“长度方向端部”)20a逐次弯曲量变大。即从中心线Q1到树脂突起20的宽度方向(Y方向)中央部与到端部32a、32b之间的尺寸的差逐次加大。即，电连接部32随着从中心线Q1朝向长度方向端部20a，从中心线Q1到宽度方向中央部为止的尺寸与从中心线Q1到宽度方向端部32a、32b为止的尺寸的差变大。若按图8进行说明，则在邻近中心线Q1的电连接部32-1中，从中心线Q1到宽度方向中央部为止的尺寸L2与从中心线Q1到宽度方向端部32a、32b为止的尺寸L1的差为尺寸差L5。相对于此，在邻近长度方向端部20a的电连接部32-X中，从中心线Q1到宽度方向中央部为止的尺寸L4与从中心线Q1到宽度方向端部32a、32b为止的尺寸L3的差为尺寸差L6。 
如上所述，尺寸差L6>尺寸差L5，随着从中心线Q1朝向长度方向端部20a该尺寸差变大。换言之，从中心线Q1朝向长度方向端部20a弯曲逐次变大。通过该弯曲的变大，电连接部32的接触面积从中心线Q1朝向长度方向端部20a逐次变大。在此，突条的树脂突起20由于是树脂，所以膨胀系数受环境稳定的变化的影响会很大，与底基板42等相比将会产生大的热膨胀。而且，长度方向的端部的膨胀量将为最大。相对于此，由于电连接部32的接触面积从中心线Q1朝向长度方向端部20a逐次变大，所以，即使树脂突起20的长度方向端部的膨胀量变大也可保持电接触。因此，能够提供能耐温度变化、并可维持稳定的导电接触的电光装置(液晶显示装置100)。
另外，如上所述，突条的树脂突起20的热膨胀量在长度方向端部20a为最大。因此，电连接部32的弯曲也不限于从中心线Q1朝向长度方向端部20a使弯曲量逐次变大，也可通过使中心线Q1附近的弯曲量比长度方向端部20a附近的弯曲量更大来产生同样的效果。 
此外，可提供一种电子设备，包括：所述电子器件、和控制部，其具有至少使包含该电子器件的结构部件进行动作的功能。在图10中，表示了作为电子设备的一个示例的笔记本型个人计算机2000；而在图11中，表示了作为电子设备的一个示例的手机3000。在笔记本型个人计算机2000或手机3000中，具备有作为电子器件的一个示例的液晶显示装置。此时控制部(未图示)可以是CPU等。 
根据如此的结构，即便因温度变化而产生构成电子器件的布线基板、树脂突起等的热膨胀的差异，也可以良好地保持导电接触状态、并防止恶化，从而能够提供可以维持更稳定的导电接触的电子设备。

Claims (6)

1.一种电子器件，具有：
半导体装置，其包括：形成有电极的半导体芯片、在所述半导体芯片的形成了所述电极的面上形成为突条的树脂突起、和包括在所述树脂突起上排列的多个电连接部并与所述电极电连接的布线；和
布线基板，其具有布线图案；
所述半导体装置搭载于所述布线基板上，通过使所述电连接部与所述布线图案相接触而电连接，
与所述布线图案相接触的多个所述电连接部形成为具有向所述树脂突起的长度方向的端部的方向突出的弯曲或折曲形状。
2.根据权利要求1所述的电子器件，其特征在于，
与所述布线图案相接触的多个所述电连接部形成为：从该电连接部的在所述树脂突起的宽度方向上的端部到所述树脂突起的长度方向的假想中心线为止的最小尺寸，比从该电连接部的在所述树脂突起的宽度方向上的中央部到所述假想中心线为止的最小尺寸长。
3.根据权利要求1所述的电子器件，其特征在于，
与所述布线图案相接触的多个所述电连接部形成为：从该电连接部的在所述树脂突起的宽度方向上的端部到所述树脂突起的长度方向的假想中心线为止的最小尺寸，比从该电连接部的在所述树脂突起的宽度方向上的中央部到所述假想中心线为止的最小尺寸短。
4.根据权利要求3所述的电子器件，其特征在于，
与所述布线图案相接触的多个所述电连接部形成为：从该电连接部的在所述树脂突起的宽度方向上的端部到所述树脂突起的长度方向的假想中心线为止的最小尺寸、与从该电连接部的在所述树脂突起的宽度方向上的中央部到所述假想中心线为止的最小尺寸之差，在所述树脂突起的长度方向的两端部比在所述树脂突起的长度方向的中央部大。
5.根据权利要求4所述的电子器件，其特征在于，
与所述布线图案相接触的多个所述电连接部形成为：从该电连接部的在所述树脂突起的宽度方向上的端部到所述树脂突起的长度方向的假想中心线为止的最小尺寸、与从该电连接部的在所述树脂突起的宽度方向上的中央部到所述假想中心线为止的最小尺寸之差，从所述树脂突起的长度方向的中央部朝向所述树脂突起的长度方向的两端部逐渐增大。
6.一种电子设备，具有：
权利要求1～5中任一项所述的电子器件；和
控制部，其具有至少使包括所述电子器件的构成部件动作的功能。
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JP4572376B2 (ja) * 2007-07-30 2010-11-04 セイコーエプソン株式会社 半導体装置の製造方法および電子デバイスの製造方法
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TWI381464B (zh) * 2008-08-29 2013-01-01 Hannstar Display Corp The bump structure and its making method
JP2011061035A (ja) * 2009-09-10 2011-03-24 Renesas Electronics Corp 半導体装置の製造方法及びマスク
CN105261602A (zh) * 2015-09-16 2016-01-20 京东方科技集团股份有限公司 一种显示面板的封装结构、转接板、封装方法及显示装置
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JP2005318015A (ja) 2004-04-26 2005-11-10 Matsushita Electric Ind Co Ltd Ｄｓｒｃ車載器及び変調方式識別方法
JP2006041413A (ja) * 2004-07-30 2006-02-09 Seiko Instruments Inc 半導体装置
JP4281656B2 (ja) * 2004-09-22 2009-06-17 セイコーエプソン株式会社 電子部品の実装構造、電子部品の実装方法、電気光学装置および電子機器
US7169920B2 (en) * 2005-04-22 2007-01-30 Xerox Corporation Photoreceptors
JP4284544B2 (ja) * 2005-06-29 2009-06-24 セイコーエプソン株式会社 半導体装置及びその製造方法
JP4487875B2 (ja) * 2005-07-20 2010-06-23 セイコーエプソン株式会社 電子基板の製造方法及び電気光学装置の製造方法並びに電子機器の製造方法
JP4273347B2 (ja) * 2005-08-03 2009-06-03 セイコーエプソン株式会社 半導体装置
JP4235835B2 (ja) * 2005-08-08 2009-03-11 セイコーエプソン株式会社 半導体装置
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