CN101369606A - Thin film transistor panel having structure for suppressing characteristic shift and manufacturing method thereof - Google Patents

Abstract

A thin-film transistor panel includes a substrate (1), and a thin-film transistor (3) formed on the substrate (1). The transistor includes a gate electrode (6), a gate insulating film (7), a semiconductor thin film (8), first and second ohmic contact layers (10, 11) formed on the semiconductor thin film (8), and source and drain electrodes (12, 13) which are respectively formed on the first and second ohmic contact layers (10, 11). The semiconductor thin film includes a channel area between the source electrode (12) and the drain electrode (13). A pixel electrode (2) is connected to the source electrode (12) of the thin-film transistor (3). First and second conductive coating films (14, 15) are provided on the source (12) and drain electrodes (13), respectively, and formed of the same material as the pixel electrode (2). The first conductive coating film (14) is wider than the source electrode (12), and the second conductive coating film (15) is wider than the drain electrode (13).

Description

Thin film transistor panel having structure for suppressing characteristic shift and manufacturing method thereof

The present invention is a divisional application with the application number "2006101718698" submitted by the applicant to the Chinese Patent Office on October 20, 2006, and the title of the invention is "a thin film transistor panel with a structure for suppressing characteristic shift and its manufacturing method".

technical field

The present invention relates to a thin film transistor panel having a structure for suppressing characteristic shift and a manufacturing method thereof.

Background technique

For an active matrix liquid crystal display device, a thin film transistor panel including a plurality of pixel electrodes and a plurality of switching thin film transistors connected to each pixel electrode is used. The opposite electrode panel having the color filter and the opposite electrode is arranged to sandwich the liquid crystal element between the thin film transistor panel, and by applying By displaying the voltage, the transmittance of the liquid crystal element changes and can be visually displayed. Japanese Patent Laid-Open No. 2005-93460 describes a structure in which thin film transistors are formed on the above-mentioned thin film transistor panel. The thin film transistor described in this prior art document is a transistor in which a gate electrode is provided on the upper surface of a substrate, a gate insulating film is provided on the upper surface of the substrate including the gate electrode, and a gate insulating film is provided on the gate electrode. A semiconductor film made of intrinsic amorphous silicon is provided on the upper surface of the semiconductor film, and a channel protective film made of silicon nitride is provided at a predetermined position on the upper surface of the semiconductor film. On both sides of the upper surface of the channel protective film and both sides The upper surface of the semiconductor thin film is provided with an ohmic contact layer made of n-type amorphous silicon, and a source electrode and a drain electrode are formed on the upper surface of each ohmic contact layer, and an overcoat film made of silicon nitride is arranged on it. .

In the conventional thin film transistor described above, the width of the source electrode and the drain electrode is larger than the width of each ohmic contact layer in the region provided directly on the semiconductor thin film. In addition, since each ohmic contact layer in the region directly provided on the semiconductor thin film is completely covered by the source electrode and the drain electrode, even if an overcoat film made of silicon nitride is formed thereon by the plasma CVD method, The surface of each ohmic contact layer in the region provided directly on the semiconductor thin film is also not damaged by plasma, and the shift of Vg (gate voltage)-Id (gate current) characteristics to the negative side can be suppressed.

However, in the above-mentioned conventional thin film transistor, since the width of the source electrode and the drain electrode is made larger than the width of each ohmic contact layer in the region directly provided on the semiconductor thin film, photolithography for forming the source electrode and the drain electrode Since the process is different from the photolithography process for forming the ohmic contact layer, there is a problem that the number of photolithography steps increases.

Contents of the invention

Therefore, the object of the present invention is to provide a thin film transistor panel that can suppress the shift of Vg-Id characteristics to the negative side without increasing the number of photolithography steps.

To achieve the above object, the thin film transistor panel of the present invention includes: a substrate; a thin film transistor formed on the substrate and having a gate electrode, a gate insulating film, a semiconductor thin film, and a pair of ohmic contacts formed on the semiconductor thin film layer, and a source electrode and a drain electrode formed on each of the ohmic contact layers, the semiconductor thin film has a channel region between the source electrode and the drain electrode; a pixel electrode, and all of the thin film transistors The source electrode is connected; and first and second conductive coating films are provided on the source electrode side and the upper part of the drain electrode side, and are formed of the same material as the pixel electrode; the first conductive The width of the covering film is wider than the width of the source electrode, and the width of the second conductive covering film is wider than the width of the drain electrode.

In addition, the method for manufacturing a thin film transistor panel of the present invention is characterized in that it includes the steps of: forming a thin film transistor on a substrate, the thin film transistor having a semiconductor thin film on a gate electrode via a gate insulating film; A pair of ohmic contact layers is provided, and a source electrode and a drain electrode are provided on each of the ohmic contact layers; a film for forming a pixel electrode is formed on the thin film transistor, and the film for forming the pixel electrode is etched. , forming a pixel electrode and a conductive coating film connected to the source electrode of the thin film transistor, and the conductive coating film is made to have an upper width of at least one of the source electrode side and the drain electrode side The source electrode or the drain electrode is wider than the width of the source electrode or the drain electrode and completely covers the outer region of the channel region.

Invention effect

According to the present invention, the source electrode or the drain electrode in the outer region of the channel region is completely covered with the conductive coating film having a width wider than that of the source electrode or the drain electrode, so that the Vg-Id characteristic can be suppressed from shifting to the negative side. offset, and by forming the conductive coating film from the same material as the pixel electrode, the number of photolithography steps can not be increased.

Description of drawings

FIG. 1 is a perspective plan view of main parts of a thin film transistor panel as a first embodiment of the present invention.

2(A) is a sectional view along II _A -II _A of FIG. 1, and 2(B) is a sectional view along II _B -II _B of FIG. 1.

3 is a schematic diagram for explaining an initial step as an example of a method of manufacturing a thin film crystal panel according to the first embodiment, wherein (A) is a perspective plan view same as that of _FIG . Sectional view of _B.

4(A) is a perspective plan view continuing the process of FIG. 3, and FIG. 4(B) is a sectional view along IV _B -IV _B thereof.

5(A) is a perspective plan view continuing the process of FIG. 4, and FIG. 5(B) is a cross-sectional view along V _B -V _B thereof.

6(A) is a perspective plan view continuing the process of FIG. 5, and FIG. 6(B) is a sectional view along VI _B -VI _B thereof.

7(A) is a perspective plan view continuing the process of FIG. 6, and FIG. 7(B) is a sectional view along VII _B -VII _B thereof.

8(A) is a perspective plan view continuing the process of FIG. 7, and FIG. 8(B) is a sectional view along VIII _B -VIII _B thereof.

9 is a perspective plan view of a main part of a thin film transistor panel as a second embodiment of the present invention.

FIG. 10(A) is a cross-sectional view along X _A -X _A of FIG. 9 , and FIG. 10(B) is a cross-sectional view along X _B -X _B of FIG. 9 .

11 is a perspective plan view of a main part of a thin film transistor panel as a third embodiment of the present invention.

Fig. 12(A) is a sectional view along XII _A - XII _A of Fig. 11, and Fig. 12(B) is a sectional view along XII _B - XII _B of Fig. 11 .

13 is a perspective plan view of main parts of a thin film transistor panel as a fourth embodiment of the present invention.

14(A) is a cross-sectional view along XIV _A -XIV _A of FIG. 13 , and FIG. 14(B) is a cross-sectional view along XIV _B -XIV _B of FIG. 13 .

15 is a perspective plan view of main parts of a thin film transistor panel as a fifth embodiment of the present invention.

16(A) is a sectional view taken along line XVI _A - XVI _A of FIG. 15 , and FIG. 16(B) is a sectional view taken along line XVI _B - XVI _B of FIG. 15 .

17 is a perspective plan view of main parts of a thin film transistor panel as a sixth embodiment of the present invention.

FIG. 18(A) is a sectional view taken along line XVIII _A - XVIII _A of FIG. 17 , and FIG. 18(B) is a sectional view taken along line XVIII _B - XVIII _B of FIG. 17 .

Symbol Description

1 glass substrate

2 pixel electrodes

3 thin film transistor

4 scan lines

5 data lines

6 Gate electrode

7 Gate insulating film

8 Semiconductor film

9 Channel protection film

10, 11 ohm contact layer

12 source electrode

13 drain electrode

14, 15 Conductive coating film

16, 17 ohm contact area

18 Overcoating

Detailed ways

(first embodiment)

1 shows a perspective plan view of the main part of the thin film transistor panel as the first embodiment of the present invention, FIG. 2(A) shows a sectional view along the line II _A -II _A of FIG. 1 , and FIG. The sectional view of II _B -II _B in Fig. 1 . In order to make the drawing clearer, the overcoat film 18 (described later) shown in FIGS. 2A and 2B is omitted in FIG. 1 . Dotted lines used in the drawings indicate the boundaries of elements. Such a thin film transistor panel includes a glass substrate 1 . A plurality of pixel electrodes 2 arranged in a matrix, thin film transistors 3 connected to these pixel electrodes 2 are arranged on the upper surface of the glass substrate 1; scanning lines arranged in the row direction to supply scanning signals (gate voltage) to each thin film transistor 3 4. A data line 5 for supplying a data signal to each thin film transistor 3 is arranged in the column direction.

That is, a gate electrode 6 made of chromium, aluminum-based metal, etc., and a scanning line 4 connected to the gate electrode 6 are provided at predetermined positions on the upper surface of the glass substrate 1 . A gate insulating film 7 made of silicon nitride is provided on the upper surface of the glass substrate 1 including the gate electrode 6 and the scanning line 4 . A semiconductor thin film 8 made of intrinsic amorphous silicon is provided at a predetermined portion of the upper surface of the gate insulating film 7 on the gate electrode 6 .

A channel protective film 9 made of silicon nitride is provided at a predetermined position on the upper surface of the semiconductor thin film 8 . In this case, channel protective film 9 is somewhat smaller in size than gate electrode 6 , and is provided on the upper surface of semiconductor thin film 8 at the center of gate electrode 6 . On the upper surface of the channel protection film 9, a pair of ohmic contact layers made of n-type amorphous silicon are provided on both sides of the channel length L direction (see FIG. 1) and on the upper surfaces of the semiconductor thin film 8 on both sides. 10, 11. A source electrode 12 and a drain electrode 13 made of chromium, aluminum-based metal, or the like are provided on the upper surfaces of the respective ohmic contact layers 10 and 11 .

In this case, the peripheral end surfaces of the ohmic contact layers 10 and 11 are flush with the peripheral end surfaces of the source electrode 12 and the drain electrode 13 . That is, each ohmic contact layer 10 , 11 is provided only under the source electrode 12 and the drain electrode 13 . The peripheral end surfaces of the semiconductor thin film 8 and the peripheral end surfaces of the pair of ohmic contact layers 10 and 11 are flush with each other. That is, the semiconductor thin film 8 is provided only under the channel protective film 9 and the pair of ohmic contact layers 10 , 11 . In addition, the pair of ohmic contact layers 10 , 11 , and the opposite end sides of the source electrode 12 and the drain electrode 13 extend over the channel protection film 9 .

Data lines 5 are provided at predetermined positions on the upper surface of gate insulating film 7 . The data line 5 has a three-layer structure consisting of an intrinsic amorphous silicon layer 5a, an n-type amorphous silicon layer 5b, and a metal layer 5c composed of chromium and aluminum-based metals in order from the bottom. Also, intrinsic amorphous silicon layer 5a, n-type amorphous silicon layer 5b, and metal layer 5c are connected to semiconductor thin film 8, ohmic contact layer 11, and drain electrode 13 in the region where drain electrode 13 is formed.

On the upper surface of the source electrode 12 on the side of the channel protective film 9 and on the upper surfaces of the channel protective film 9 and the gate insulating film 7 on both sides in the direction of the channel width W (see FIG. 1 ), there are layers made of ITO, etc. A conductive coating film 14. On the drain electrode 13 and the upper surface of the metal layer 5c of the data line 5 near the drain electrode 13, and the upper surfaces of the channel protection film 9 and the gate insulating film 7 on both sides in the direction of the channel width W, a layer made of ITO or the like is provided. Another conductive coating film 15 . In this case, the width in the channel width W direction of each of the conductive coating films 14 and 15 is wider than the width in the same direction of the source electrode 12 and the drain electrode 13 . In addition, the respective tips of the source electrode 12 and the drain electrode 13 extending on the channel protective film 9 are not covered by the respective conductive coating films 14 and 15 . In addition, another conductive coating film 15 is extended so as to span from the drain electrode 13 to a part of the data line (drain wiring) 5 connected to the drain electrode 13 .

Here, on the gate electrode 6 outside the channel protective film 9, the overlapped portion of the semiconductor thin film 8 and the ohmic contact layers 10, 11 is an area outside the channel region, and the ohmic contact regions 16, 17 are formed. And, as shown in FIG. 2B, both end surfaces of the semiconductor thin film 8, one ohmic contact layer 10, and the source electrode 12 in the direction of the channel width W in one ohmic contact region 16 are provided by a conductive electrode provided in contact with the two end surfaces. The covering film 14 is completely covered. In addition, although not shown in the figure, the semiconductor thin film 8 in the other ohmic contact region 17, the other ohmic contact layer 11, and the both end faces of the channel width W direction of the drain electrode 13 are shown in FIG. 2B. The other conductive film 15 that is placed in contact with both ends is completely covered.

However, from the gate electrode 6, the gate insulating film 7, the semiconductor thin film 8, the channel protection film 9, the pair of ohmic contact layers 10 and 11, the source electrode 12, the drain electrode 13, and the pair of conductive coating films 14 and 15, A thin film transistor 3 with a channel protection film type bottom gate structure is formed.

The pixel electrode 2 made of ITO or the like is provided on the upper surface of the source electrode 12 opposite to the side of the channel protective film 9 and at predetermined positions on the upper surface of the gate insulating film 7 . In this case, one conductive coating film 14 is integrally formed continuously with the pixel electrode 2 . An overcoat film 18 made of silicon nitride is provided on the upper surface of the gate insulating film 7 including the pixel electrode 2 and the thin film transistor 3 .

Here, in the thin film transistor 3 in this thin film transistor panel, in FIG. 1, an ohmic contact layer 10 and a source electrode 12 are provided on the right side of the gate electrode 6, that is, on the right side in the direction parallel to the scanning line 4. On the opposite left side, a further ohmic contact layer 11 and a drain electrode 13 are provided. In this case, the channel length L of the semiconductor thin film 8 is the length in the left-right direction of the channel protective film 9 , and the channel width W is the length in the vertical direction of the ohmic contact layers 10 and 11 . The facing end surfaces of the respective conductive coating films 14 and 15 extend to the inside of the channel region, that is, to the inside of the channel protection film 9 . However, the opposing end surfaces of the conductive coating films 14 and 15 do not reach the end surfaces of the source electrode 12 or the drain electrode 13 . In this case, the opposite end surfaces of the conductive coating films 14 and 15 may extend to the same plane as the end surfaces of the source electrode 14 or the drain electrode 13 or extend further to the channel protection film 9 than these. center of. However, since the conductive coating films 14 and 15 must be electrically insulated, if they extend to the same plane as the end faces of the source electrode 12 or the drain electrode 13 or extend further to the center of the channel protective film 9 than they do, due to misalignment , there is a high possibility of a short circuit between the two, so in order to obtain a fine display pixel, as shown in the figure, it is desirable to design in advance the opposite end faces of each conductive coating film 14, 15 so as not to reach the source electrode 12 or end face of the drain electrode 13 .

Therefore, in the thin film transistor 3 in such a thin film transistor panel, the semiconductor thin film 8 in each ohmic contact region 16, 17 and the both end surfaces of the channel width W direction of each ohmic contact layer 10, 11 are different from the source electrode 12. The respective conductive coating films 14 and 15 that are wider than the drain electrode 13 in the channel width W direction are completely covered. In addition, since the respective conductive coating films 14 and 15 are connected to the source electrode 12 and the drain electrode 13, the source electrode 12 and the drain electrode 13 have the same potential.

As a result, each conductive coating film 14, 15 and the gate electrode at the same potential as the source electrode 12 and drain electrode 13 are applied to the semiconductor thin film 8 and each ohmic contact layer 10, 11 in each ohmic contact region 16, 17. 6, formed between the longitudinal electric field perpendicular to the glass substrate 1, thereby confirming that the shift of the Vg-Id characteristic to the negative side can be suppressed. Furthermore, the absolute values of the gate-on voltage and the gate-off voltage applied to the gate electrode 6 are desirably the same.

Next, an example of a method of manufacturing such a thin film transistor panel will be described. First, as shown in FIGS. 3(A) and 3(B), at a predetermined position on the upper surface of the glass substrate 1, a metal film made of chromium or the like formed by sputtering is patterned by photolithography to form Gate electrode 6 and scan line 4. Then, on the upper surface of the glass substrate 1 including the gate electrode 6 and the scanning line 4, a gate insulating film 7 made of silicon nitride, an intrinsic amorphous silicon film 21 and a silicon nitride film 22 are successively formed by CVD. .

Then, in the channel protective film formation region on the upper surface of the silicon nitride film 22, the applied resist film is patterned by photolithography, whereby a resist film 23 is formed. Thereafter, the silicon nitride film 22 is etched using the resist film 23 as a mask, and the channel protection film 9 is formed under the resist film 23 as shown in FIGS. 4(A) and 4(B). Next, the resist film 23 is peeled off.

Next, as shown in FIGS. 5(B) and 5(A), on the upper surface of the intrinsic amorphous silicon film 21 including the channel protective film 9, an n-type amorphous silicon film 24 is formed by CVD, Then, the metal film 25 made of chromium or the like is formed by sputtering. Then, at predetermined positions on the upper surface of the metal film 25, the applied resist film is patterned by photolithography to form resist films 26a, 26b. In this case, the resist film 26 a is used to form the source electrode 12 , and the resist film 26 b is used to form the drain electrode 13 and the data line 5 .

Next, using the resist films 26a, 26b (including the channel protection film 9) as a mask, the metal film 25, the n-type amorphous silicon film 24 and the intrinsic amorphous silicon film 21 are sequentially etched, as shown in FIG. 6 (A) and 6(B). That is, the source electrode 12 and the ohmic contact layer 10 are formed under the resist film 26a, the drain electrode 13 and the ohmic contact layer 11 are formed under the resist film 26b, and the two ohmic contact layers 10, 11 and the channel protection A semiconductor thin film 8 is formed under the film 9 . Further, a data line 5 having a three-layer structure composed of a metal film 5c, an n-type amorphous silicon film 5b, and an intrinsic amorphous silicon film 5a is formed under the resist film 26b. Then, the resist films 26a, 26b are peeled off.

In this case, since the metal film 25, the n-type amorphous silicon film 24, and the intrinsic amorphous silicon film 21 are sequentially etched using the resist films 26a, 26b (including the channel protection film 9) as a mask, the formation of The source electrode 12, the drain electrode 13, the pair of ohmic contact layers 10, 11, and the semiconductor thin film 8, therefore, are different from the source electrode 12 and the drain electrode formed by the photolithography process different from the pair of ohmic contact layers 10, 11 and the semiconductor thin film 8. 13, the number of photolithography steps can be reduced.

Furthermore, after the source electrode 12 and the drain electrode 13 are formed, the resist films 26a, 26b can be peeled off, and then the source electrode 12 and the drain electrode 13 (including the channel protection film 9) can be used as a mask to sequentially etch The n-type amorphous silicon film 24 and the intrinsic amorphous silicon film 21 form a pair of ohmic contact layers 10 and 11 and a semiconductor thin film 8 .

Then, as shown in FIGS. 7(A) and 7(B), on the upper surface of the gate insulating film 7 including the source electrode 12, the drain electrode 13 and the data line 5, a pixel electrode made of ITO is formed by sputtering. The film 27 is formed. Then, the applied resist film is patterned by photolithography at predetermined positions on the upper surface of the pixel electrode forming film 27 to form resist films 28a and 28b. In this case, the resist film 28 a is used to form the pixel electrode 2 and one conductive coating film 14 , and the resist film 28 b is used to form the other conductive coating film 15 .

Then, using the resist films 28a, 28b as masks, the film 27 for pixel electrode formation is etched, as shown in FIGS. 8(A), 8(B). That is, the pixel electrode 2 and one conductive coating film 14 are formed under the resist film 28 a, and the other conductive coating film 15 is formed under the resist film 28 b. In this case, since the pair of conductive coating films 14 and 15 are formed simultaneously with the formation of the pixel electrode 2 using the same material as the pixel electrode 2, it is not necessary to increase the number of photolithography steps.

Also, in this state, source electrode 12 , ohmic contact layer 10 , and both end surfaces in the channel width W direction of semiconductor thin film 8 under one conductive coating film 14 are completely covered with one conductive coating film 14 . In addition, drain electrode 13 , ohmic contact layer 11 , and both end surfaces in the channel width W direction of semiconductor thin film 8 under another conductive coating film 15 are completely covered with another conductive coating film 15 .

Next, the resist films 28a, 28b are peeled off. Then, as shown in FIG. 1 and FIG. 2(A) and 2(B), on the upper surface of the gate insulating film 7 including the pixel electrode 2, etc., an overcoat film made of a silicon nitride film is formed by plasma CVD. 18 for film formation. In this way, as shown in FIG. 1 and FIGS. 2(A) and 2(B), a thin film transistor panel is obtained.

(second embodiment)

Fig. 9 has shown the perspective plan view of the main part of the thin film transistor panel as the second embodiment of the present invention, and Fig. 10 (A) has shown the sectional view along X _A -X _A of Fig. 9, and Fig. 10 (B) has shown along Fig. 9 Sectional view of X _B -X _B. In this thin film transistor panel, the difference from the thin film transistor panel shown in Figure 1 and Figure 2(A) and Figure 2(B) is that the pixel electrode 2 and a conductive coating film 14 are arranged The upper surface of the film 18 is connected to the source electrode 12 through the contact hole 19 provided in the overcoat film 18, and another conductive coating film 15 is arranged on the upper surface of the overcoat film 18 and through the contact hole 19 arranged in the overcoat film The contact hole 20 in 18 is connected to the drain electrode 13 .

(third embodiment)

11 shows a perspective plan view of the main part of the thin film transistor panel as the third embodiment of the present invention, FIG. 12(A) shows a cross-sectional view along XII _A -XII _A of FIG. Sectional view of XII _B -XII _B of 11. The biggest difference between this thin film transistor panel and the thin film transistor panel shown in FIG. 1 , FIG. 2(A) and FIG. 2(B) is that the thin film transistor 3 is made into a channel etching type.

That is, in the thin film transistor 3 of the thin film transistor panel, the channel protection film 9 is not provided, and the upper surface of the relatively thick semiconductor thin film 8 arranged in a planar cross shape at a predetermined position on the upper surface of the gate insulating film 7 is placed on a pair of Regions other than under the ohmic contact layers 10 and 11 have recesses 8 a.

In addition, in this thin film transistor 3, since each ohmic contact region 16, 17 extends to the end faces of the source electrode 12 and the drain electrode 13 on the side of the gate electrode 6, these end faces are partly covered by the respective conductive coating films 14, 15 covered. Furthermore, since the thin film transistor 3 in this case is a channel-etched type, it is possible to shorten the channel length L to some extent compared with the case of the first embodiment described above.

Next, an example of a method of manufacturing such a thin film transistor panel will be briefly described. First, the intrinsic amorphous silicon film formed relatively thickly on the upper surface of the gate insulating film 7 is patterned by photolithography to form a relatively thick semiconductor thin film 8 approximately in the shape of a cross in plan. The n-type amorphous silicon film and metal film continuously formed on the upper surface of the gate insulating film 7 of the semiconductor thin film 8 are patterned in sequence, thereby forming a source electrode 12, a drain electrode 13 and a pair of ohmic contact layers 10,11. In this case, recessed portion 8a is formed by overetching on the upper surface of semiconductor thin film 8 in the region other than under the pair of ohmic contact layers 10 and 11 .

Then, the ITO film formed on the upper surface of gate insulating film 7 including source electrode 12 and drain electrode 13 is patterned by photolithography to form pixel electrode 2 and a pair of conductive coating films 14 and 15 . Therefore, even in this case, it is not necessary to increase the number of photolithography steps. Also, a dedicated photolithography process for forming the semiconductor thin film 8 is necessary, but a photolithography process for forming the channel protective film is not required, so the number of photolithography processes does not increase as a whole.

(fourth embodiment)

13 shows a perspective plan view of the main part of the thin film transistor panel as the fourth embodiment of the present invention, FIG. 14(A) shows a sectional view along XIV _A -XIV _A of FIG. 13 , and 14(B) shows a cross-sectional view along XIV A of FIG. 13 Sectional view of _B -XIV _B. In this thin film transistor panel, the difference from the thin film transistor panel shown in FIG. 11 and FIG. 12(A) and FIG. 18 and is connected to the source electrode 12 through the contact hole 19 provided in the overcoat film 18, and another conductive coating film 15 is placed on the upper surface of the overcoat film 18 through the overcoat film The contact hole 20 in 18 is connected to the drain electrode 13 .

(fifth embodiment)

FIG. 15 is a perspective plan view showing a main part of a thin film transistor panel as a fifth embodiment of the present invention. FIG. 16(A) shows a sectional view taken along line XVI _A - XVI _A of FIG. 15 , and FIG. 16(B) shows a sectional view taken along line XVI _B - XVI _B of FIG. 15 . This thin film transistor panel differs from the thin film transistor panel shown in FIG. 1 and FIGS. 2(A) and 2(B) in that one conductive coating film 14 is omitted.

Furthermore, in the case shown in FIG. 1 and FIGS. 2(A) and 2(B), the other conductive coating film 15 may be omitted. In addition, in the case shown in FIG. 9 and FIGS. 10(A) and 10(B), either one of the pair of conductive coating films 14 and 15 may be omitted. In addition, in the cases shown in FIG. 11 , FIG. 12(A), and FIG. 12(B), either one of the pair of conductive coating films 14 and 15 may be omitted. In addition, in the case shown in FIG. 13 , FIG. 14(A), and FIG. 14(B), either one of the pair of conductive coating films 14 and 15 may be omitted.

(sixth embodiment)

FIG. 17 is a perspective plan view showing a main part of a thin film transistor panel as a sixth embodiment of the present invention. FIG. 18(A) shows a sectional view along XVIII _A -XVIII _A of FIG. 17 , and FIG. 18(B) shows a sectional view along XVIII _B -XVIII _B of FIG. 17 . The difference between this thin film transistor panel and the thin film transistor panel shown in FIG. 9 and FIG. 10(A) and FIG. It is not connected to the drain electrode 13 and is provided in an island shape on the upper surface of the overcoat film 18 . That is, when it is difficult to form the layout of the contact hole 20 on the overcoat film 18 on the drain electrode 13, another conductive coating film 15 is not electrically connected to the drain electrode 13 and is provided in an island shape on the overcoat film. 18 on the upper surface.

In this case, although the other conductive coating film 15 is island-shaped and electrically insulated from the drain electrode 13, a vertical electric field is formed due to capacitive coupling at the portion facing the drain electrode 13 through the overcoat film 18, Further, a vertical electric field is formed by capacitive coupling at the portion facing the gate electrode 6 through the overcoat film 18 and the gate insulating film 7 .

Claims (14)

1. A thin film transistor panel, characterized in that it has: A thin film transistor (3), comprising a semiconductor thin film (8) having a source region (16), a drain region (17) and a channel region, a source electrode (12) connected to the source region (16), a source electrode (12) connected to the drain region a drain electrode (13) connected to the region (17), and a gate electrode (6) formed corresponding to the channel region; A first transparent conductive film (14), connected to the source electrode (12), covering at least the entire source electrode (12) outside the channel region; A second transparent conductive film (15), connected to the drain electrode (13), covering at least the entire drain electrode (13) outside the channel region; The first transparent conductive film (14) is electrically insulated from the second transparent conductive film (15). 2. The thin film transistor panel according to claim 1, characterized in that, the second transparent conductive film (15) is formed from the outside of the channel region across the inside of the channel region. 3. The thin film transistor panel according to claim 1, characterized in that, the first conductive coating film (14) is arranged to be in contact with the upper surface of the source electrode (12), and is in contact with the pixel electrode (2) Continuously integrally formed. 4. The thin film transistor panel according to claim 1, characterized in that, the first conductive coating film (14) is arranged to be connected to the upper surface of the source electrode (12) and the side surfaces on both sides in the width direction, The sides of the ohmic contact layer (10) on both sides in the width direction are in contact. 5. The thin film transistor panel according to claim 1, characterized in that, the second conductive coating film (15) is provided in contact with the upper surface of the drain electrode (13), and The electrode (13) is extended so as to straddle a part of the drain wiring (5) connected to the drain electrode (13). 6. The thin film transistor panel according to claim 5, characterized in that, the conductive coating film (15) is arranged to be in contact with the upper surface of the drain electrode (13) and the side surfaces on both sides in the width direction thereof, the The side surfaces on both sides in the width direction of the ohmic contact layer (10) are in contact. 7. The thin film transistor panel according to claim 1, characterized in that it has an overcoat film (18) covering the thin film transistor (3), the pixel electrode (2) and the first and second conductive A permanent coating film (14, 15) is provided on the overcoating film (18). 8. The thin film transistor panel according to claim 7, characterized in that, the first conductive coating film (14) is arranged as a layer of the overcoating film (18) on the source electrode (12). The upper surface is continuous with the pixel electrode (2) and connected with the source electrode (12) through a contact hole (19) provided in the overcoat film (18). 9. The thin film transistor panel according to claim 7, characterized in that, the second conductive coating film (15) is disposed on the overcoating film (18) on the drain electrode (13) surface. 10. The thin film transistor panel according to claim 7, characterized in that, the second conductive coating film (15) communicates with the said overcoating film (18) through a contact hole (20) Drain connection. 11. The thin film transistor panel according to claim 1, characterized in that the end face of the source electrode (12) on the side opposite to the drain electrode (13) is not covered by the first conductive coating film (14) COVER. 12. The thin film transistor panel according to claim 1, characterized in that, the end face of the drain electrode (13) on the side opposite to the source electrode (12) is not covered by the second conductive coating film (15) COVER. 13. The thin film transistor panel according to claim 1, characterized in that there is an ohmic contact layer (10) between the semiconductor film (8) and the source electrode (12), and the source electrode (12) The end surface on the side opposite to the drain electrode (13) of the ohmic contact layer (10) below it is covered with the first conductive coating film (14). 14. The thin film transistor panel according to claim 1, characterized in that there is an ohmic contact layer (11) between the semiconductor film (8) and the drain electrode (13), and the drain electrode (13) The end surface on the side opposite to the source electrode (12) of the ohmic contact layer (11) below it is covered with the second conductive coating film (15).

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