CN101329852A - Common voltage driving circuit of liquid crystal display - Google Patents

Abstract

The present invention relates to a common voltage driving circuit of a liquid crystal display, comprising: a clock signal output unit, composed of first to sixth transistors and outputted by an external system according to the control output of at least one of the first to third gate output voltages The input first clock signal and the second clock signal; the output node voltage controller, including the seventh to the thirteenth transistor and the first to the fourth capacitor, and through the first and the second clock signal and the first to the third gate The output voltage changes the voltage of the positive and negative polarity output nodes; the initialization voltage supply unit includes the fourteenth to twentieth transistors and provides the initialization voltage to the output node voltage controller; and the common voltage output unit includes the twenty-second and the second Thirteen transistors and a fifth capacitor, and the voltage of the positive and negative output nodes is prevented from changing by the fifth capacitor when alternately outputting higher and lower common voltages according to the voltages of the positive and negative output nodes.

Description

Common voltage driving circuit of liquid crystal display

technical field

The invention relates to a device for supplying common voltage to a liquid crystal display (LCD), in particular to a common voltage drive circuit of the liquid crystal display capable of preventing the common voltage from floating in the liquid crystal panel.

Background technique

With the development of information technology (IT), the demand for flat panel display devices is rapidly increasing. Liquid crystal display is a traditional flat panel display device.

A liquid crystal display is a display device whose image information is respectively provided to pixels arranged in a matrix to control the light transmittance of the pixels to display a desired image. To this end, the liquid crystal display includes a liquid crystal panel on which pixels, which are minimum units for realizing an image, are arranged in a matrix and a driving IC (integrated circuit) (driver) driving the liquid crystal panel. In addition, since the liquid crystal display itself does not emit light, the liquid crystal display includes a backlight unit that provides light.

Generally, if the liquid crystal panel includes a common voltage driving circuit (driving IC), a positive or negative common voltage is applied to the liquid crystal panel through the common voltage driving circuit. In this case, a common voltage of a desired level (predetermined level) cannot be stably supplied due to parasitic capacitance or leakage current occurring near the driver circuit or peripheral circuits.

For example, when a common voltage of negative polarity is applied to the liquid crystal panel through the common voltage driving circuit, the voltage of the output node (Q node) is not maintained at a predetermined initial level, but is shown in FIG. 1 due to parasitic capacitance or leakage current. There is gradual change.

In other words, positive and negative polarity output node (Q node, Q node) voltages alternately maintain "low" levels, but fail to maintain a predetermined initial level (ideally Q node or ideally Q node) but gradually increased.

This results in a common voltage drift phenomenon, resulting in a defective screen image as shown in Figure 2.

Therefore, the related art liquid crystal display having the common voltage driving circuit cannot properly handle the variation of the common voltage of lower or higher level, causing deterioration of image quality.

Contents of the invention

Therefore, various features as described below are proposed here in order to deal with the above-mentioned problems. An aspect of the exemplary embodiments is to prevent a higher or lower common voltage from changing due to parasitic capacitance or leakage current when the common voltage is applied to the liquid crystal panel through the common voltage driving circuit.

Another aspect of the illustrative embodiments is to prevent changes in the common voltage by using capacitors of minimum capacitance.

The present invention provides a common voltage drive circuit for a liquid crystal display, comprising: a clock signal output unit, composed of first to sixth transistors M1 to M6 and outputting at least one of the first to third gate voltages VGOUT1, VGOUT2, and VGOUT3 Gate output voltage control outputs the first clock signal VCLK1 and the second clock signal VCLK2 input by the external system; the output node voltage controller includes the seventh to thirteenth transistors and the first to fourth capacitors, and passes the first clock The signal VCLK1 and the second clock signal VCLK2 and the first to third gate output voltages VGOUT1, VGOUT2, VGOUT3 change the voltages of the positive polarity output node Q node and the negative polarity output node Q node; the initialization voltage supply unit includes the fourteenth to the first Twenty-one transistors M14 to M21 and provide an initialization voltage to the output node voltage controller; and a common voltage output unit including twenty-second and twenty-third transistors M22, M23 and a fifth capacitor C5, and when output according to positive polarity The fifth capacitor C5 prevents the voltage change of the positive output node Q node and the negative output node Q node when the voltages of the node and the negative output node alternately output a higher common voltage and a lower common voltage.

The foregoing and other objects, features and advantages of the present invention will become more apparent with reference to the accompanying drawings and the following detailed description of the invention.

Description of drawings

FIG. 1 is a waveform diagram of an output node voltage of the related art;

2 is a schematic diagram illustrating a defective screen image due to a common voltage drift phenomenon in the related art;

3 is a circuit diagram of a common voltage drive circuit of a liquid crystal display (LCD) according to the present invention;

Fig. 4 a shows the waveform of each part in the first frame in Fig. 3; And

Fig. 4b shows the waveforms of each part in Fig. 3 in the second frame.

Detailed ways

Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram of a common voltage driving circuit of a liquid crystal display (LCD) according to the present invention.

As shown in Figure 3, the common voltage drive circuit includes: a clock signal input unit 31, including first to sixth MOS transistors M1 to M6, and inputs the first and second clock signals VCLK1 and VCLK2 according to the gate output voltage; the output node voltage The controller 32 includes seventh to thirteenth MOS transistors M7 to M13 and first to fourth capacitors C1 to C4, and outputs voltages VGOUT1 to C4 through first and second clock signals VCLK1 and VCLK2 and first to third gates VGOUT3 changes the voltage of the positive polarity output node (Q node) and the negative polarity output node (Q node); the initialization voltage supply unit 33 includes fourteenth to twenty-first MOS transistors M14 to M21, and provides an output node voltage controller 32 initialization voltage; and a common voltage output unit 34 including the twenty-second and twenty-third MOS transistors M22 and M23 and the fifth capacitor C5, and prevents the positive polarity output node (Q node) and The voltages of the negative polarity output nodes (Q nodes) are changed from their initial levels to alternately output a higher common voltage VCOMH or lower common voltage VCOML.

In the clock signal input unit 31, the terminal of the second clock signal VCLK2 is sequentially connected to the positive polarity output node (Q node) via (or through) the diode type first and second MOS transistors M1, M2 and the third MOS transistor M3 ), and the end of the first clock signal VCLK1 is sequentially connected to the negative polarity output node (Q node) via the diode type fourth and fifth MOS transistors M4, M5 and sixth MOS transistor M6. Likewise, the ends of the second gate output voltage VGOUT2 are simultaneously connected to the gates of the third and sixth MOS transistors M3, M6.

Here, with respect to the diode-type first and second MOS transistors M1 and M2 and the third MOS transistor M3 connected in series between the terminal to which the second clock signal VCLK2 is input and the positive polarity output node (Q node), the second The terminal of the clock signal VCLK2 is connected to the drain of the diode-type first MOS transistor M1, the source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2, and the source of the diode-type second MOS transistor M2 is connected to The drain of the third MOS transistor M3. The source of the third MOS transistor M3 is connected to the positive polarity output node (Q-node). Gates of the diode type first and second MOS transistors M1 and M2 are connected to a terminal to which the second clock signal VCLK2 is input.

With respect to the diode-type fourth and fifth MOS transistors M4 and M5 and sixth MOS transistor M6 connected between the terminal to which the first clock signal VCLK1 is input and the negative polarity output node Q node, The terminal is connected to the drain of the fourth MOS transistor M4, the source of the fourth MOS transistor M4 is connected to the drain of the diode-type fifth MOS transistor M5, and the source of the diode-type fifth MOS transistor M5 is connected to the sixth MOS transistor Drain of M6. The source of the sixth MOS transistor M6 is connected to the negative polarity output node (Q node). In addition, the gates of the diode type fourth and fifth MOS transistors M4 and M5 are connected to a terminal to which the first clock signal VCLK1 is input.

In the output node voltage controller 32, a plurality of first to fourth capacitors C1 to C4 are connected in series between a positive polarity output node (Q node) and a negative polarity output node (Q node), and between the plurality of first to fourth capacitors Of the fourth capacitors C1 to C4, first common connection points (or nodes) of the first and second capacitors C1 and C2 are connected to the intermediate connection node N1 and the power supply voltage terminal via the tenth and twelfth MOS transistors M10 and M12, respectively. VSS, wherein the intermediate connection node N1 is a common connection node of the second and third capacitors C2 and C3, and a voltage is applied externally to the power supply voltage terminal VSS. This first intermediate connection point N1 is usually electrically connected via eleventh and thirteenth MOS transistors M11 , M13 to a second common connection point between third and fourth capacitors C3 , C4 .

In addition, the first gate output voltage VGOUT1 is commonly connected to the gates of the twelfth and thirteenth MOS transistors M12-M13, which are connected in series to each other. The terminal to which the second gate output voltage VGOUT2 is input is connected to the gates of the tenth and eleventh MOS transistors M10-M11, which are connected in series to each other. The end portion of the output voltage VGOUT3 input by the third gate is electrically connected to the first capacitor between the first and second capacitors C1 and C2 through the eighth and ninth MOS transistors M8, M9 after passing through the diode-type seventh MOS transistor M7, respectively. The common connection node and the second common connection node between the third and fourth capacitors C3, C4.

Regarding the tenth and eleventh MOS transistors M10 and M11 and the The sources of the twelfth and thirteenth MOS transistors M12 and M13, the tenth and twelfth MOS transistors M10 and M12 are connected to the first common connection point, the sources of the eleventh and thirteenth MOS transistors M11 and M13 Connect to the second common connection point. The gates of the tenth and eleventh MOS transistors M10 and M11 are connected to each other so as to be connected to a terminal to which the second gate output voltage VGOUT2 is input, and the drains of the tenth and eleventh MOS transistors M10 and M11 are connected to each other at together to connect with the first intermediate connection node N1. In addition, the gates of the twelfth and thirteenth MOS transistors M12 and M13 are connected to each other to be connected to a terminal to which the first gate output voltage VGOUT1 is input, and the drains of the twelfth and thirteenth MOS transistors M12 and M13 The poles are connected together to be connected with the first intermediate connection node N1.

The drain and gate of the diode-type seventh MOS transistor M7 are commonly connected to a terminal to which the third gate output voltage VGOUT3 is input, and the source of the diode-type seventh MOS transistor M7 is commonly connected to the eighth and ninth MOS transistors M8 and the drain of M9. The source of the eighth MOS transistor M8 is connected to the first common connection point, and the source of the ninth MOS transistor M9 is connected to the second common connection point. The gate of the eighth MOS transistor M8 is connected to the positive polarity output node (Q-node), and the gate of the ninth MOS transistor M9 is connected to the negative polarity output node (Q-node).

In the initialization voltage supply unit 33, the terminal to which the first gate output voltage VGOUT1 is input is commonly connected to the respective gates of the fourteenth to seventeenth MOS transistors M14 to M17. Also, the power supply voltage terminal VSS is commonly connected to the second intermediate connection node N2, and the sources of the fifteenth and seventeenth MOS transistors M15 and M17 among the fourteenth to seventeenth MOS transistors M14 to M17 are commonly connected to the second intermediate connection node N2. The second intermediate connection node N2. The second intermediate connection node N2 is connected to the positive polarity output node (Q node) via the fourteenth and fifteenth MOS transistors M14, M15, and is also connected to the negative polarity output node via the sixteenth and seventeenth MOS transistors M16, M17. node (Q-node). Further, the second intermediate connection node N2 is connected to the negative polarity output node (Q node) via the eighteenth and nineteenth MOS transistors M18, M19, and is connected to the positive polarity via the twentieth and twenty-first MOS transistors M20, M21. Sexual output node (Q node). The positive polarity output node (Q node) is connected to the gates of the eighteenth and nineteenth MOS transistors M18, M19 and the negative polarity output node (Q node) is connected to the twentieth and twenty-first MOS transistors M20, Gate of M21.

In other words, between the positive polarity output node (Q-node) and the negative polarity output node (Q-node), the fourteenth and fifteenth MOS transistors M14 and M15 and the eighteenth and nineteenth MOS transistors M18 and M19 are connected in series to each other, and the sixteenth and seventeenth MOS transistors M16 and M17 and the twentieth and twenty-first MOS transistors M20 and M21 are connected in series to each other.

In this case, the gates of the fourteenth to seventeenth MOS transistors M14 to M17 are commonly connected to the terminal to which the first gate output voltage VGOUT1 is input, and the gates of the eighteenth and nineteenth MOS transistors M18 and M19 and the drain of the fourteenth MOS transistor M14 are connected to the positive polarity output node (Q-node), while the gates of the twentieth and twenty-first MOS transistors M20 and M21 and the drain of the sixteenth MOS transistor M16 Connect to the negative polarity output node (Q-node). The common connection point between the source of the fifteenth MOS transistor M15 and the drain of the eighteenth MOS transistor M18 and the common connection point between the source of the seventeenth MOS transistor M17 and the drain of the twentieth MOS transistor M20 The second intermediate connection node N2 connected to the connection point is connected to the power supply voltage terminal VSS.

In the common voltage output unit 34, a positive polarity output node (Q node) and a negative polarity output node (Q node) are connected to the gates of the twenty-second and twenty-third MOS transistors M22 and M23. The fifth capacitor C5 is connected between the gates of the twenty-second and twenty-third MOS transistors M22 and M23, and the terminals of the lower common voltage VCOML and the higher common voltage VCOMH are inputted via the twenty-second The second and twenty third MOS transistors M22, M23 are commonly connected to the common voltage output terminal VCOMOUT.

That is, the positive polarity output node (Q node) is connected to the gate of the twenty-second MOS transistor M22, and the negative polarity output node (Q node) is connected to the gate of the twenty-third MOS transistor M23. In this case, the fifth capacitor C5 is connected between the gates of the twenty-second MOS transistor M22 and the twenty-third MOS transistor M23. In addition, the end to which the high common voltage VCOMH is input is connected to the source of the twenty-second MOS transistor M22, and the end to which the low common voltage VCOML is input is connected to the source of the twenty-third MOS transistor M23. Drains of the twenty-second and twenty-third MOS transistors M22 and M23 are connected to each other to form output terminals of a common voltage.

The working principle of the invention constructed as described above will now be described in detail with reference to FIGS. 4a and 4b.

In the initial state of the first frame, the terminal voltage VSS of 10V is transmitted to the first intermediate connection point N1 of the first to fourth capacitors C1 to C4 connected in series. The first intermediate connection node N1 is commonly connected to a common connection point between the drains of the tenth and eleventh MOS transistors M10 and M11 and connected to between the drains of the twelfth and thirteenth MOS transistors M12 and M13 public connection point.

In this state, as shown in (a) of FIG. 4a, in the first frame, the first gate output voltage VGOUT1 is input at a low level (-8V), so the twelfth to seventeenth MOS transistors M12 to M17 conduction. Then, both ends of the second capacitor C2 are connected through the twelfth MOS transistor M12, and both ends of the third capacitor C3 are connected through the thirteenth MOS transistor M13.

In this way, the terminal voltage VSS is commonly transmitted to the positive polarity output node (Q node) and one end of the first capacitor C1 through the fourteenth and fifteenth MOS transistors M14 and M15. In addition, the terminal voltage VSS is generally transmitted to the negative polarity output node (Q node) and the other end of the fourth capacitor C4 through the sixteenth and seventeenth MOS transistors M16 and M17.

Therefore, when the first gate output voltage VGOUT1 is input at a low level (-8V) in the first frame, the respective intermediate connection points of the first to fourth capacitors C1 to C4 connected in series and the two output nodes (Q nodes ) (Q node) is initialized to 10V.

Subsequently, as shown in (b) of FIG. 4a, when the second gate output voltage VGOUT2 is input at a low level (-8V), the third MOS transistor M3 is turned on. Therefore, the -8V second clock signal VCLK2 shown in (f) of FIG. 4a is sequentially transmitted to the positive polarity output node Q node via the diode-type first and second MOS transistors M1 and M2 and the third MOS transistor M3.

Next, the voltage of -8V shown in (h) in Fig. 4a output from the positive polarity output node is transmitted to the gate of the twenty-second MOS transistor M22 at the output end, so that the twenty-second MOS transistor M22 is turned on .

At this time, the sixth MOS transistor M6 is also turned on by the second gate output voltage VGOUT2 of -8V, and since the first clock signal VCLK1 is 10V, the fourth and fifth MOS transistors M4 and M5 are not turned on, so the negative polarity output The voltage level of node Q is maintained at 10V, as shown in (i) of FIG. 4a.

Subsequently, as shown in (c) of Figure 4a, the third gate output voltage VGOUT3 is input at a low level (-8V), and is transmitted to the first and second Common connection point of capacitors C1, C2. Therefore, the voltage at the common connection point of the first and second capacitors C1, C2 is converted from 10V to -8V. Then, the voltage of the positive output node Q node is converted from -8V to -26V through bootstrapping, as shown in (h) of FIG. 4a.

The twenty-second MOS transistor M22 is fully turned on by the output voltage (-26V) output from the positive polarity output node (Q node).

Here, stable transition driving is performed by the twenty-second MOS transistor M22 fully turned on by bootstrap boost from -8V to -26V. That is, stable pulses cannot be supplied to the liquid crystal panel due to occurrence of a noise phenomenon due to rapid transition variations.

Therefore, the higher common voltage VCOMH shown in (d) of FIG. 4a is stably output to the common voltage output terminal VCOMOUT through the twenty-second MOS transistor M22. That is, the higher common voltage VCOMH is output from the common voltage output terminal VCOMOUT. Here, the higher common voltage VCOMH may be, for example, 5V.

In this way, when the higher common voltage VCOMH is output through the above process, generally, the voltage at the positive polarity output node Q node cannot be maintained at the predetermined initial level, but as shown in FIG. 1, due to surrounding parasitic capacitance or leakage current And gradually increase.

However, in the present invention, due to the presence of the capacitor (C5) connected between the positive polarity output node Q node and the negative polarity output node Q node, the voltage at the positive polarity output node Q node is not affected by surrounding parasitic capacitance or leakage current , so the voltage does not gradually increase. Therefore, the higher common voltage VCOMH can be output in a stable form, as shown in FIG. 4a.

When the second frame starts after the first frame, the first gate output voltage VGOUT1 is input at a low level (-8V), as shown in (a) in FIG. 4b, so that the twelfth to seventeenth MOS transistors M12 to M17 conduction. Thereafter, both ends of the second capacitor C2 are connected through the twelfth MOS transistor M12, and both ends of the third capacitor C3 are connected through the thirteenth MOS transistor M13.

At this time, the terminal voltage VSS of 10V is commonly transmitted to the positive polarity output node Q node and one end of the first capacitor C1 through the fourteenth and fifteenth MOS transistors M14 and M15 . Likewise, the terminal voltage VSS is commonly transmitted to the negative polarity output node Q node and the other end of the fourth capacitor C4 via the seventeenth and sixteenth MOS transistors M17 and M16 .

Therefore, in the second frame, when the first gate output voltage VGOUT1 is input at a low level (-8V), the voltage at the positive polarity output node (Q node) is converted from -26V to 10V, as shown in Figure 4b (h) As shown, the voltage at the output node (Q node) of negative polarity remains at 10V as in the first frame.

Thereafter, as shown in (b) of FIG. 4b, the second gate output voltage VGOUT2 is input at a low level (-8V), thereby turning on the third MOS transistor M3. Then, as shown in (f) of FIG. 4b, the 10V second clock signal VCLK2 is sequentially transmitted to the positive polarity output node Q node through the diode-type first and second MOS transistors M1 and M2 and the third MOS transistor M3. Thus, since the voltage with a potential of 10V has been applied to the positive polarity output node Q node through the above process, the potential at the positive polarity output node Q node does not change, as shown in (h) of FIG. 4b.

At this time, the sixth MOS transistor M6 is turned on by the second gate output voltage VGOUT2 of -8V. Therefore, as shown in (g) of FIG. 4b, the first clock signal VCLK1 of -8V is transmitted to the negative polarity output node Q node through the diode-type fourth and fifth MOS transistors M4 and M5 and the sixth MOS transistor M6. Therefore, the potential of the negative polarity output node Q node is switched from 10V to -8V, as shown in (i) of FIG. 4b.

Finally, the voltage of -8V output from the negative polarity output node Q node is transmitted to the gate of the twenty-third MOS transistor M23 of the common voltage output unit 34, so that the twenty-third MOS transistor M23 starts to be turned on.

Afterwards, the third gate output voltage VGOUT3 is input at a low level (-8V), as shown in (c) in Figure 4b, and then transmitted to the third and fourth through the diode-type seventh MOS transistor M7 and ninth MOS transistor M9 Common connection point of capacitors C3 and C4. Therefore, the voltage at the common connection point of the third and fourth capacitors C3, C4 is switched from 10V to -8V. Immediately afterwards, the voltage at the negative polarity output node Q node is converted from -8V to -26V due to bootstrap, as shown in (i) in Figure 4b.

The twenty-third MOS transistor M23 is fully turned on by the output voltage of -26V output from the negative polarity output node Q node.

Here, the twenty-third MOS transistor M23 fully turned on by the bootstrap boost from -8V to -26V performs stable transition driving. That is, stable pulses cannot be supplied to the liquid crystal panel due to occurrence of a noise phenomenon due to rapid transition variations.

Therefore, as shown in (e) of FIG. 4b, the lower common voltage VCOML is stably output to the common voltage output terminal VCOMOUT through the twenty-third MOS transistor M23. That is, the lower common voltage VCOML of the 0 level is output from the common voltage output terminal VCOMOUT. Here, for example, the lower common voltage VCOML may be 0V.

Thus, when the lower common voltage VCOML is output through the above process, generally, the voltage at the negative polarity output node Q node cannot be maintained at the predetermined initial level, but as shown in FIG. 1, due to surrounding parasitic capacitance and leakage current presence gradually increased.

However, in the present invention, due to the presence of the capacitor (C5) connected between the positive and negative polarity output nodes Q node and Q node, the voltage at the negative polarity output node Q node is not affected by surrounding parasitic capacitance or leakage current, so , the voltage does not increase gradually.

Therefore, the lower common voltage VCOML can be output in a stable form, as shown in FIG. 4b.

Likewise, if the fifth capacitor C5 in the common voltage output unit 34 is omitted, the present invention can replace the role of the fifth capacitor C5 by increasing the capacitance of the first to fourth capacitors C1 to C4 in the output node voltage controller 32 .

However, in this case, since the capacitances of the first to fourth capacitors C1 to C4 increase the capacitance of the fifth capacitor C5, the total capacitance value of the capacitors is doubled compared with the case of using the fifth capacitor C5, and therefore , no effect (ineffective).

In addition, since the first to fourth capacitors C1 to C4 of the output node voltage controller 32 occupy about 30% of the entire circuit area, the increase in capacitance of the first to fourth capacitors C1 to C4 requires more installation space.

Experimental results show that when the capacitance of the fifth capacitor C5 exceeds 0.1 pF, the initial voltage levels of the positive output node Q node and the negative output node Q node can be stably maintained.

As shown above, in the present invention, when the common voltage is supplied to the liquid crystal panel via the common voltage driving circuit of the LCD, a capacitor is installed at the output terminal to prevent the common voltage from changing due to parasitic capacitance or leakage current. Therefore, the liquid crystal panel is stably driven, thereby preventing deterioration of image quality.

Also, installing capacitors in the common voltage output unit is more effective than installing capacitors in the output node voltage controller, thereby stabilizing the common voltage with capacitors of small capacitance.

The present invention can be embodied in various forms without departing from its characteristics, and it should be understood that the above-described embodiments are not limited to any details of the foregoing description unless otherwise indicated, but are to be construed broadly within the scope defined in the appended claims. , and therefore the appended claims are intended to cover all changes and modifications which fall within the spirit and scope of the appended claims, or equivalents of such spirit and scope.

Claims (18)

1. A common voltage drive circuit of a liquid crystal display, comprising: The clock signal output unit includes first to sixth transistors (M1 to M6) and outputs the first gate output voltage input by the external system according to the control of at least one of the first to third gate output voltages (VGOUT1, VGOUT2, VGOUT3). A clock signal (VCLK1) and a second clock signal (VCLK2); The output node voltage controller includes seventh to thirteenth transistors (M7-M13) and first to fourth capacitors (C1-C4), and passes the first clock signal (VCLK1) and the second clock signal (VCLK2) and The first to third gate output voltages (VGOUT1, VGOUT2, VGOUT3) change the voltages of the positive polarity output node (Q node) and the negative polarity output node (Q node); an initialization voltage supply unit including fourteenth to twenty-first transistors (M14-M21) and providing an initialization voltage to the output node voltage controller; and A common voltage output unit comprising twenty-second and twenty-third transistors (M22, M23) and a fifth capacitor (C5), and when according to the positive polarity output node (Q node) and the negative polarity output node (Q node) When the voltage alternately outputs a higher common voltage and a lower common voltage, the fifth capacitor (C5) prevents the voltage change of the positive polarity output node (Q node) and the negative polarity output node (Q node). 2. The driving circuit according to claim 1, wherein the first to twenty-third transistors are MOS transistors. 3. The drive circuit according to claim 1, characterized in that, in the clock signal output unit, ends of the second clock signal (VCLK2) inputted from the outside are commonly connected to the diode-type first and second MOS transistors The gate of (M1, M2) and the drain of the diode-type first MOS transistor (M1), the source of the diode-type first MOS transistor (M1) and the drain of the diode-type second MOS transistor (M2) are connected to each other at Together, the source of the diode-type second MOS transistor (M2) and the drain of the third MOS transistor (M3) are connected to each other, and the ends of the first clock signal (VCLK1) input from the outside are commonly connected to the diode-type The gate of the fourth and fifth MOS transistors (M4, M5) and the drain of the diode-type fourth MOS transistor (M4), the source of the diode-type fourth MOS transistor (M4) and the diode-type fifth MOS transistor (M5) ) drains are connected to each other, the source of the diode-type fifth MOS transistor (M5) and the drain of the sixth MOS transistor (M6) are connected to each other, and the terminals of the second gate output voltage (VGOUT2) from the outside are common The ground is connected to the gates of the third and sixth MOS transistors (M3, M6), the source of the third MOS transistor (M3) is connected to the positive polarity output node (Q node), and the source of the sixth MOS transistor (M6) pole is connected to the negative polarity output node (Q node). 4. The drive circuit according to claim 3, characterized in that said first and second clock signals (VCLK1, VCLK2) have opposite phases to each other. 5. The driving circuit according to claim 3, characterized in that, the "low" level of the first and second clock signals (VCLK1, VCLK2) is -8V, and the first and second clock signals ( The "high" level of VCLK1, VCLK2) is 10V. 6. The driving circuit according to claim 1, wherein, in the output node voltage controller, the first to fourth capacitors C1 to C4 are connected in series between the positive polarity output node (Q node) and the negative polarity output node (Q node) Q node), the common connection point of the first and second capacitors (C1, C2) is connected to the sources of the eighth, tenth and twelfth MOS transistors (M8, M10, M12), the third and fourth The common connection point of the capacitor (C3, C4) is connected to the sources of the ninth, eleventh and thirteenth MOS transistors (M9, M11, M13), and the second and third capacitors (C2, C3) between the An intermediate connection node (N1) is commonly connected to the drains of the tenth to thirteenth MOS transistors (M10, M13) and the power supply voltage terminal (VSS), and the terminal of the first gate output voltage (VGOUT1) is commonly connected to The gates of the twelfth and thirteenth MOS transistors (M12, M13), the terminals of the second gate output voltage (VGOUT2) are commonly connected to the gates of the tenth and eleventh MOS transistors (M10, M11), Terminals of the third gate output voltage (VGOUT3) are commonly connected to the gate and drain of the diode-type seventh MOS transistor (M7), the drains of the eighth and ninth MOS transistors (M8, M9) and the diode-type seventh MOS transistor (M8, M9). The sources of the seven MOS transistors (M7) are connected to each other, the gates of the eighth MOS transistor (M8) are connected to the positive polarity output node (Q node), and the gates of the ninth MOS transistor (M9) are connected to the negative polarity output node ( Q node). 7. The driving circuit according to claim 1, wherein the first to third gate output voltages (VGOUT1, VGOUT2, VGOUT3) are sequentially switched from high level to low level every predetermined time period. 8. The driving circuit according to claim 6, wherein the first to third gate output voltages (VGOUT1, VGOUT2, VGOUT3) are maintained at 10V or -8V. 9. The driving circuit according to claim 1, characterized in that, in the initialization voltage supply unit, terminals of the first gate output voltage (VGOUT1) input from the outside are commonly connected to the fourteenth to tenth The gates of the seven MOS transistors (M14 to M17), the positive polarity output node (Q node) is connected to the drain of the fourteenth MOS transistor (M14), the gates of the eighteenth and nineteenth MOS transistors (M18, M19) pole and the source of the twenty-first MOS transistor (M21), the negative polarity output node (Q node) is connected to the drain of the sixteenth MOS transistor (M16), the twenty and twenty-first MOS transistors (M20, The gate of M21) and the source of the nineteenth MOS transistor (M19), the power supply voltage terminal (VSS) is connected to the second intermediate connection node (N2), wherein the second intermediate connection node (N2) is commonly connected to the tenth The sources of the fifth and seventeenth MOS transistors (M15, M17) and the drains of the eighteenth and twentieth MOS transistors (M18, M20), the source of the fourteenth MOS transistor (M14) and the fifteenth MOS transistors The drains of the transistors (M15) are connected together, the source of the sixteenth MOS transistor (M16) and the drains of the seventeenth MOS transistor (M17) are connected together, the source of the eighteenth MOS transistor (M18) The electrode and the drain of the nineteenth MOS transistor (M19) are connected to each other, and the source of the twentieth MOS transistor (M20) and the drain of the twenty-first MOS transistor (M21) are connected to each other. 10. The drive circuit according to claim 9, wherein the positive and negative polarity output nodes (Q node, Q node) are synchronized with the first to third gate output voltages (VGOUT1, VGOUT2, VGOUT3) at 10V, The order of -8V and -26V is converted sequentially. 11. The drive circuit according to claim 1, characterized in that, in the common voltage output unit, the positive polarity output node (Q node) is connected to the gate of the twenty-second MOS transistor (M22), and the negative polarity The output node (Q node) is connected to the gate of the twenty-third MOS transistor (M23), and the fifth capacitor (C5) is connected between the gates of the twenty-second and twenty-third MOS transistors (M22, M23) , the terminal of the higher common voltage (VCOMH) is connected to the source of the twenty-second MOS transistor (M22), and the terminal of the lower common voltage (VCOML) is connected to the source of the twenty-third MOS transistor (M23). sources, and the twenty-second and twenty-third MOS transistors (M22, M23) are commonly connected to the common voltage output terminal (VCOMOUT). 12. The drive circuit according to claim 11, characterized in that said higher common voltage (VCOMH) is 5V. 13. The driving circuit according to claim 11, characterized in that the lower common voltage (VCOML) is 0V. 14. The drive circuit according to claim 11, characterized in that, when a higher common voltage (VCOMH) is output through the twenty-second MOS transistor (M22), the fifth capacitor (C5) prevents the twenty-second The gate voltage of the two MOS transistors (M22) changes. 15. The driving circuit according to claim 11, characterized in that, when the lower common voltage (VCOML) is output through the twenty-third MOS transistor (M23), the fifth capacitor (C5) prevents the second The gate voltage of the thirteen MOS transistors (M23) varies. 16. The driving circuit according to claim 11, characterized in that, the twenty-second and twenty-third MOS transistors (M22, M23) alternately conduct voltages of positive and negative polarity output nodes (Q nodes, Q nodes) Pass. 17. The drive circuit according to claim 11, wherein the fifth capacitor C5 has a capacitance of 0.1 pF or greater. 18. The driving circuit according to claim 1, wherein the liquid crystal display comprises a liquid crystal panel in which a common voltage driving circuit is installed.

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