CN100430991C - Method for eliminating ghost of display device - Google Patents

Abstract

The invention provides a gate driving circuit capable of eliminating shutdown afterimage, which is applicable to a display device. The gate driving circuit of the present invention includes: the circuit comprises a first capacitor, a diode, a second capacitor and a voltage stabilizing circuit. The first capacitor is used for filtering high-frequency surge and high-frequency noise of the input voltage, the diode is used for receiving the input voltage, the second capacitor is charged through forward conduction of the diode and provides the input voltage for the voltage stabilizing circuit, and finally the output voltage is transmitted to a logic circuit in the display device through voltage level conversion of the voltage stabilizing circuit.

Description

Method for Eliminating Afterimages of Display Devices

technical field

The present invention relates to a gate drive circuit, and in particular to a gate drive device for eliminating afterimage after shutdown of a display device.

Background technique

Figure 1 is a timing diagram for driving a TFT liquid crystal display. Please refer to Figure 1. The traditional TFT liquid crystal display includes a display panel and a backlight module. However, the current internal startup procedure of the TFT liquid crystal display is to first turn on the total power supply of the TFT liquid crystal display at the time sequence t _N1 (as shown in curve A), including the power applied to the TFT liquid crystal display. The voltage on the common electrode and pixel electrode of the liquid crystal display. Next, input the image signal (as shown by curve B) into the pixel structure of the TFT liquid crystal display at timing t _N2 , and then turn on the backlight module (as shown by curve C) at timing t _N3 to provide a light source for the display panel, thereby enabling TFT liquid crystal display displays images. Please continue to refer to Figure 1. The shutdown procedure inside a traditional TFT liquid crystal display is the opposite of its startup procedure. It first turns off the backlight module at timing t _F1 , and the image signal input to the pixel structure is completely completed at timing t _F2 , and then at timing t F2 _F3 turns off the total power of the TFT LCD display.

As mentioned above, after turning off the backlight module and before the end of the image signal, that is, during the time sequence t _F1 to t _F2 (usually 16.7 milliseconds), since the image signal still exists in the pixel structure, and the pixel electrode Charges remain, and these residual charges have no effective discharge path, so it takes a period of time to fully discharge. Therefore, after the TFT liquid crystal display is turned off, image sticking often occurs after the time sequence t _F3 .

FIG. 2 is a gate drive circuit diagram of a known display device, and FIG. 3 is a timing diagram of a logic drive power shutdown of a known display device. Please refer to FIG. 2 and FIG. 3 together. When the display device is powered on, FIG. 2 utilizes an inductor 201 and capacitors 203, 205 with an integrated voltage regulator circuit 207 to provide the driving power (VDD) required by the logic circuit on the display device. . The gate logic drive power supply (VGH, VGL) will pass through the voltage shifter (Levelshifter) of each channel circuit in the gate drive circuit (Gate driver) according to the logic state (VDD or VSS) provided by the logic circuit of the display device, Convert the logic state (VDD or VSS) into the gate logic drive power (VGH or VGL), thereby turning on or off the thin film transistors of the pixel structure in the display device.

Then, when the display device is turned off (as shown by the dotted line I in FIG. 3 ), the logic drive power supply (VDD) and the gate logic drive power supply (VGH, VGL) are turned off at the same time, which causes the gate drive of the display device to be closed after the display device is turned off. The power supply (VGH, VGL) still has residual charges to turn on or turn off the thin film transistors of the pixel structure in the display device, and then image sticking occurs.

In order to solve the above problems, the known technology is to use three control ICs with a microprocessor to control the turn-off sequence of the driving power (VDD, VGH, VGL) required by the logic circuit on the display device after the timing _tF3 . In this way, when the display device is turned off, the turn-off sequence of the logic driving power supply (VDD) will be extended to turn on the thin film transistors of all pixel structures in the display device, and then the pixel electrodes will be rapidly discharged to eliminate after-image after shutdown.

However, since the known method must use three more control ICs and a microprocessor to control the turn-off sequence of the drive power (VDD, VGH, VGL) required by the logic circuit on the display device, it is also difficult to consider in terms of manufacturing cost. It is more improved.

Contents of the invention

In view of the above circumstances, the object of the present invention is to provide a gate driving circuit of a display device for eliminating image sticking generated when the display device is turned off.

The present invention converts an input voltage to a voltage level first, and then provides the driving power (VDD) required by the logic circuit in the display device. The gate driving circuit of the present invention includes: a first capacitor, a diode, a second capacitor and a voltage stabilizing circuit. Among them, the first capacitor is used to filter the high-frequency surge and high-frequency noise of the input voltage, and the diode is used to receive the input voltage, and then charge the second capacitor through the forward conduction of the diode and provide the input voltage to stabilize the voltage. circuit, and finally through the voltage level conversion of the voltage stabilizing circuit, the output voltage is sent to the logic circuit in the display device.

Because of the present invention, the driving power (VDD) required by the logic circuit in the display device can be extended when the display device is turned off. Therefore, compared with the known technology, the use of three control ICs and microprocessors will be replaced, and the cost of manufacturing can be reduced.

In order to make the above-mentioned and other features and advantages of the present invention more comprehensible, preferred embodiments are described in detail below together with the accompanying drawings.

Description of drawings

Figure 1 is a timing diagram for driving a TFT liquid crystal display.

FIG. 2 is a gate driving circuit diagram of a known display device.

FIG. 3 is a timing diagram of a conventional display device logic drive power off.

FIG. 4 is a structural diagram of a conventional gate driving circuit for a display device.

FIG. 5 is a diagram of a gate driving circuit according to a preferred embodiment of the present invention.

FIG. 6 is a timing diagram of turning off the logic driving power according to an embodiment of the present invention.

FIG. 7 is a timing diagram of turning off the logic driving power according to another embodiment of the present invention.

Description of main component marking

201: Inductor

203, 205: Capacitor

207: Integrated voltage regulator circuit

401: decoder

402: Voltage Shifter

403: output stage

500: Gate drive circuit

501: first capacitor

503: diode

505: second capacitor

507: voltage regulator circuit

S0～Sn: Control signal of shift register

G1～Gm: Gate lines in the display device

I: Display device off timing

D1, D2: delay timing of the logic drive power supply VDD after the display device is turned off

VIN: input voltage

VINP: Input voltage (VIN-0.25V)

VSS: reference potential

VDD: logic drive power supply

VGH, VGL: gate logic drive power supply

t _N1 , t _N2 , t _N3 , t _F1 , t _F2 , t _F3 : timing

Detailed ways

FIG. 4 is a structural diagram of a conventional gate driving circuit for a display device. The decoder 401 has a plurality of output terminals, and each output terminal is coupled to a voltage shifter and an output stage, thus forming each channel circuit, and finally coupled to one of the gate lines G1-Gm in the display device one.

The decoder 401 first receives the control signals S0-Sn provided by the shift register, wherein the control signals S0-Sn designate gate lines of the display device to be turned on. For example, if the gate line G1 is to be turned on, the decoder 401 will output a logic 1 (that is, the logic driving power VDD provided by the present invention) to the voltage shifter 402 after decoding the control signals S0˜Sn, and output a logic 0 (that is, The present invention provides the reference potential VSS) to other voltage shifters. Next, the voltage shifter 402 will boost the logic driving power supply VDD to the gate logic driving power supply VGH with the input logic 1 signal, and then output it to the corresponding output stage, while other voltage shifters will input logic 0 The signal of the reference potential VSS is stepped down to the gate logic dynamic power supply VGL, and then output to the corresponding output stage, so that the gate line G1 turns on the thin film transistor of the pixel structure in the display device because of the logic 1, and the other gate lines G2-Gm turn off the thin film transistors of the pixel structure in the display device due to the logic 0.

Next, FIG. 5 is a diagram of a gate driving circuit according to a preferred embodiment of the present invention. Referring to FIG. 5 , the gate driving circuit 500 of the present invention includes a first capacitor 501 , a diode 503 , a second capacitor 505 and a voltage stabilizing circuit 507 . Wherein, the first capacitor 501 is coupled between the input voltage VIN and the reference potential VSS, the reference potential can be ground potential, the anode terminal of the diode 503 is used to receive the input voltage VIN, and the cathode terminal is respectively coupled to the second capacitor 505 The positive terminal and the input terminal of the voltage stabilizing circuit 507. In addition, the cathode end of the second capacitor 505 and the ground end of the voltage stabilizing circuit 507 are coupled to the reference potential VSS, and finally the logic driving power VDD is provided to the logic in the display device through the voltage level conversion of the voltage stabilizing circuit 507. circuit, wherein the voltage stabilizing circuit 507 can be an integrated voltage stabilizing circuit.

In this embodiment, the first capacitor 501 will first filter out the high-frequency surge and high-frequency noise of the input voltage VIN, which can be +5V, and then provide a stable input voltage VIN to make the diode 503 forward and provide the input voltage VINP (VIN-0.25V) to the input terminal of the voltage stabilizing circuit 507 and charge the second capacitor 505, and then convert the input voltage VINP (VIN-0.25V) to the voltage level through the stabilizing circuit 507 , and finally provide logic driving power VDD to the logic circuit in the display device, wherein the logic driving power VDD is the output voltage provided by the gate driving circuit, and the output voltage can be +3.3V.

Wherein, the first capacitor 501 in a preferred embodiment of the present invention may be a ceramic capacitor or a tantalum capacitor, and the capacitance value may be 0.1uF. The diode 503 can be a Schottky diode, and because the forward conduction voltage of the Schottky diode is lower than that of a general diode, it can be 0.25V here, so when the display device is turned off, the voltage difference between the two ends of the diode 503 is small (VIN- 0.25V), so the amount of current flowing back through the diode 505 is small, and the second capacitor 505 is used to store the charge, and the logic driving power VDD output by the voltage stabilizing circuit 507 is delayed by a time sequence. In the present invention, the second capacitor 505 may be an electrolyte capacitor.

Here, the capacitance of the second capacitor 505 will determine the timing delay of the logic driving power VDD after the display device is turned off. When the capacitor value is larger, the delay time sequence D2 of the logic driving power supply VDD is relatively long; and when the capacitance value is small, the delay sequence D1 of the logic driving power supply VDD is relatively short.

Fig. 6 and Fig. 7 are a kind of logical drive power off timing diagram according to the second capacitor with different capacitance values, please refer to Fig. 5, Fig. 6 and Fig. 7 together, when the capacitance value selected for the second capacitor 505 in Fig. 5 When it is 330uF, the logic driving power VDD will generate a delayed timing D1 after the display device is turned off, and when the second capacitor 505 is 1000uF, the logic driving power VDD will generate a delayed timing D2 after the display device is turned off . Although the second capacitors with two capacitance values are provided above, those skilled in the art should know that the capacitance value of the second capacitor does not affect the main spirit of the present invention. Therefore, those skilled in the art can adjust the capacitance of the second capacitor according to actual needs.

To sum up, the present invention provides a gate driving circuit, which is applicable to a display device. Since the present invention utilizes the diode 503 and the second capacitor 505, the logic drive power supply VDD is extended by a time sequence when the display device is turned off, thereby turning on the thin film transistors of all pixel structures in the display device, and then rapidly discharging the pixel electrodes to achieve elimination. After power off, compared with the known technology, the advantage of the present invention is that it does not need to use three more control ICs and microprocessors, so it is also relatively low in cost considerations.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (12)

1. A gate drive circuit capable of eliminating ghosting, which is characterized in that it is suitable for a display device, and is used to convert the input voltage into an output voltage to supply the power required by the logic circuit and delay the timing of the power supply. The pole drive circuit consists of: a first capacitor coupled between the input voltage and a reference potential; a diode, the anode terminal of which receives the input voltage; a second capacitor coupled between the cathode terminal of the diode and the reference potential; and The regulator circuit is coupled to the cathode terminal of the diode to generate the output voltage to the logic circuit. 2 . The gate drive circuit capable of eliminating image sticking according to claim 1 , wherein the first capacitor is a ceramic capacitor for filtering high-frequency surge and high-frequency noise of the input voltage. 3 . The gate drive circuit capable of eliminating image sticking according to claim 1 , wherein the first capacitor is a tantalum capacitor for filtering high-frequency surges and high-frequency noise of the input voltage. 4. The gate drive circuit capable of eliminating image sticking according to claim 1, wherein the diode is a Schottky diode. 5 . The gate drive circuit capable of eliminating image sticking according to claim 4 , wherein the forward conduction voltage of the Schottky diode is 0.25V. 6. The gate drive circuit capable of eliminating image sticking according to claim 1, wherein the second capacitor is an electrolyte capacitor. 7. The gate drive circuit capable of eliminating image sticking according to claim 1, wherein the capacitance of the second capacitor is 330uF. 8. The gate drive circuit capable of eliminating image sticking according to claim 1, wherein the capacitance of the second capacitor is 1000uF. 9. The gate drive circuit capable of eliminating image sticking according to claim 1, wherein the voltage stabilizing circuit is an integrated voltage stabilizing circuit. 10. The gate drive circuit capable of eliminating image sticking according to claim 1, wherein the input voltage is +5V. 11. The gate drive circuit capable of eliminating image sticking according to claim 1, wherein the output voltage is +3.3V. 12. The gate drive circuit capable of eliminating image sticking according to claim 1, wherein the reference potential is a ground potential.

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