KR101349780B1 - Common voltage generation circuit of liquid crystal display - Google Patents

Abstract

According to the present invention, when a common voltage is supplied to a liquid crystal panel in a common voltage driving circuit of a liquid crystal display device, the voltage of the output node is not maintained as it is, but is changed due to parasitic capacitance or leakage current, thereby preventing display defects. It is about technology to do. The present invention comprises a clock signal input unit which is composed of a plurality of MOS transistors, and receives first and second clock signals under control of a gate output voltage; An output node voltage control unit comprising a plurality of MOS transistors and a capacitor, the output node voltage control unit changing a voltage of the positive and negative polarity output nodes by the first and second clock signals and the first and third gate output voltages; An initialization voltage supply unit comprising a plurality of MOS transistors, the initialization voltage supply unit supplying an initialization voltage of the output node voltage control unit; Composed of a plurality of MOS transistor and one capacitor, the output voltage of the positive and negative polarity of the positive and negative polarity is changed by using the capacitor to alternately output the upper and lower common voltage according to the voltage of the positive and negative output node Achieved by a common voltage output.

LCD, Common Voltage

Description

Common voltage driving circuit of liquid crystal display device {COMMON VOLTAGE GENERATION CIRCUIT OF LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for supplying a common voltage of a liquid crystal display device, and more particularly, to a common voltage driving circuit of a liquid crystal display device suitable for preventing a common voltage from floating in a liquid crystal panel having a common voltage driving circuit. .

Recently, the demand for flat panel display devices is rapidly increasing due to the development of information technology (IT). As a representative example of the flat panel display device, there may be mentioned a liquid crystal display (LCD).

A liquid crystal display device is a display device in which image information is individually supplied to pixels arranged in a matrix, and the light transmittance of the pixels is adjusted to display a desired image. To this end, the liquid crystal display includes a liquid crystal panel in which pixels, which are the smallest units for implementing an image, are arranged in an active matrix form, and a drive IC for driving the liquid crystal panel. Since the LCD does not emit light by itself, the LCD includes a backlight unit that supplies light to the LCD.

In general, in the case of a liquid crystal panel in which a common voltage driving circuit (drive IC) is incorporated, a common voltage of positive polarity or negative polarity is supplied to the liquid crystal panel through the common voltage driving circuit. Due to the existing parasitic capacitance or leakage current, it is impossible to stably supply a common voltage of a desired level.

For example, when supplying a negative common voltage to the liquid crystal panel through the common voltage driving circuit, the voltage of the output node is not maintained at the desired initial level and gradually becomes as shown in FIG. 1 due to the parasitic capacitance or the leakage current. Was changed.

-Node)의 전압이 서로 교번되게 '로우'레벨을 유지하게 되는데, 원래 목적한 초기 레벨(Ideal Case Q-Node 또는 Ideal Case

-Node)를 유지하지 못하고 점진적으로 상승(Real Case Q-Node 또는 Real Case

-Node)되었다.That is, the positive and negative output nodes (Q-Node), (

The voltages of the nodes are alternately maintained at the low level. The original initial level (Ideal Case Q-Node or Ideal Case) is maintained.

-Node can't hold and gradually rises (Real Case Q-Node or Real Case)

-Node).

As a result, a common voltage floating phenomenon occurs, and as a result, a screen defect phenomenon occurs as shown in FIG. 2.

As described above, in the liquid crystal display device in which the common voltage driving circuit is incorporated, there is a problem in that the lowering or the upper common voltage level is not appropriately responded to, thereby causing a deterioration in image quality.

Accordingly, an object of the present invention is to prevent the common voltage from fluctuating due to parasitic capacitance or leakage current when supplying the common voltage of the lower or upper level to the liquid crystal panel through the common voltage driving circuit.

Still another object of the present invention is to prevent the common voltage from changing by using a capacitor having a minimum capacity.

The present invention for achieving the above object, the clock signal input unit for inputting the first and second clock signal under the control of the gate output voltage; An output node voltage controller configured to change the voltages of the positive and negative polarity output nodes by the first and second clock signals and the first and third gate output voltages; An initialization voltage supply unit supplying an initialization voltage of the output node voltage controller; It is characterized by comprising a common voltage output unit for preventing the voltage of the positive and negative polarity output node is changed by using a capacitor in alternately outputting the upper and lower common voltage according to the voltage of the positive and negative polarity output node. .

The present invention provides a common voltage to the liquid crystal panel through a common voltage driving circuit of the liquid crystal display device, by installing a capacitor at the output terminal, and by using this to prevent the common voltage from being changed due to parasitic capacitance or leakage current, It is possible to drive more stably, and thereby there is an effect that can prevent the degradation of the image quality.

In addition, by providing a capacitor in the common voltage output unit, there is an effect that the common voltage can be stabilized using a capacitor having a smaller capacity than that provided in the output node voltage control unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

-Node)의 전압을 변화시키는 출력노드전압 제어부(32)와; 모스트랜지스터(M14-M21)로 구성되어, 상기 출력노드전압 제어부(32)의 초기화전압을 공급하는 초기화전압 공급부(33)와; 모스트랜지스터(M22,M233) 및 콘덴서(C5)로 구성되어, 상기 정,부극성출력노드(Q-Node),(

-Node)의 전압에 따라 상위공통전압(VCOMH) 또는 하위공통전압(VCOML)을 교번되게 출력함에 있어서 그 콘덴서(C5)를 이용하여 상기 정,부극성출력노드(Q-Node),(

-Node)의 전압이 초기 레벨로부터 변화되는 것을 방지하는 공통전압 출력부(34)로 구성하였다.FIG. 3 is a circuit diagram showing an embodiment of a common voltage driving circuit of a liquid crystal display according to the present invention. As shown in FIG. A clock signal input unit 31 for inputting two clock signals VCLK1 and VCLK2; It is composed of a MOS transistor (M7-M13) and a capacitor (C1-C4), and the positive and negative output node (VGOUT1-VGOUT3) by the first and second clock signals (VCLK1), (VCLK2) and gate output voltage (VGOUT1-VGOUT3) Q-Node), (

An output node voltage control unit 32 for changing a voltage of the node; An initialization voltage supply unit (33) configured of morph transistors (M14-M21) for supplying an initialization voltage of the output node voltage control unit (32); Most transistors (M22, M233) and capacitor (C5), the positive and negative output node (Q-Node), (

In order to alternately output the upper common voltage VCOMH or the lower common voltage VCOML according to the voltage of the node, the positive and negative output nodes Q-Node, (

The common voltage output unit 34 prevents the voltage of -Node from changing from an initial level.

-Node)에 접속되며, 제2게이트출력전압(VGOUT2)의 단자가 상기 모스트랜지스터(M3),(M6)의 게이트에 공통접속되어 구성된다.The clock signal input unit 31 has the terminal of the second clock signal VCLK2 sequentially connected to the positive output node Q-Node through the diode type MOS transistor M1, M2 and the MOS transistor M3. And a terminal of the first clock signal VCLK1 is sequentially connected to the negative output node through the diode-type MOS transistors M4, M5, and MOS transistor M6.

A terminal of the second gate output voltage VGOUT2 is commonly connected to the gates of the MOS transistors M3 and M6.

-Node)의 사이에 콘덴서(C1-C4)가 직렬접속되고, 상기 콘덴서(C1),(C2)의 공통접속점이 모스트랜지스터(M10),(M12)를 각기 통해 중간접속노드(N1) 및 전원단자(VSS)에 공통접속됨과 아울러 그 공통접속점이 모스트랜지스터(M11),(M13)를 각기 통해 상기 콘덴서(C3),(C4)의 공통접속점에 접속되며, 게이트출력전압(VGOUT1),(VGOUT2)의 단자가 상기 모스트랜지스터(M12,M13),(M10,M11)의 게이트에 각각 공통접속되고, 게이트출력전압(VGOUT3)의 단자가 다이오드형 모스트랜지스터(M7)를 통한 후 게이트가 상기 정,부극성출력노드(Q-Node),(

-Node)에 각기 접속된 모스트랜지스터(M8),(M9)를 각기 통해 상기 콘덴서(C1,C2),(C3,C4)의 공통접속점에 각각 접속되어 구성된다.The output node voltage control unit 32 includes a positive output node (Q-Node) and a negative output node (

The capacitors C1-C4 are connected in series between the nodes, and the common connection point of the capacitors C1 and C2 is connected to the intermediate connection node N1 and the power supply through the MOS transistors M10 and M12, respectively. The common connection point is connected to the terminal VSS, and the common connection point is connected to the common connection point of the capacitors C3 and C4 through the MOS transistors M11 and M13, respectively, and the gate output voltages VGOUT1 and VGOUT2. Terminal) is commonly connected to the gates of the MOS transistors M12, M13, and M10 and M11, and the gate of the gate output voltage VGOUT3 passes through the diode-type MOS transistor M7. Negative output node (Q-Node), (

And are connected to common connection points of the capacitors C1, C2 and C3, C4, respectively, through the MOS transistors M8 and M9 connected to the -Node.

-Node)에 각기 접속되고, 상기 중간접속노드(N2)가 모스트랜지스터(M20,M21),(M18,M19)를 각기 통해서는 정,부극성출력노드(Q-Node),(

-Node)에 각각 접속되며, 상기 정,부극성출력노드(Q-Node),(

-Node)가 상기 모스트랜지스터(M18,M19),(M20,M21)의 게이트에 각기 접속되어 구성된다.In the initialization voltage supply unit 33, a terminal of the gate output voltage VGOUT1 is commonly connected to the gates of the MOS transistors M14 to M17, and the power supply terminal VSS is commonly connected to the intermediate connection node N2. The intermediate connection node N2 passes through the MOS transistors M15, M14, and M17 and M16, respectively, to the positive and negative output nodes (Q-Node), (

Are connected to each other, and the intermediate connection node N2 is connected to the positive and negative output nodes (Q-Node) through the MOS transistors M20, M21, and M18 and M19, respectively.

Each of the positive and negative output nodes (Q-Node), (

A node is connected to the gates of the MOS transistors M18, M19 and M20, M21, respectively.

-Node)가 모스트랜지스터(M22),(M23)의 게이트에 각기 접속되고, 그 모스트랜지스터(M22),(M23)의 게이트 사이에 콘덴서(C5)가 접속되며, 상,하위공통전압(VCOMH),(VCOML)의 단자가 상기 모스트랜지스터(M22),(M23)를 각기 통해 공통전압출력단자(VCOMOUT)에 공통접속되어 구성된다.The common voltage output unit 34 is the positive and negative output nodes (Q-Node), (

A node is connected to the gates of the MOS transistors M22 and M23, respectively, and a capacitor C5 is connected between the gates of the MOS transistors M22 and M23, and the upper and lower common voltages VCOMH are connected. A terminal of (VCOML) is configured to be commonly connected to the common voltage output terminal (VCOMOUT) through the MOS transistors (M22) and (M23), respectively.

Referring to Figure 4 attached to the operation of the present invention configured as described above in detail as follows.

In the initial state of the first frame, the terminal voltage VSS of 10V is transmitted to the intermediate connection node N1 of the capacitors C1-C4 connected in series. The intermediate connection node N1 is commonly connected to the drain and source common connection points of the MOS transistors M10, M11 and M12 and M13, which are connected in series and connected in parallel.

In this state, in the first frame, the first gate output voltage VGOUT1 is input to the low (-8V) as shown in FIG. 4A, and the MOS transistors M12-M17 are turned on. Accordingly, both ends of the capacitor C2 are connected through the MOS transistor M12, and both ends of the capacitor C3 are connected through the MOS transistor M13.

-Node) 및 상기 콘덴서(C4)의 타측 단자에 공통으로 전달된다.In this case, the terminal voltage VSS is commonly transmitted to one terminal of the positive output node Q-Node and the capacitor C1 through the MOS transistors M15 and M14. In addition, the terminal voltage (VSS) through the MOS transistors (M17, M16) through the negative output node (

Node) and the other terminal of the capacitor (C4) are commonly transmitted.

-Node)가 상기 10V로 초기화 된다.Therefore, when the first gate output voltage VGOUT1 is input low (-8V) in the first frame, each intermediate connection point of the series-connected capacitors C1-C4 and the two output nodes Q-Node, (

-Node) is initialized to the 10V.

Thereafter, the second gate output voltage VGOUT2 is input to a low (-8V) as shown in FIG. 4A (b), whereby the MOS transistor M3 is turned on. Accordingly, the second clock signal VCLK2 of -8V as shown in (f) of FIG. 4A sequentially passes through the diode-type MOS transistors M1, M2, and the MOS transistor M3. -Node).

Accordingly, as shown in (h) of FIG. 4A, a voltage of −8 V output from the positive output node Q-Node is transferred to the gate of the MOS transistor M22 of the output terminal, and the MOS transistor M22 is turned on. To start.

-Node)의 전압 레벨은 도 4a의 (i)와 같이 계속 10V로 유지된다. At this time, the MOS transistor M6 is also turned on by the second gate output voltage VGOUT2 of -8V, but since the first clock signal VCLK1 is 10V, the MOS transistors M4 and M5 are not turned on and thus are not turned on. Polarity output node

The node's voltage level is kept at 10V as shown in Fig. 4A (i).

Thereafter, the third gate output voltage VGOUT3 is input to a low (-8V) as shown in FIG. 4A, which is a capacitor C1 through the diode-type MOS transistor M7 and the MOS transistor M8. It is transmitted to the common connection point of (C2). Accordingly, the voltage at the common connection point of the capacitors C1 and C2 transitions from 10V to -8V. As a result, the voltage of the positive output node Q-Node changes from -8V to -26V as shown in (h) of FIG. 4A.

The MOS transistor M22 is completely turned on by the output voltage (-26V) from the positive output node Q-Node. Accordingly, the upper common voltage VCOMH as shown in FIG. 4A (d) is output to the common voltage output terminal VCOMOUT through the MOS transistor M22. That is, the upper common voltage VCOMH is output from the common voltage output terminal VCOMOUT. Here, it is assumed that the upper common voltage VCOMH is 5V.

However, when outputting the upper common voltage VCOMH through the above process, in general, the voltage of the positive output node Q-Node is not maintained at the desired initial level without surrounding parasitic capacitance or leakage. The current gradually increased as shown in FIG. 1.

-Node)의 사이에 연결한 콘덴서(C5)에 의하여, 주변의 기생 캐패시턴스나 누설전류의 영향을 받지 않게 되어 점진적으로 상승되지 않는다.However, in the present invention, the voltage of the positive output node (Q-Node) is positive, negative output node (Q-Node), (

By the capacitor C5 connected between -Node, it is not influenced by parasitic capacitance or leakage current and does not gradually rise.

Therefore, the upper common voltage VCOMH can be output in a stable form as shown in FIG. 4A.

On the other hand, when the second frame is started after the first frame, the first gate output voltage VGOUT1 is input to the low (-8V) as shown in (a) of FIG. 4b, whereby the MOS transistors M12 to M17. ) Is turned on. Accordingly, both ends of the capacitor C2 are connected through the MOS transistor M12, and both ends of the capacitor C3 are connected through the MOS transistor M13.

-Node) 및 상기 콘덴서(C4)의 타측 단자에 공통으로 전달된다.At this time, the terminal voltage VSS of 10V is commonly transmitted to the positive output node Q-Node and one terminal of the capacitor C1 through the MOS transistors M15 and M14. In addition, the terminal voltage (VSS) through the MOS transistor (M17, M16) through the negative output node (

Node) and the other terminal of the capacitor (C4) are commonly transmitted.

-Node)의 전압은 첫 번째 프레임에서와 같이 그대로 10V로 유지된다.Accordingly, when the first gate output voltage VGOUT1 is input low (-8V) in the second frame, the voltage of the positive output node Q-Node is -8V to 10V as shown in FIG. 4B (h). Transition to the negative output node (

Node's voltage is kept at 10V as it is in the first frame.

Thereafter, the second gate output voltage VGOUT2 is input to a low (-8V) as shown in (b) of FIG. 4B, whereby the MOS transistor M3 is turned on. Accordingly, the second clock signal VCLK2 of 10V, as shown in FIG. 4B, sequentially passes through the diode type transistors M1, M2, and M3, and the positive output node Q−. Node). However, since the potential of the positive output node Q-Node has already been supplied with a potential of 10 V through the above process, there is no change in the potential of the positive output node Q-Node as shown in FIG. 4B (h). .

-Node)에 전달된다. 이로 인하여, 상기 부극성출력노드(

-Node)의 전위가 도 4b의 (i)와 같이 10V에서 -8V로 천이된다.At this time, the MOS transistor M6 is also turned on by the second gate output voltage VGOUT2 of -8V. Accordingly, the first clock signal VCLK1 of -8V, as shown in (g) of FIG. 4B, passes through the diode-type MOS transistors M4 and M5 and the MOS transistor M6 to output the negative polarity output node.

-Node). As a result, the negative output node (

-Node) transitions from 10V to -8V as shown in Fig. 4B (i).

-Node)에서 출력되는 -8V의 전압이 출력단의 모스트랜지스터(M23)의 게이트에 전달되어 그 모스트랜지스터(M23)가 턴온되기 시작한다.Therefore, the negative output node (

A voltage of -8V output from -Node) is transferred to the gate of the MOS transistor M23 of the output terminal, and the MOS transistor M23 starts to turn on.

-Node)의 전압이 도 4b의 (i)와 같이 -8V에서 -26V로 천이된다.Thereafter, the third gate output voltage VGOUT3 is input to the low (-8V) as shown in (c) of FIG. 4B, which is a capacitor C3 through the diode-type MOS transistor M7 and the MOS transistor M9. It is transmitted to the common connection point of (C4). As a result, the voltage at the common connection point of the capacitors C3 and C4 transitions from 10V to -8V. As a result, the negative output node (

The voltage of -Node) changes from -8V to -26V as shown in (i) of FIG. 4B.

-Node)로부터의 출력전압(-26V)에 의해 상기 모스트랜지스터(M23)가 완전히 턴온된다. 이에 따라, 도 4b의 (e)와 같은 하위공통전압(VCOML)이 상기 모스트랜지스터(M23)를 통해 공통전압출력단자(VCOMOUT)로 출력된다. 즉, 상기 공통전압출력단자(VCOMOUT)에서 제로 레벨의 하위공통전압(VCOML)이 출력된다. 여기서, 하위공통전압(VCOML)은 0V인 것을 예로 하였다.And, the negative output node (

The MOS transistor M23 is completely turned on by the output voltage (-26V) from -Node. Accordingly, the lower common voltage VCOML as shown in (e) of FIG. 4B is output to the common voltage output terminal VCOMOUT through the MOS transistor M23. That is, the low common voltage VCOML of the zero level is output from the common voltage output terminal VCOMOUT. Here, the lower common voltage VCOML is assumed to be 0V.

-Node)의 전압이 목적한 초기 레벨로 그대로 유지되지 않고 주변의 기생 캐패시턴스나 누설전류로 인하여 도 1에서와 같이 점진적으로 상승되었다. However, when outputting the lower common voltage VCOML through the same process as described above, in general, the negative output node (

The voltage of -Node) is not maintained at the desired initial level but gradually increased as shown in FIG. 1 due to the surrounding parasitic capacitance or leakage current.

-Node)의 전압이 정,부극성출력노드(Q-Node),(

-Node)의 사이에 연결한 콘덴서(C5)에 의하여, 주변의 기생 캐패시턴스나 누설전류의 영향을 받지 않게 되어 점진적으로 상승되지 않는다.However, in the present invention, the negative output node (

-Node) voltage is positive, negative output node (Q-Node), (

By the capacitor C5 connected between -Node, it is not influenced by parasitic capacitance or leakage current and does not gradually rise.

Therefore, the lower common voltage VCOML can be output in a stable form as shown in FIG. 4B.

Instead of omitting the capacitor C5, the capacitor C5 may take the role of the capacitor C5 by increasing the capacity of the capacitors C1 and C4 of the output node voltage controller 32.

However, in this case, the capacities of the capacitors C1 and C4 must all be increased by the capacities of the capacitors C5. As a result, the total capacity of the capacitors is doubled as compared to using the capacitors C5. to be.

In addition, since the capacitors C1-C4 of the output node voltage controller 32 occupy about 30% of the total circuit area, the capacitors C1 and C4 are installed for the same reason as described above. It takes a lot of space.

-Node)의 전압이 초기 레벨을 안정되게 유지하는 것으로 밝혀졌다.When the capacitance of the capacitor C5 is 0.1PF or more as a result of the experiment, the positive and negative output nodes (Q-Node), (

It has been found that the voltage at -Node) keeps the initial level stable.

1 is a waveform diagram of an output node voltage according to the prior art.

2 is an exemplary view showing a screen failure due to a conventional common voltage floating phenomenon.

3 is a common voltage driving circuit diagram of a liquid crystal display device according to the present invention;

4A is a waveform diagram of each part of FIG. 3 in a first frame.

4B is a waveform diagram of each part of FIG. 3 in a second frame.

DESCRIPTION OF THE REFERENCE SYMBOLS

31: clock signal input unit 32: output node voltage control unit

33: initialization voltage supply unit 34: common voltage output unit

Claims (18)

A clock signal input unit comprising a plurality of transistors and configured to input first and second clock signals under control of a gate output voltage; An output node voltage control unit comprising a plurality of transistors and a capacitor, the output node voltage control unit changing a voltage of the positive and negative polarity output nodes by the first and second clock signals and the first and third gate output voltages; An initialization voltage supply unit comprising a plurality of transistors to supply an initialization voltage of the output node voltage control unit; Comprising a plurality of transistors and one capacitor, the output of the upper and lower common voltage alternately in accordance with the voltage of the positive and negative output node, the voltage of the positive and negative output node is changed by using the capacitor. A common voltage driving circuit of a liquid crystal display device, characterized by comprising a common voltage output unit for preventing. The common voltage driving circuit of a liquid crystal display device according to claim 1, wherein the transistor is a MOS transistor. The method of claim 1, The clock signal input unit, A first MOS transistor M1 diode-connected to the terminal of the second clock signal VCLK2;  A second MOS transistor (M2) having a drain connected to the source of the first MOS transistor (M1) and a gate connected to a terminal of the second clock signal (VCLK2); A third MOS transistor (M3) having a drain connected to the source of the second morph transistor (M2) and a source connected to the positive output node (Q-Node); A fourth MOS transistor M4 diode-connected to the terminal of the first clock signal VCLK1; A fifth MOS transistor M5 having a drain connected to the source of the fourth MOS transistor M4 and a gate connected to the terminal of the first clock signal VCLK1; A sixth MOS transistor (M6) having a drain connected to the source of the fifth MOS transistor (M5) and a source connected to the positive output node (Q-Node); And The negative output node (

A common voltage of the liquid crystal display device connected to the gate of the second gate output voltage VGOUT2, the terminal of the second gate output voltage VGOUT2 being connected to the gates of the third and sixth transistors M3 and M6. Driving circuit. 4. The common voltage driving circuit of claim 3, wherein the first and second clock signals VCLK1 and VCLK2 are opposite in phase. 4. The common voltage driving circuit of claim 3, wherein the first and second clock signals VCLK1 and VCLK2 have a low level of −8 V and a high level of 10 V. 5. The method of claim 1, The output node voltage control unit, A first intermediate connection node N1 connected to the ground voltage VSS terminal; Tenth and eleventh MOS transistors M10 and M11 having a gate connected to a terminal of a second gate output voltage VGOUT2 and a drain connected to the first intermediate connection node N1; Twelfth and thirteenth MOS transistors M12 and M13 having a gate connected to a terminal of a first gate output voltage VGOUT1 and a drain connected to the first intermediate connection node N1; And Positive, negative output node (Q-Node), (

First to fourth capacitors C1 to C4 connected in series between the nodes; The common connection point of the first and second capacitors C1 and C2 is connected to the sources of the tenth and twelfth MOS transistors M10 and M12, and the common connection point of the third and fourth capacitors C3 and C4. Is connected to the sources of the eleventh and thirteenth MOS transistors (M11, M13) A common voltage driving circuit of a liquid crystal display device characterized in that. The method according to claim 6, The first to third gate output voltages VGOUT1, VGOUT2, and VGOUT3 sequentially transition from a 'high' level to a 'low' level for a predetermined period of time. in. The method according to claim 6, And the first to third gate output voltages (VGOUT1), (VGOUT2), and (VGOUT3) are maintained at 10V or -8V. The method of claim 1, Initialization voltage supply unit, A second intermediate connection node N2 connected to the ground voltage VSS terminal; A gate is connected to the terminal of the first gate output voltage VGOUT1, and a drain is positive and negative output node (Q-Node), (

Fourteenth and sixteenth MOS transistors M14 and M16 connected to a node; A gate is connected to the terminal of the first gate output voltage VGOUT1, a drain is connected to the fourteenth and sixteenth MOS transistors M14 and M16, respectively, and a source is connected to the second intermediate connection node N2. The fifteenth and seventeenth MOS transistors M15 and M17; Gates are positive, negative output nodes (Q-Node), (

An eighteenth and twentieth MOS transistors M18 and M20 connected to a second node and a drain connected to the second intermediate connection node N2; And Gates are positive, negative output nodes (Q-Node), (

A drain is connected to the eighteenth and nineteenth MOS transistors M18 and M19, respectively, and a source is respectively a negative and positive output node (

Nodes), 19th and 21st morph transistors M19 and M21 connected to a connection to (Q-Node). Common voltage driving circuit of the liquid crystal display device comprising a. 10. The method of claim 9, The positive and negative output nodes (Q-Node), (

Node is sequentially shifted to 10V, -8V, -26V in synchronization with the first to third gate output voltage (VGOUT1), (VGOUT2), (VGOUT3). in. The method of claim 1, The common voltage output unit, The positive and negative output nodes (Q-Node), (

A fifth capacitor C5 connected between the nodes; A twenty-second MOS transistor (M22) having a gate connected to one electrode of the fifth capacitor (C5), a source connected to an upper common voltage (VCOMH) terminal, and a drain connected to a common voltage output terminal (VCOMOUT); And A 23rd MOS transistor M23 having a gate connected to the other electrode of the fifth capacitor C5, a source connected to a lower common voltage VCOML terminal, and a drain connected to a common voltage output terminal VCOMOUT. Common voltage driving circuit of the liquid crystal display device comprising a. 12. The common voltage driving circuit of claim 11, wherein the upper common voltage VCOMH is 5V. 12. The common voltage driving circuit of claim 11, wherein the lower common voltage (VCOML) is 0V. 12. The method of claim 11, The fifth capacitor C5 prevents the gate voltage of the twenty-second MOS transistor M22 from being changed when the fifth common capacitor V5 outputs the upper common voltage VCOMH through the twenty-second MOS transistor M22. Common voltage driving circuit of liquid crystal display device. 12. The method of claim 11, The capacitor C5 prevents the gate voltage of the twenty-third MOS transistor M23 from fluctuating when the lower common voltage VCOML is output through the twenty-third MOS transistor M23. Common voltage drive circuit of the device. 12. The method of claim 11, Twenty-second and twenty-third MOS transistors (M22), (M23) is a positive, negative output node (Q-Node), (

And a common voltage driving circuit of the liquid crystal display, which is alternately turned on by the voltage of -Node.  12. The common voltage driving circuit of claim 11, wherein the fifth capacitor (C5) is 0.1PF or more. The common voltage driving circuit of claim 1, wherein the liquid crystal display is a type in which a common voltage driving circuit is incorporated in the liquid crystal panel.

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