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CN101317268A - 具有emi屏蔽的叠层多芯片封装 - Google Patents

具有emi屏蔽的叠层多芯片封装 Download PDF

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CN101317268A
CN101317268A CNA2007800003883A CN200780000388A CN101317268A CN 101317268 A CN101317268 A CN 101317268A CN A2007800003883 A CNA2007800003883 A CN A2007800003883A CN 200780000388 A CN200780000388 A CN 200780000388A CN 101317268 A CN101317268 A CN 101317268A
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substrate
electronic component
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CN101317268B (zh
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梁立慧
陈有志
沈文龙
仲镇华
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Hong Kong Applied Science and Technology Research Institute ASTRI
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Abstract

一种具有EMI屏蔽元件的叠层多芯片封装，包括第一和第二基板，它们通过一个栅阵列金属连接结点，如球栅阵列，被安装在一起。每个基板有一个与之相连的导电层。电子元件被安装在第一和第二基板之间，并被一组金属连接结点包围住，金属连接结点也被电连接到此两个基板的导电层，以形成一个此元件的导电法拉第笼。

Description

具有EMI屏蔽的叠层多芯片封装
技术领域
本发明涉及多芯片封装，特别是叠层多芯片封装。更特别地，本发明涉及一种具有EMI屏蔽的叠层多芯片封装，以避免封装里的芯片受到电磁干扰、或对封装里的其它元件产生电磁干扰。
背景技术
电磁干扰(EMI)，也被称为射频干扰(RFI)，是由电磁辐射引起，在电子电路设计里是一个重要的考虑因素。电磁辐射是由带有变化电信号的电子电路和元件发出。有三种主要技术用来改善或消除EMI。第一种技术是将敏感元件与电磁辐射源物理隔离。第二种技术是使用旁路或去藕电容和过滤器将不要的干扰信号接地。最后，第三种技术是使用法拉第笼(Faraday cage)或阻隔外壳来屏蔽敏感元件或产生EMI的元件。
当前电子电路设计的重点是趋向尺寸更小且功率更大的设备。相当大量的工作都在多芯片封装领域进行，其中多个集成电路(IC)芯片被紧密封装在一个小封装内。在这种封装内，物理隔离敏感设备和电磁辐射源是不可行的，且去藕也仅是部分有效。所以，在这些多芯片封装内屏蔽是一种重要的解决方案。
在当前芯片封装内最流行的屏蔽方式是通过使用导电罩壳来密封敏感元件或产生EMI的元件。元件被安装在支撑基板的一个区域上，在支撑基板下有一个接地层，一个金属盒、或其它形状的罩壳，被安装在元件上面，将元件密封在导电外壳内。但是，这种类型的金属罩壳在基板表面上占用了相当大的空间，并往往不是很坚固，由于固定罩壳在基板上的焊接点上的交变应力(cyclic stress)，经常导致罩壳从基板表面移位。这同样阻碍了成型环氧树脂的流动，且如果电子设备所在环境条件突然发生变化，水蒸气可能在罩壳内积聚。
发明概述
所以，本发明的目的是提供一种具有EMI屏蔽空间的叠层多芯片封装，该屏蔽空间用于在封装内必须被隔离的敏感元件和产生EMI的元件。
鉴于前述，在此披露一种具有EMI屏蔽空间的叠层多芯片封装，其包括第一基板，在第一基板的绝缘层之间有第一接地层；一个电子元件，被安装在第一基板层的第一面上；和第二基板，在第二基板的绝缘层中间有第二接地层，其中通过栅阵列的金属连接结点，第一基板被安装在第二基板上，电子元件位于基板之间，且至少一组金属连接结点包围住电子元件，并被电连接到第一接地层和第二接地层。
优选地，电子元件被密封在与第一基板和第二基板接触的树脂外壳内。
优选地，电子元件是一个集成电路芯片，且芯片已经变薄到一个5到7密尔之间的厚度。
优选地，通过第一基板和第二基板里的多个相应电镀通孔，该组金属连接结点被电连接到第一接地层和第二接地层。
优选地，金属连接结点是焊接球。
通常，在此披露的一种叠层电子元件封装，包括第一基板、安装在第一基板上的第二基板、位于基板之间的一个电子元件、与第一基板相连的第一导电层、与第二基板相连的第二导电层、和多个包围住该电子元件并与第一和第二导电层互连的导电结点。
从以下的描述，本发明将变得更加清楚。
附图说明
现通过例子并结合附图描述本发明的典型实施例，其中：
图1是依照本发明的一个具有EMI屏蔽的叠层多芯片封装的典型实施例的横截面图，
图2是图1叠层多芯片封装的第二截面图，
图3是图2区域III的截面图，
图4是EMI屏蔽外壳的切开的透视图，
图5描述一个典型球栅阵列的覆盖区，
图6描述用于典型实施例的球栅阵列覆盖区，
图7描述典型实施例的第一变化，和
图8描述典型实施例的第二变化。
具体实施例描述
在本说明书和权利要求里，1密尔(mil)＝25.4微米(1×10-6m)。
通常，本发明是一个叠层多芯片封装，其具有第一和第二基板，第一和第二基板通过栅格阵列的金属连接结点，如焊球栅阵列，被安装在一起。每个基板有一个接地层，其处于基板绝缘层之间。一个敏感元件或产生EMI的元件被安装在第一和第二基板之间，并被一组金属连接结点围住，金属连接结点也被电连接到此两个基板的接地层，以形成一个此元件的导电法拉第笼。
在附图里，描述了本发明在多芯片集成封装里实施的一个典型实施例，多芯片集成封装具有射频(RF)和数字集成电路(IC)芯片，其被一起封装在一个叠层基板排列里。这种排列经常被称为叠层多芯片模块(MCM)。但是，这个典型的例子不是意在限制本发明适用的范围或功能。本领域有经验的技术人员将会明白，本发明也可以适用于其它类型的叠层基板排列，比如其中期望隔离一个或多个元件以免噪音干扰或避免产生噪音干扰到封装的其它部分。而且，典型实施例是一个单层封装，只具有一个支撑基板，其被连接到系统基板或母板。有经验的技术人员将会明白，本发明可以等同地应用到多叠层基板，并可以被应用在与系统基板分离的两个或多个互连基板之间。一种特别的IC芯片构造也被描述用来说明本发明，这也不是意在限制本发明的使用范围或功能。其它芯片类型、元件和/或其组合也可以与本发明一起使用。本发明通常应用于任何敏感电子元件或产生EMI的元件，它们必须被隔离在一个分层的基板封装内。
参考附图，在典型实施例里，MCM 1被安装在主系统板或母板2上，通过球栅阵列(BGA)3相互连接。MCM 1包括一个支撑基板10，其有两个数字IC芯片11、12安装在其第一面，和一个RF芯片13安装在其第二面。数字IC芯片11、12是一个存储芯片和一个逻辑芯片，用来控制RF模块1。RF芯片13必须足够薄以便被安装在RF模块1和主板2之间的BGA 3支起空间33内。一个典型的RF芯片是15-25密尔厚：对一个稳固的BGA支起距离而言太厚了。但是，芯片能够变薄到5-7密尔之间。在IC技术和制造领域内变薄芯片是惯用方法。，RF模块支撑基板10在其一个或多个表面上有印刷电路，也有焊盘并使用互连线14来安装芯片11、12、13到支撑基板10上。数字IC和RF芯片11、12、13通过基板上的电镀通孔(过孔)而互相连接。对本发明而言，印刷电路和芯片互连过孔不是决定性的，所以在此不作详细说明。
RF模块支撑基板10有一个或多个导电接地层15位于绝缘层16、17之间，绝缘层由环氧树脂或其它合适的非导电材料制成。这种类型的基板在印刷电路板技术和制造领域是惯常使用的。模块基板10通过球栅阵列(BGA)3被安装和连接到系统基板20上。在RF模块基板10的第二面上有许多以栅格样式排列的焊接球30、31围住RF芯片13。一个典型的BGA栅格样式如图5所示。参照图6，依照本发明，在BGA 3里，形成RF芯片空间32的周边的最里面的焊接球31(如图6实线所示)是电连接到在模块基板10内的接地层15的。通过基板10第二面和接地层15之间的接地层过孔34，提供这种电连接。接地层过孔34与模块基板10第二面上的过孔焊盘35或凸点下金属(UBM)焊头连接，它们又与内周边的焊接球31附着在一起。
通过相应的栅格样式排列的电焊盘21、37或UBM点，承受RF模块1的BGA 3的焊接球30、31，从而使得RF模块1连接在系统基板20的表面。在焊盘21、37栅格的中央，是一个对应的RF芯片空间。系统基板20也具有一个或多个导电接地层22位于绝缘层23、24之间。形成系统基板RF芯片空间周边的最里面的焊盘37，和模块支撑基板10上的内边界的焊接球31一样，被同样电连接到系统基板接地层22。即，接地层过孔36是在系统基板的内边界焊盘37和接地层22之间。所以，当RF模块1被安装在系统基板2上时，通过球栅阵列BGA 3，就形成了关于RF芯片13的法拉第笼，用于芯片的EMI屏蔽。法拉第笼包括RF模块基板10和系统基板的上接地层和下接地层15、22，上下接地层又通过多个接地层过孔34、36和内边界的BGA焊接球31在被屏蔽的芯片空间32周围互连。BGA3的其余焊接球30(图6虚线所示)提供RF模块1和系统2之间的电连接。RF模块1和系统2之间的电连接与模块基板10和系统基板20的接地层15、22是电隔离的。
法拉第笼在RF芯片13周围提供一个接地导电外壳，以避免其受到由邻近数字芯片11、12和变化的电子信号引起的电子和EMI干扰。尽管在形成笼边缘的内边界的焊接球31之间有空隙，但是这基本上不影响笼的屏蔽效果，因为电磁波不会穿透尺寸小于其波长的过孔太远。大多数现代电子设备，如手机、无线网络适配器和电信设备，在从300MHz到10GHz的超高频(UHF)频道上运作。这是一个1米到100毫米的波长范围。通常，焊接球31之间的空隙仅有几百微米，远远小于EMI波的波长，其通常不会穿过焊接球31之间的空隙。
为了使设计更加稳固，避免使用中的震动，芯片和互连线都被塑封在环氧树脂罩壳40、41里。这在电路板和MCM组件里是惯常使用的，这些方法都是本领域技术人员所熟知的。但是，在本发明里，被屏蔽的RF芯片13或其它元件，位于基板10、20之间的BGA支起空间33里。所以，密封RF芯片13的环氧树脂铸件40的厚度，需要被控制和调整以作为一个用于BGA支起空间33的隔离物。RF芯片13的树脂铸件40与系统基板20接触，以协助支撑模块基板10，防止BGA焊接球30、31在再流热过程期间破裂。在焊膏印刷过程期间，可以增加在每个铸造焊盘上的焊膏量，以增强焊接球高度和基板翘曲的变化容差。
应该理解，对本领域技术人员显而易见的修改和替换不能被认为超出本发明的范围。例如，BGA互连应用在叠层基板之间，但是，显而易见的是，技术人员可以使用针脚栅阵列(PGA)、引脚栅阵列(LGA)或其它栅类型互连系统来包围互连基板之间屏蔽空间。
在典型实施例里，屏蔽笼(即法拉第笼)的上和下导电表面，是由基板的接地层15、22提供。但是，应该理解，这些导电层不需要延伸到基板的整个区域，也不需要在基板的层之间。参照图7，在其中一个基板(例如系统基板20)的一个表面上可以有一个大导电层或焊盘25，用来承接内边界的焊接球31，并形成屏蔽笼的一边。另外，参照图9，在安装有屏蔽电子元件的基板的另一面，可以有一个类似的导电层或焊盘26，并通过电镀通孔27而连接到焊接球31。

Claims (14)

1.一种具有EMI屏蔽空间的叠层多芯片封装，包括：
第一基板，在第一基板的绝缘层之间有第一接地层，
一个电子元件，安装在第一基板的第一面，
第二基板，在第二基板的绝缘层之间有第二接地层，其中通过栅阵列金属连接结点，第一基板被安装在第二基板上，该电子元件位于基板之间，且至少一组包围该电子元件的金属连接结点被电连接到第一接地层和第二接地层。
2.根据权利要求1所述的叠层多芯片封装，其中电子元件被密封在一个树脂罩壳内，该罩壳与第一基板和第二基板接触。
3.根据权利要求1所述的叠层多芯片封装，其中电子元件是一个集成电路芯片。
4.根据权利要求3所述的叠层多芯片封装，其中集成电路芯片已经变薄到5到7密尔之间的厚度。
5.根据权利要求1所述的叠层多芯片封装，其中该组金属连接结点分别通过第一基板和第二基板里的多个电镀通孔，而被电连接到第一接地层和第二接地层。
6.根据权利要求1所述的叠层多芯片封装，其中金属连接结点是焊接球。
7.一种叠层电子元件封装，包括：
第一基板，
第二基板，被安装在第一基板上，
一个电子元件，位于基板之间，
第一导电层，与第一基板相连，
第二导电层，与第二基板相连，和
多个导电结点，包围住电子元件，并与第一和第二导电层互连。
8.根据权利要求7所述的叠层电子元件封装，其中第一和第二基板机械支撑并电连接多个电子元件。
9.根据权利要求7所述的叠层电子元件封装，其中多个导电结点是部分球栅阵列，其将第二基板安装到第一基板上。
10.根据权利要求7所述的叠层电子元件封装，其中导电结点通过电镀通孔，被互连到第一和第二导电层中的至少一个导电层。
11.根据权利要求7所述的叠层电子元件封装，其中电子元件被密封在树脂罩壳内，该罩壳与第一基板和第二基板接触。
12.根据权利要求7所述的叠层电子元件封装，其中至少一个导电层是一个位于其中一个基板的一个表面上的导电焊盘。
13.根据权利要求12所述的叠层电子元件封装，其中导电焊盘是位于其中一个基板的一个与电子元件相反的表面上。
14.一种叠层电子元件封装，包括：
一个基板，有一个导电层，
一个电子元件，被安装在该基板的一个表面上，
多个导电结点，用来将该基板安装在第二基板上，所述结点包围住该电子元件，并与该导电层互连。
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