CN101312174A - Circuit assembly - Google Patents

Abstract

The invention relates to a circuit component structure, which comprises a first semiconductor substrate, a second semiconductor substrate and a third semiconductor substrate, wherein the first semiconductor substrate is provided with at least one first metal connecting pad; a first passivation layer on the first semiconductor substrate and having at least one first opening exposing the first metal pad; the first metal layer is positioned on the first protective layer, is connected with the first metal bonding pad through the first opening, and is provided with a first routing bonding pad and a second routing bonding pad; the second semiconductor substrate is positioned on the first semiconductor substrate and exposes at least one side edge of the first semiconductor substrate, the first routing connecting pad and the second routing connecting pad, the second semiconductor substrate is provided with a second metal connecting pad, a second protective layer is positioned on the second semiconductor substrate and is provided with at least one second opening to expose the second metal connecting pad; a first wire bonding wire located on the first wire bonding pad and connected to a first external circuit; and a second routing wire which is positioned on the second routing bonding pad and connected to the second metal bonding pad of the second semiconductor substrate.

Description

Line components

technical field

The invention relates to a circuit component structure, in particular to a chip structure capable of performing a double-wire manufacturing process on the chip.

Background technique

In recent years, with the continuous maturity and development of semiconductor process technology, various high-efficiency electronic products have been continuously introduced, and the integration of integrated circuit (Integrated Circuit, IC) components has also been continuously improved. In the packaging process of integrated circuit components, integrated circuit packaging (IC packaging) plays a very important role, and the type of integrated circuit packaging can be roughly divided into wire bonding package (Wire Bonding Package, WB), tape automatic bonding package ( Tape Automatic Bonding (TAB) and flip chip bonding (FlipChip, FC) and other types, and each package has its own particularity and application fields.

However, when the size of integrated circuits is further miniaturized, when the metal connection structure on the integrated circuit is connected to other circuits or systems, it will gradually become an adverse impact on circuit performance, especially the parasitic capacitance of the metal connection structure When the resistance and resistance increase, the performance of the chip will be seriously reduced. For example, when the parasitic capacitance (parasitic capacitance) and resistance of the metal interconnection increase, it will mean that the performance of the chip will decrease. Among them, the most worthy of concern are the voltage drop along the power bus (power bus) and the ground bus (ground bus) (voltage drop), and the resistor capacitor delay (RC delay) of the critical signal path. In order to reduce the resistance, if wide metal lines are used, the parasitic capacitance of these wide metal lines will increase.

In view of this, the present invention aims at the above-mentioned problems, and proposes a manufacturing process and structure of a circuit assembly, which effectively overcomes the troubles of the prior art.

Contents of the invention

The main purpose of the present invention is to provide a circuit assembly, which utilizes reconfigurable lines (RDL) to allow chips to overlap with the largest overlapping area during stacking, thereby reducing the overall volume.

Another object of the present invention is to provide a circuit assembly, which uses polymer bumps to replace existing metal bumps, so as to greatly reduce material costs.

In order to achieve the above object, the technical scheme adopted in the present invention comprises:

A circuit assembly, characterized in that it includes: a first semiconductor substrate, the first semiconductor substrate has at least one first metal pad; a first protective layer, located on the first semiconductor substrate, the The first protection layer has at least one opening exposing the first metal pad; a first metal layer is located on the first protection layer and electrically connected to the first metal pad, so The first metal layer has a first bonding pad and a second bonding pad; a first bonding wire is located on the first bonding pad and connected to a first external circuit; and a The second bonding wire is located on the second bonding pad and connected to a second external circuit.

In order to achieve the above object, the technical scheme adopted in the present invention comprises:

A circuit assembly, characterized in that it comprises: a first semiconductor substrate, a first protection layer is located on the first semiconductor substrate, at least one first opening of the first protection layer exposes the A first pad of the first semiconductor substrate, and a first metal layer located on the first protection layer and connected to the first pad through the first opening, the first metal layer including a plurality of first bonding pads; a second semiconductor substrate located on the first semiconductor substrate and exposing at least one side of the first semiconductor substrate and the first bonding pads, And a second protective layer is located on the second semiconductor substrate, at least one second opening of the second protective layer exposes a second pad of the second semiconductor substrate, and a second metal layer is located on the second protective layer and connected to the second pad through the second opening, the second metal layer includes a plurality of second bonding pads; a third semiconductor substrate, Located on the second semiconductor substrate and exposing at least one side of the second semiconductor substrate and the second bonding pad, and a third protection layer is located on the third semiconductor substrate, At least one third opening of the third protection layer exposes a third pad of the third semiconductor substrate, and a third metal layer is located on the third protection layer and passes through the first Three openings are connected to the third pads, the third metal layer includes several third bonding pads; a fourth semiconductor substrate, located on the third semiconductor substrate and exposing the first At least one side of three semiconductor substrates and the third bonding pad, and a fourth protection layer is located on the fourth semiconductor substrate, at least one fourth opening of the fourth protection layer exposes the A fourth pad of the fourth semiconductor substrate, and a fourth metal layer is located on the fourth protective layer and connected to the fourth pad through the fourth opening, the fourth The metal layer includes several fourth bonding pads; several bonding wires, located at the first bonding pad, the second bonding pad, the third bonding pad and the On the fourth bonding pad, the first bonding pad and the second bonding pad, the second bonding pad and the third bonding pad, The third bonding pad and the fourth bonding pad are connected to each other through the bonding wire; and an external circuit is connected to the first bonding wire through the bonding wire On at least one of the bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad.

Compared with the prior art, the invention has the beneficial effects of: not only the overall volume is reduced, but also the material cost is reduced.

Description of drawings

Fig. 1a to Fig. 1d are the schematic diagrams of the formation of fine wire structure and protective layer in the present invention;

2a to 2p are schematic diagrams of the first implementation of the first embodiment of the present invention;

3a to 3m are schematic diagrams of a second implementation of the first embodiment of the present invention;

4a to 4c are schematic diagrams of a third implementation of the first embodiment of the present invention;

5a to 5k are schematic diagrams of the first implementation of the second embodiment of the present invention;

6a to 6j are schematic diagrams of a second implementation of the second embodiment of the present invention;

7a to 7b are schematic diagrams of the third embodiment of the second embodiment of the present invention;

8a to 8k are schematic diagrams of the fourth embodiment of the second embodiment of the present invention;

9a to 9g are schematic diagrams of the fifth embodiment of the second embodiment of the present invention;

10a to 10h are schematic views of the sixth implementation of the second embodiment of the present invention.

Description of reference numerals: 10-substrate; 12-component layer; 14-metal oxide semiconductor transistor; 16-source; 18-drain; 20-gate; 22-thin line structure; 24-thin line layer; 26- Fine line dielectric layer; 28-opening; 30-conductive plug; 32-pad; 34-protective layer; 36-opening; 38-adhesion barrier layer; 40-seed layer; 42-photoresist layer; 42a-light 44-metal layer; 44a-wire pad; 44b-wire pad; 46-polymer layer; 46a-opening; 48-semiconductor chip; 49-integrated circuit; 48a-first semiconductor chip; 48b-second semiconductor chip; 50-adhesive; 52-first external circuit; 52a-connection pad; 54-second external circuit; 54a-connection pad; 56-wire; 58-polymer protection layer; 59 -integrated circuit; 60-polymer layer; 60a-opening; 62-adhesion barrier layer; 64-seed layer; 66-photoresist layer; 66a-photoresist layer opening; 68-metal layer; 68a-bonding pad ; 68b-wire pad; 70-polymer layer; 70a-opening; 72-semiconductor chip; 72a-first semiconductor chip; 72b-second semiconductor chip; 74-adhesive; 76-first external circuit; 76a -connection pad; 78-second external circuit; 78a-connection pad; 80-polymer protective layer; 82a-semiconductor chip; 82b-semiconductor chip; 82c-semiconductor chip; 82d-semiconductor chip; 84-first external Circuit board; 86-second external circuit; 88a-wiring pad; 88b-wiring pad; 90a-wiring pad; 90b-wiring pad; 92a-wiring pad; 92b-wiring pad Pad; 94a-wiring pad; 94b-wiring pad; 84a-connecting pad; 86a-connecting pad; 96-wire; 97-polymer protective layer; 112-polymer layer; 112a-opening; 114 -polymer bump; 116-adhesion/barrier layer; 118-seed layer; 120-photoresist layer; 120a-photoresist layer opening; 122-metal layer; 124-bonding pad; 126-semiconductor chip; 128- External circuit; 129-junction metal layer; 130-anisotropic conductive adhesive; 132-tin layer; 134-tin gold alloy layer; 32'-pad; 120b-photoresist layer opening; External substrate; 140-bonding pad; 142-bonding metal layer; 144-packaging layer; 146-wire; 147-solder ball; 148-polymer block; 150-polymer layer; Metal layer; 156-metal layer; 158-photoresist layer; 158a-photoresist layer opening; 160-metal layer.

Detailed ways

The present invention is a semiconductor circuit assembly structure and its manufacturing process, wherein several different types of semiconductor circuit assembly structures and their manufacturing processes are disclosed in this invention, each of the disclosed methods and structures is constructed on a semiconductor substrate, and A fine interconnect structure and a protective layer are further provided on the semiconductor substrate. Therefore, the structure and formation method of the semiconductor substrate, the fine interconnect structure and the protective layer are explained first, and then various embodiments of the present invention are explained. The word "above" in the present invention means to be on something and in contact with it, or to be on something but not in contact with it, and the word "upper" in the present invention means to be on something on and in contact with something.

Semiconductor substrate:

Referring to Fig. 1a, a substrate 10 is provided. The substrate 10 is usually a silicon substrate, which can be an intrinsic silicon substrate, a p-type silicon substrate or an n-type silicon substrate. base. For high-performance chips, silicon-germanium (SiGe) or silicon-on-insulator

(Silicon-On-Insulator, SOI) substrate. Wherein, the silicon germanium substrate includes a silicon germanium epitaxial layer (epitaxial layer) on the surface of the silicon substrate, and the silicon substrate on the insulating layer includes an insulating layer (preferably silicon oxide) on a silicon substrate, and a An epitaxial layer of silicon or silicon germanium is formed on the insulating layer.

Then please refer to shown in FIG. 1 b, a component layer (device layer) 12 is formed on this substrate 10, and this component layer 12 generally includes at least one semiconductor component (semiconductor device), and this component layer 12 is in the surface of the substrate 10 and/or on the surface. Wherein, the semiconductor component may be a MOS transistor (MOS transistor) 14, such as an N-type MOS transistor (NMOS transistor, n-channel MOS transistor) or a P-type metal-oxide-semiconductor transistor (PMOS transistor, p-channel MOS transistor) , and this metal-oxide-semiconductor transistor 14 includes a source 16, a drain 18 and a gate 20, and the gate 20 is usually a polysilicon (polysilicon), a polycrystalline tungsten polycide (tungsten polycide), a tungsten silicide (tungsten silicide), a titanium silicide (titanium silicide), a cobalt silicon (cobalt silicide) or a silicide gate (salicide gate). In addition, the semiconductor component can also be bipolar transistor, diffused metal oxide semiconductor (Diffused MOS, DMOS), lateral diffused metal oxide semiconductor (Lateral Diffused MOS, LDMOS), charge coupled device (Charged-Coupled Device , CCD), complementary metal oxide semiconductor (CMOS) sensing components, photo-sensitive diodes (photo-sensitive diode), resistance components (formed due to the polysilicon layer or diffusion region in the silicon substrate). Various circuits can be formed using these semiconductor components, such as complementary metal oxide semiconductor (CMOS) circuits, N-type metal oxide semiconductor circuits, P-type metal oxide semiconductor circuits, bicarrier complementary metal oxide semiconductor (BiC MOS) circuits , Complementary metal oxide semiconductor sensor circuit, diffused metal oxide semiconductor power supply circuit, lateral diffused metal oxide semiconductor circuit, etc. In addition, the component layer 12 also includes a NOR gate or a NAND gate, and may also be an inverter, an AND gate, or an OR gate ( OR gate), a static random access memory unit (SRAM cell), a dynamic random access memory unit (DRAM cell), a non-volatile memory unit (non-volatile memory cell), a flash memory unit (flash memory cell) , a programmable read-only memory unit (EPROM cell), a read-only memory unit (ROM cell), a magnetic random access memory (magnetic RAM, MRAM) unit, a sense amplifier (sense amplifier), a transport Amplifier (operational amplifier, Op Amp, OPA), an adder (adder), a multiplexer (multiplexer), a duplexer (diplexer), a multiplier (multiplier), an analog/digital converter (A/D converter), a digital/analog converter (D/A converter), a complementary metal oxide semiconductor sensing element unit (CMOS sensorcell), a photo-sensitive diode (photo-sensitive diode), a complementary metal oxide semiconductor, a bipolar complementary metal oxide semiconductor, a bipolar circuit or an analog circuit.

Detailed online structure:

1c, a fine-line structure 22 is formed on the substrate 10 and the component layer 12, and the fine-line structure 22 includes several fine-line conductivity layers (fine-line conductivity layer) 24, several fine-line dielectric layers ( fine-line dielectric layer) 26 and several openings 28 in the thin-line dielectric layer 26, and conductive plugs (fine-line via plug) 30 in the opening 28, and at least one fine-line via plug is arranged on the topmost thin-line layer 24 regions, which are defined as pads 32 .

In this embodiment, the thin circuit layer 24 is selected from aluminum metal material and copper metal material, or more specifically, an aluminum layer formed by sputtering or a copper layer formed by damascene. Therefore, the fine line layer 24 can be: (1) all the thin line layers 24 are aluminum layers; (2) all the thin line layers 24 are copper layers; (3) the bottom thin line layers 24 are aluminum layers, The thin circuit layer 24 on the top layer is a copper layer; or (4) the thin circuit layer 24 on the bottom layer is a copper layer, and the thin circuit layer 24 on the top layer is an aluminum layer.

In addition, the thickness of each thin circuit layer 24 is between 0.05 micron (μm) and 2 microns, and preferably between 0.2 micron and 1 micron. If the thin circuit layer 24 is a circuit, The horizontal design standard (width) is between 20 nanometers (nano-meter) and 15 micrometers, and preferably between 20 nanometers and 2 micrometers.

Firstly, explain that the thin line layer 24 is an aluminum layer. The aluminum layer of the thin line layer 24 is usually formed by physical vapor deposition (Physical Vapor Deposition, PVD), for example, by sputtering (sputtering), and then deposited A photoresist layer with a thickness between 0.1 micron and 4 microns (preferably between 0.3 micron and 2 microns) is used to pattern the aluminum layer, and then perform a wet etching or wet etching on the aluminum layer - Dry etching, preferably dry plasma etching (usually including fluorine plasma). In addition, an adhesion/barrier layer (adhesion/barrier layer) can be selectively formed under the aluminum layer, wherein the adhesion/barrier layer can be titanium, titanium-tungsten alloy, titanium nitride or a composite layer formed of the above materials ; On the aluminum layer, an anti-reflection layer (such as titanium nitride) can also be selectively formed. In addition, the opening 28 can be selectively filled by chemical vapor deposition (CVD) tungsten metal, and then the tungsten metal layer is polished by chemical mechanical polishing (CMP) to form the conductive plug 30. .

Then explain that the thin line layer 24 is a copper layer. The copper layer of the thin line layer 24 is usually formed by electroplating and a damascene process, which is described as follows: (1) Deposit a copper diffusion barrier layer (such as thickness Oxynitride layer or nitride layer between 0.05 micron and 0.25 micron); (2) using plasma-assisted chemical vapor deposition (plasma enhanced CVD, PECVD), spin-on coating (spin-on coating) or high density A thin line dielectric layer 26 with a thickness between 0.1 micron and 2.5 micron is deposited by plasma chemical vapor deposition (High Density Plasma CVD, HDPCVD), wherein the thin line dielectric layer 26 is between 0.3 micron and 2.5 micron A thickness between 1.5 microns is preferred; (3) a photoresist layer with a deposition thickness between 0.1 microns and 4 microns is used to pattern the fine-line dielectric layer 26, wherein the thickness of the photoresist layer is again between 0.1 micron and 4 microns. It is preferably between 0.3 microns and 2 microns, and then the photoresist layer is exposed and developed to form several openings and/or several trenches in the photoresist layer, and then the photoresist layer is removed; (4) Deposit an adhesion/barrier layer and a seed layer by sputtering or chemical vapor deposition. Wherein, the adhesion/barrier layer includes tantalum, tantalum nitride, titanium nitride, titanium or titanium-tungsten alloy, or a composite layer formed of the above materials. In addition, the seed layer is usually a copper layer, and the copper layer can be formed by sputtering copper metal, chemical vapor deposition of copper metal, or first depositing a copper metal by chemical vapor phase, and then sputtering a copper metal. (5) Electroplating a copper layer with a thickness between 0.05 micron and 2 microns on the seed layer, wherein a copper layer with an electroplated copper layer thickness between 0.2 micron and 1 micron is preferred; (6) Remove the copper layer, seed layer and adhesion/barrier layer that are not in the openings or trenches of the thin-line dielectric layer 26 by grinding (preferably chemical mechanical grinding) the wafer, until exposed The fine line dielectric layer 26 under the adhesion/barrier layer. After chemical mechanical polishing, only the metal in the opening or trench remains, and the remaining metal is used as a metal conductor (circuit or plane) or a conductive plug 30 (connecting two adjacent thin circuit layers 24 ). In addition, a double-damascene process can also be used to simultaneously form the conductive plug 30 and the metal lines or metal planes in one electroplating process and one chemical mechanical polishing process. Two photolithography processes and two electroplating processes are applicable to the dual damascene process. The dual damascene process adds more process steps of depositing and patterning another dielectric layer between the step (3) of patterning a dielectric layer and the step (4) of depositing a metal layer in the above single damascene process.

Next, the fine-line dielectric layer 26 will be described. The thin-line dielectric layer 26 is formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, or spin-on. The material of the thin line dielectric layer 26 includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (PECVDTEOS) formed by plasma-assisted chemical vapor deposition, Spin-on-glass (SOG, silicon oxide or siloxane-based), fluorosilicate glass (Fluorinated SilicateGlass, FSG) or a low dielectric constant (low-K) material, such as black diamond film (Black Diamond, which is Applied Materials Products, the company translated as Applied Materials), ULKCORAL (a product of Novellus) or SiLK (IBM) low dielectric constant dielectric material. Silicon oxide formed by plasma-assisted chemical vapor deposition, tetraethoxysilane formed by plasma-assisted chemical vapor deposition, or oxide formed by high-density plasma has a dielectric constant K between 3.5 and 4.5; Fluoro-silicate glass formed by plasma-assisted chemical vapor deposition or high-density plasma has a dielectric constant value between 3.0 and 3.5, while low-k dielectric materials have a dielectric constant value between 1.5 Dielectric constant values between to 3.5. Low-k dielectric materials, such as black diamond films, are porous and contain hydrogen, carbon, silicon, and oxygen, and their molecular formula is HwCxSiyOz. The fine-line dielectric layer 26 typically includes inorganic materials to achieve a thickness greater than 2 microns. The thickness of each fine-line dielectric layer 26 is between 0.05 microns and 2 microns. In addition, the openings 28 in the thin line dielectric layer 26 are formed by etching the patterned photoresist layer by wet etching or dry etching, wherein the preferred etching method is dry etching. Types of dry etching include fluorine plasma.

The protective layer:

Referring to FIG. 1 c , a protection layer 34 is formed on the fine line structure 22 , and the protection layer 34 plays a very important role in the present invention. The protective layer 34 is an important component in the integrated circuit industry, as described in Volume 2 of "Silicon Processing in the VLSI era" written by S.Wolf in 1990 and issued by Lattice Press, the protective layer 34 is in the integrated circuit In-process is defined as the final layer and deposited on the overall top surface of the wafer. The protective layer 34 is an insulating and protective layer that can prevent mechanical and chemical damage during assembly and packaging. In addition to preventing mechanical scratches, the protective layer 34 can also prevent mobile ions, such as sodium ions, and transition metals, such as gold and copper, from penetrating into the underlying integrated circuit. circuit components. In addition, the protection layer 34 can also protect the underlying components and connection lines (fine-line metal structure and thin-line dielectric layer) from moisture intrusion.

The protective layer 34 usually includes a silicon nitride (silicon nitride) layer and/or a silicon oxynitride (siliconoxynitride) layer, and its thickness is between 0.2 microns to 1.5 microns, and the thickness is between 0.3 microns to 1.0 microns. The thickness between is better. Other materials used in the protective layer 300 include silicon oxide formed by plasma-assisted chemical vapor deposition, plasma-enhanced tetraethylorthosilicate (PETEOS) oxide, and phosphosilicate glass. (phosphor silicate glass, PSG), borophospho silicate glass (BPSG), oxide formed by high density plasma (HDP). Next, describe some examples that the protective layer 34 is composed of composite layers, the order from the bottom to the top is: (1) the thickness is between 0.1 micron and 1.0 micron (the preferred thickness is between 0.3 micron and 0.7 micron) oxide/silicon nitride with a thickness between 0.25 microns and 1.2 microns (preferably between 0.35 microns and 1.0 microns), this type of protective layer 34 is usually covered on a metal formed of aluminum On the connection line, the metal connection line formed of aluminum usually includes the process of sputtering aluminum and etching aluminum; Nitride/Oxide between 0.2 micron and 1.2 micron thick (preferably between 0.1 micron and 0.2 micron thick)/Oxide between 0.2 micron and 1.2 micron thick (preferably between 0.3 micron and 0.5 micron thick) micron)/oxide with a thickness between 0.2 micron and 1.2 micron (preferably between 0.3 micron and 0.6 micron), this type of protective layer 34 is usually covered with copper On the metal connection circuit, the metal connection circuit formed by copper usually includes electroplating, chemical mechanical polishing and damascene processes. In addition, the oxide layer in the above two examples may be silicon oxide formed by plasma-assisted chemical vapor deposition, oxide of plasma-enhanced tetraethyl orthosilicate (Plasma-enhanced tetraethyl orthosilicate, PETEOS), Oxide formed by high-density plasma. The above content is applicable to all embodiments of the present invention.

Please refer to FIG. 1d, at least one opening 36 is formed in the protection layer 34, and the opening 36 of the protection layer 34 is formed by wet etching or dry etching, wherein dry etching is the preferred method. In addition, the size of the opening 36 is between 0.1 micron and 200 microns, preferably between 1 micron and 100 microns or between 5 microns and 30 microns, and the shape of the opening 36 can be circular, Square, rectangular or polygonal, so the size of the above-mentioned opening 36 refers to the diameter of the circle, the side length of the square, the longest diagonal of the polygon or the width of the rectangle, wherein the length of the rectangle is between 1 Micron to 1 cm, preferably 5 micron to 200 micron.

Wherein the opening 36 of the protective layer 34 also has different sizes for different components installed in the component layer 12. Generally speaking, the size of the opening 36 of the protective layer 34 is between 0.1 micron and 100 microns, and the size is between 0.3 micron and 30 microns. It is preferable between microns; if voltage regulators, transformers and electrostatic discharge protection circuits are arranged in the component layer 12, the size of the opening 36 is relatively large, and its range is between 1 micron and 150 microns, and It is preferably between 5 microns and 100 microns. In addition, the opening 36 exposes a metal pad 32 on the uppermost layer of the thin circuit layer 24 for electrically connecting the circuit or plane on the over-passivation layer 36 .

The structure described above is defined as a wafer (wafer), such as a silicon wafer (silicon wafer), which is manufactured using different generations of integrated circuit process technologies, such as 1 micron, 0.8 micron, 0.6 micron, 0.5 micron, 0.35 micron, 0.25 microns, 0.18 microns, 0.25 microns, 0.13 microns, 90 nanometers (nm), 65 nanometers, 45 nanometers, 35 nanometers, and 25 nanometers technologies, and the generations of these integrated circuit process technologies are based on the gate length of the metal oxide semiconductor transistor 14 (gate length) or effective channel length (channel length) to define.

The size of the wafer is, for example, 5 o'clock, 6 o'clock, 8 o'clock, 12 o'clock, or 18 o'clock. The substrate 10 is fabricated using a lithography process including coating, exposing and developing photoresist. The thickness of the photoresist used to fabricate the substrate 10 is between 0.1 μm and 0.4 μm, and the photoresist is exposed by a 5X stepper or scanner. Among them, the multiple of the stepper means that when the light beam is projected from a mask (usually made of quartz) onto the wafer, the figure on the mask is reduced to the ratio of the wafer, and five times (5X) is It means that the proportion of the pattern on the mask is five times that of the pattern on the wafer. Scanners used in the advanced generation of integrated circuit process technology are usually scaled down by four times (4X) to improve the resolution. The beam wavelengths used by steppers or scanners are 436 nm (g-line), 365 nm (i-line), 248 nm (deep ultraviolet, DUV), 193 nm (DUV), 157 nm (DUV) Or 13.5 nm (extremely short ultraviolet, EUV). In addition, high-index immersion (high-index immersion) lithography technology can also be used to complete the thin circuit layer 24 on the wafer.

In addition, the wafers are fabricated in a clean room with class 10 or better (eg, class 1). The maximum number of dust particles per cubic foot allowed in a class 10 clean room is: no more than 1 dust particle greater than or equal to 1 micron, no more than 10 dust particles greater than or equal to 0.5 micron, no more than 10 dust particles greater than or equal to No more than 30 dust particles of 0.3 microns, no more than 75 dust particles greater than or equal to 0.2 microns, no more than 350 dust particles greater than or equal to 0.1 microns, and a clean room of class 1 allows per cubic foot The maximum number of dust particles per foot is: no more than 1 dust particle greater than or equal to 0.5 micron, no more than 3 dust particles greater than or equal to 0.3 micron, no more than 7 dust particles greater than or equal to 0.2 micron, Contain no more than 35 dust particles greater than or equal to 0.1 micron.

Wherein when copper is used as the thin line layer 24, a metal cap (metal cap) (not shown) needs to be used to protect the copper pad 32 exposed by the opening 36 of the protective layer 34, so that the pad 32 is free from It is damaged by oxidation and corrosion, and can be used as a wire bond for subsequent chips. The metal top layer includes an aluminum (aluminum) layer, a gold (gold) layer, a titanium (Ti) layer, a titanium-tungsten alloy layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer or a nickel ( Ni) layer. Wherein, when the metal top layer is an aluminum layer, a barrier layer (barrier layer) is formed between the copper pad and the metal top layer, and the barrier layer includes titanium, titanium-tungsten alloy, titanium nitride, tantalum, nitrogen tantalum, chromium (Cr) or nickel.

The above is the explanation of the semiconductor substrate 10, the fine interconnection structure 22 and the protective layer 34 of the present invention. Several different types of embodiments of the present invention are explained below. The embodiment of the present invention is to manufacture an over-passivations scheme and Manufacturing process, in the present invention, the structure on the protective layer includes stacked packaging, tape automated bonded (TAB), COG (chip on glass), tape-and-reel die bonding (Tape Carrier Package, TCP), COF (chip on film) packaging methods, and the use of polymer bumps to bond to another external substrate with Flip Chip (FC) technology, the structure and manufacturing process of each embodiment are explained below .

In addition, many parts of the embodiments explained below have the same materials and processes, so the materials and processes of the same components in the following embodiments will not be repeated. For example, the pads 32 in the following embodiments are made of aluminum. The material of the pad is used as an illustration, but the material of the pad 32 can also be copper. The difference is that when the material of the pad 32 includes copper metal, a metal top layer (such as an aluminum layer) must be used to protect the exposed layer 34 through the opening 36. The contact pads 32 containing copper metal are exposed, so that the contact pads 32 containing copper metal are prevented from being oxidized and corroded. And when the metal top layer is an aluminum layer, a barrier layer (barrier layer) is formed between the pad 32 and the aluminum layer, and the barrier layer includes titanium, titanium-tungsten alloy, titanium nitride, tantalum, tantalum nitride, chromium (Cr) or nickel. The following content is described without a metal top layer, but those skilled in the art can rely on the description of the following embodiments to implement by adding a metal top layer.

The first implementation of the first embodiment:

First, please refer to FIG. 2a, forming an adhesion barrier layer (adhesion/barrier layer) 38 on the protective layer 34 and the pads 32 above the entire substrate 10. In the present invention, the substrate 10 refers to a silicon wafer (silicon wafer) ), and the material of the adhesion barrier layer 38 can be formed of titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten alloy, vanadium, chromium, copper, chrome-copper alloy, tantalum, tantalum nitride, the above-mentioned materials alloy or a composite layer composed of the above materials. In addition, the adhesion/barrier layer 38 can be formed by means of electroplating, electroless plating, chemical vapor deposition or physical vapor deposition (such as sputtering), among which physical vapor deposition is preferably formed methods, such as metal sputtering process. In addition, the thickness of the adhesion/barrier layer 38 is between 0.02 micron and 0.8 micron, and preferably between 0.05 micron and 0.2 micron.

Please refer to FIG. 2b, and then form a seed layer (seed layer) 40 with a thickness between 0.005 micron and 2 microns (preferably between 0.1 micron and 0.7 micron) on the adhesion/barrier layer 38 On the other hand, the method of forming the seed layer 40 is, for example, sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. The seed layer 40 is beneficial to the setting of subsequent metal circuits, so the material of the seed layer 40 will vary with the material of the subsequent metal circuits. For example, when the metal layer of copper material is formed by electroplating on the seed layer 40, the material of the seed layer 40 is copper; when the metal layer of gold material is formed by electroplating on the seed layer 40, the material of the seed layer 40 is gold. When the metal layer of palladium material is formed by electroplating on the seed layer 40, the material of the seed layer 40 is preferably palladium; when the metal layer of platinum material is formed by electroplating on the seed layer 40, the material of the seed layer 40 is based on platinum. Good; when the metal layer of rhodium material is formed by electroplating on the seed layer 40, the material of the seed layer 40 is preferably rhodium; when the metal layer of the ruthenium material is formed by electroplating on the seed layer 40, the material of the seed layer 40 is preferably ruthenium When the metal layer of rhenium material is formed by electroplating on the seed layer 40, the material of the seed layer 40 is preferably rhenium; when the metal layer of nickel material is formed by electroplating on the seed layer 40, the material of the seed layer 40 is preferably nickel .

Referring to FIG. 2c, a photoresist layer 42 is formed on the seed layer 40, and the photoresist layer 42 is patterned by exposure and development processes to form a photoresist layer opening 42a on the photoresist layer. 42 and expose the seed layer 40 located above the pads 32 , and in the process of forming the photoresist layer opening 42 a, for example, exposure and development are performed with double (1X) exposure machines (steppers) or scanners (scanners).

The photoresist layer 42 has two types, which are: (1) wet film photoresist (liquid photoresist), which is formed by single or multiple spin coating or printing. The thickness of the wet film photoresist is between 3 microns and 60 microns, preferably between 5 microns and 40 microns; and (2) dry film photoresist (dry film photo resist), which It is formed by laminating method. The thickness of the dry film photoresist is between 30 microns and 300 microns, preferably between 50 microns and 150 microns. In addition, the photoresist can be positive-type or negative-type, and positive-type thick photoresist is better for better resolution. Expose the photoresist using an aligner or a one-fold (1X) stepper. This double (1X) means that when the beam is projected from a mask (usually made of quartz or glass) onto the wafer, the pattern on the mask is reduced to the ratio of the wafer, and the pattern on the mask The scale is the same as the pattern scale on the wafer. The beam wavelengths used by the aligner or double stepper are 436 nm (g-line), 397 nm (h-line), 365 nm (i-line), g/h line (combined with g-line and h-line) or g/h/i line (combined g-line, h-line and i-line). Using a double stepper (or double aligner) with a beam wavelength of g/h line or g/h/i line can be used for exposure of thick photoresist or thick photo sensitive polymer. In addition, the shape of the opening 42a of the patterned photoresist layer 42 may also include coil shape, square, circle, polygon or irregular shape.

2d and 2e, a metal layer 44 is formed on the seed layer 40 in the opening 42a by electroplating. The metal layer 44 is, for example, gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium or nickel. A single-layer metal layer structure or a composite metal layer structure, the thickness of the metal layer 44 is between 1 micron and 20 microns, preferably between 1.5 microns and 15 microns, and the composite metal layer structure Combinations include copper/nickel/gold, copper/gold, copper/nickel/palladium, copper/nickel/platinum and other combinations. In this embodiment, the metal layer 44 is a single layer, and the material of the metal layer 44 is gold. Two areas are defined on the surface of the metal layer 44, and these two areas are respectively a wire bonding pad 44a and a wire bonding pad 44b. The wire bonding pads 44a and 44b can provide wire bonding in subsequent manufacturing processes. The pads 44a, 44b are viewed from a top perspective view (FIG. 2e), and the positions of the bonding pads 44a, 44b are different from those of the pads 32, wherein the bonding pads 44a or the substrate 10 below the bonding pads 44b At least one active component may be provided, and the active component includes a diode, a transistor, etc. The active component has been described in detail in the above-mentioned component layer 12, so it will not be repeated here. In addition, one of the bonding pads 44a, 44b The positions of the bonding pads 44a and 44b can be changed according to different needs of users, as shown in FIG. 2f.

Please refer to FIG. 2g to remove the patterned photoresist layer 42, wherein the patterned photoresist layer 42 can be removed by organic solvents, such as acetone, alcohols, etc., or by inorganic solvents, such as sulfuric acid and hydrogen peroxide. (H2SO4, H2O2), etc., and the patterned photoresist layer 42 can also be removed by burning with high pressure oxygen (O2).

2h, the seed layer 40 and the adhesion barrier layer 38 that are not below the metal layer 44 are removed. If the material of the seed layer 44 is gold, it can be removed by using an etching solution containing iodine to remove the adhesion barrier. The method of the barrier layer 38 is divided into dry etching and wet etching. The dry etching uses high-pressure argon gas for sputter etching, while the wet etching can use hydrogen peroxide to remove the adhesive barrier layer 38 when it is a titanium-tungsten alloy.

Referring to FIG. 2i, a polymer layer 46 is then formed on the protection layer 34 and the metal layer 44, and the polymer layer 46 is patterned by exposure, development and etching processes to polymerize the polymer layer. The material layer 46 forms several openings 46a, and the openings 46a expose the bonding pads 44a, 44b on the metal layer 44, and then heat and harden to harden the polymer layer 46. The temperature of this hardening process is between 150 degrees. (°C) to 300°C (°C), and the material of the polymer layer 46 can be selected from polyimide (polyimide, PI), phenylcyclobutene (benzocyclobutene, BCB), parylene (parylene ), epoxy-based material (epoxy-based material), such as epoxy resin or photoepoxySU-8 provided by Sotec Microsystems in Renens, Switzerland, elastic material (elastomer), such as silicone (silicone). Wherein, when the polymer layer 46 is an optically sensitive material, the polymer layer 46 can be patterned only by lithography process (no etching process is required).

Please refer to FIG. 2j. Only the bonding pads 44a and 44b in FIG. 2j are different from FIG. 2i. FIG. 2j again illustrates that the positions of the bonding pads 44a and 44b can be changed according to user or product design requirements.

Referring to FIG. 2 k , the substrate 10 is subjected to a dicing step to produce a plurality of semiconductor chips (chips) 48 .

So far, the fabrication of the semiconductor chip 48 is completed, and the integrated circuit 49 below represents various structures under the protection layer 34 in FIGS. 2 a to 2 i. That is, the integrated circuit 22 includes the substrate 10 , the device layer 12 , the metal oxide semiconductor transistor 14 , the source 16 , the drain 18 , the gate 20 , the fine line structure 22 , the thin line dielectric layer 26 , and the conductive plug 30 .

2l and 2m, these semiconductor chips 48 include a first semiconductor chip 48a and a second semiconductor chip 48b; wherein the first semiconductor chip 48a and the second semiconductor chip 48b may come from the same substrate 10 or different substrates 10, or the structural design of the first semiconductor chip 48a and the second semiconductor chip 48b may be the same or different; then use an adhesive 50 (such as epoxy resin) to adhere the first semiconductor chip 48a to a first external circuit 52 , the first external circuit 52 includes one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a silicon substrate. In this embodiment, the first external circuit 52 is a printed circuit board, and the first external circuit 52 has several connection pads 52a.

Also use the adhesive 50 to adhere and stack the lower surface of the second semiconductor chip 48b on the polymer layer 46 on the first semiconductor chip 48a, wherein at least 1% to 10% of the area of the first semiconductor chip 48a is exposed, and the first semiconductor chip 48b is exposed. The exposed area of the semiconductor chip 48a includes the bonding pad 44a and the bonding pad 44b of the first semiconductor chip 48a.

2n, the lower surface of a second external circuit 54 is also adhered and stacked on the polymer layer 46 of the second semiconductor chip 48b by using an adhesive 50. This second external circuit 54 can be selected from a printed circuit board, One of a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a silicon substrate. In this embodiment, the second external circuit 54 is a silicon chip, and the second external circuit 54 has a plurality of connection pads 54a.

Please refer to shown in Fig. 2 o, utilize the bonding process to form several wires 56 on the bonding pad 44a and the bonding pad 44b of the first semiconductor chip 48a, the bonding pad 44a and the bonding pad of the second semiconductor chip 48b On the pad 44b, on the connection pad 52a of the first external circuit 52, and on the connection pad 54a of the second external circuit 54, the connection pad 44a of the first semiconductor chip 48a is connected to the first external circuit 52. The pads 52a are connected to each other, so that the bonding pad 44b of the first semiconductor chip 48a is connected to the bonding pad 44a of the second semiconductor chip 48b, and the bonding pad 44b of the second semiconductor chip 48b is connected to the second external circuit 54. The connection pads 54a of the second semiconductor chip 48b are connected to each other, wherein there will be a small part of the connection pads 44a of the second semiconductor chip 48b, part of the connection pads 54a of the second external circuit 54 and part of the connection pads of the first external circuit 52 52a are interconnected (not shown).

Please refer to FIG. 2p, the first semiconductor chip 48a, the second semiconductor chip 48b, the first external circuit 52 and the second external circuit 54 that have completed the wire bonding process are packaged to form a polymer protection layer 58 to cover the On the first semiconductor chip 48 a , the second semiconductor chip 48 b , the first external circuit 52 and the second external circuit 54 , the polymer protection layer 58 is made of, for example, epoxy resin.

The second embodiment of the first embodiment:

The structure and manufacturing method of the second embodiment are quite similar to those of the first embodiment, so the materials and manufacturing processes of the same components in the following embodiments will not be described repeatedly. Among them, the integrated circuit 59 Various structures below the protective layer 34 in Figures 3a to 3n will be represented. That is, the integrated circuit 22 includes the substrate 10 , the device layer 12 , the metal oxide semiconductor transistor 14 , the source 16 , the drain 18 , the gate 20 , the fine line structure 22 , the thin line dielectric layer 26 , and the conductive plug 30 .

3a, a polymer layer 60 is formed on the protective layer 34, and the polymer layer 60 is patterned by exposure, development and etching processes, so that the polymer layer 60 forms a number of layers. An opening 60a exposing the pad 32 through the opening 60a.

Please refer to FIG. 3b, and then form an adhesion barrier layer (adhesion/barrier layer) 62 on the polymer layer 60 and the pad 32 above the entire substrate 10; then form a thickness between 0.005 microns and 2 microns A seed layer 64 (preferably between 0.1 μm and 0.7 μm thick) is over the entire adhesion/barrier layer 62 .

Referring to FIG. 3c, a photoresist layer 66 is formed on the seed layer 64, and the photoresist layer 66 is patterned by exposure and development processes to form photoresist layer openings 66a on the photoresist layer. 66 and expose the seed layer 64 above the pads 32 , and in the process of forming the photoresist layer opening 66 a, for example, exposure and development are carried out with double (1X) exposure machines (steppers) or scanners (scanners).

3d and 3e, a metal layer 68 is formed in the opening 66a and on the seed layer 64 by electroplating. The metal layer 68 is, for example, gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium or nickel. A single-layer metal layer structure or a composite metal layer structure, the thickness of the metal layer 68 is between 1 micron and 20 microns, preferably between 1.5 microns and 15 microns, and the composite metal layer structure Combinations include copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/platinum combinations. In this embodiment, the metal layer 68 is a single layer, and the material of the metal layer 68 is gold. Two areas are defined on the surface of the metal layer 68, and these two areas are respectively a wire bonding pad 68a and a wire bonding pad 68b. The wire bonding pads 68a and 68b can provide wire bonding in subsequent manufacturing processes. The pads 68a, 68b are viewed from a top perspective view, and the positions of the bonding pads 68a, 68b are different from the positions of the pads 32, wherein the bonding pads 68a or the substrate 10 below the bonding pads 68b can be provided with at least An active component. This active component has been introduced in detail in the component layer 12 above, and will not be repeated here.

Referring to FIG. 3 f , the patterned photoresist layer 66 and the seed layer 64 and the adhesion barrier layer 62 not under the metal layer 68 are removed.

Referring to FIG. 3g, a polymer layer 70 is then formed on the polymer layer 60 and the metal layer 68, and the polymer layer 70 is patterned by exposure, development and etching processes to make the polymer layer 70 Several openings 70 a are formed in the polymer layer 70 , and the openings 70 a expose the bonding pads 68 a , 68 b on the metal layer 68 , followed by heating and hardening to harden the polymer layer 70 .

Referring to FIG. 3 h , the substrate 10 is subjected to a dicing step to produce a plurality of semiconductor chips (chips) 72 .

3i and 3j, these semiconductor chips 72 include a first semiconductor chip 72a and a second semiconductor chip 72b; wherein the first semiconductor chip 72a and the second semiconductor chip 72b may come from the same substrate 10 or different substrates 10, or the structural design of the first semiconductor chip 72a and the second semiconductor chip 72b may be the same or different; then use an adhesive 74 (such as epoxy resin) to adhere the first semiconductor chip 72a to a first external circuit 76 , the first external circuit 76 has several connecting pads 76a.

Also use the adhesive 74 to adhere and stack the lower surface of the second semiconductor chip 72b on the polymer layer 70 on the first semiconductor chip 72a, wherein at least 1% to 10% of the area of the first semiconductor chip 72a is exposed, and the first semiconductor chip 72a is exposed. The exposed area of the semiconductor chip 72a includes the bonding pad 68a and the bonding pad 68b of the first semiconductor chip 72a.

Please refer to FIG. 3k, the lower surface of a second external circuit 78 is also adhered and stacked on the polymer layer 70 of the second semiconductor chip 72b by using an adhesive 74. This second external circuit 78 can be selected from a printed circuit board, One of a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a silicon substrate. In this embodiment, the second external circuit 78 is a silicon chip, and the second external circuit 78 has a plurality of connection pads 78a.

See also shown in Fig. 3l, utilize the wire-bonding process to form several wires 80 on the wire-bonding pad 68a and the wire-bonding pad 68b of the first semiconductor chip 72a, on the wire-bonding pad 68a and the wire-bonding pad 68b of the second semiconductor chip 72b. On the pad 68b, on the connection pad 76a of the first external circuit 76, and on the connection pad 78a of the second external circuit 78, the connection pad 68a of the first semiconductor chip 72a is connected to the first external circuit 76. The pads 76a are connected to each other, so that the bonding pad 68b of the first semiconductor chip 72a is connected to the bonding pad 68a of the second semiconductor chip 72b, and the bonding pad 68b of the second semiconductor chip 72b is connected to the second external circuit 78. The connecting pads 78a of the second semiconductor chip 72b are connected to each other, wherein there will be a small part of the bonding pads 68a of the second semiconductor chip 72b, part of the connecting pads 78a of the second external circuit 78 and part of the connecting pads of the first external circuit 76 76a are interconnected (not shown).

Please refer to FIG. 3m, the first semiconductor chip 72a, the second semiconductor chip 72b, the first external circuit 76 and the second external circuit 78 that have completed the wire bonding process are packaged to form a polymer protective layer 80 to cover the On the first semiconductor chip 72 a , the second semiconductor chip 72 b , the first external circuit 76 and the second external circuit 78 , the polymer protective layer 80 is made of, for example, epoxy resin.

The third implementation mode of the first embodiment:

The structure and manufacturing method of the third embodiment are quite similar to those of the second embodiment, so the materials and manufacturing processes of the same components in the following embodiments will not be described repeatedly.

The structure of the second embodiment is that 2 semiconductor chips are stacked on a first external circuit board, and another second external circuit is arranged on the upper semiconductor chip, and the 2 semiconductor chips, the first external circuit are connected via several wires. The circuit board is connected to the second external circuit. The structure of the third embodiment is shown in Figure 4a, which is composed of four semiconductor chips 82a, 82b, 82c, 82d, a first external circuit board 84 and a second external circuit 86, wherein four semiconductor chips are formed The processes and materials of 82a, 82b, 82c, and 82d are the same as those of the second embodiment (as shown in Figures 3a to 3h), and the semiconductor chip 82a produced through the process of the second embodiment has a bonding pad 88a and bonding pad 88b, the semiconductor chip 82b has a bonding pad 90a and a bonding pad 90b, the semiconductor chip 82c has a bonding pad 92a and a bonding pad 92b, and the semiconductor chip 82d has a bonding pad 94a and a bonding pad 90b. The first external circuit board 84 has a connection pad 84a, and the second external circuit 86 also has a connection pad 86a.

In the manufacturing process, the semiconductor chip 82a is first placed on the first external circuit board 84 by using an adhesive, and then the semiconductor chip 82b is stacked on the semiconductor chip 82a by using the same adhesive, and the semiconductor chip 82c is stacked on the semiconductor chip 82b. Above, the semiconductor chip 82d is stacked on the semiconductor chip 82c, and the second external circuit 86 is stacked on the semiconductor chip 82d, wherein at least 1% to 10% of the area of the semiconductor chip 82a, the semiconductor chip 82b and the semiconductor chip 82c are exposed, and The semiconductor chip 82d has at least 1% to 70% of the exposed area, and the exposed surfaces of the semiconductor chip 82a, the semiconductor chip 82b, the semiconductor chip 82c and the semiconductor chip 82d also make the bonding pads 88a, 88b, and the bonding pads 90a, 90b, bonding pads 92a, 92b and bonding pads 94a, 94b are exposed.

Please refer to FIG. 4 b , using a wire bonding process to form several wires 96 on the wire bonding pads 88a and 88b of the semiconductor chip 82a, and on the wire bonding pads 90a and 90b of the semiconductor chip 82b. , on the bonding pad 92a and the bonding pad 92b of the semiconductor chip 82c, on the bonding pad 94a and the bonding pad 94b of the semiconductor chip 82d, on the connecting pad 84a of the first external circuit board 84 and the second external On the connecting pad 86a of the circuit 86, the bonding pad 88a of the semiconductor chip 82a is connected to the connecting pad 84a of the first external circuit 84, so that the bonding pad 88b of the semiconductor chip 82a is connected to the bonding pad of the semiconductor chip 82b. The bonding pads 90a are connected to each other, so that the bonding pads 90b of the semiconductor chip 82b are connected to the bonding pads 92a of the semiconductor chip 82c, and the bonding pads 92b of the semiconductor chip 82c are connected to the bonding pads 94a of the semiconductor chip 82d. connection, so that the bonding pad 94b of the semiconductor chip 82d and the connection pad 86a of the second external circuit 86 are connected to each other.

Wherein part of the connection pad 86a of the second external circuit 86 is connected to the connection pad 84a of the first external circuit board 84, part of the bonding pad 88a of the semiconductor chip 82b, and part of the bonding pad 90a of the semiconductor chip 82c The bonding pads 90a of a part of the semiconductor chip 82d are connected to the connecting pads 84a of the first external circuit board 84 (not shown in the figure).

Please refer to FIG. 4c, the semiconductor chips 82a, 82b, 82c, 82d, the first external circuit board 84, and the second external circuit 86 that have completed the wire bonding process are subjected to the packaging process to form a polymer protection layer 97 coated on the semiconductor. On the chips 82a, 82b, 82c, 82d, the first external circuit board 84 and the second external circuit 86, the polymer protection layer 97 is made of epoxy resin, for example.

The first implementation mode of the second embodiment:

In the structure of this embodiment, the substrate 10, the component layer 12, the metal oxide semiconductor transistor 14, the source 16, the drain 18, the gate 20, the thin line structure 22, the thin line dielectric layer 26, the conductive plug 30, etc. are integrated circuits 100, and the structures and processes of the integrated circuit 100 have been fully described in the above implementation, so the structures and processes of the integrated circuit 100 in the embodiment will not be described repeatedly.

Referring to FIG. 5 a , a polymer layer 112 is formed on the protection layer 34 and the pads 32 on the entire integrated circuit 100 .

Referring to FIG. 5b, the polymer layer 112 is patterned through exposure, development and etching processes, so that the polymer layer 112 forms several openings 112a and several polymer bumps. bump) 114 (only one is shown in the figure), the opening 112a exposes the protective layer 34 and the pad 32, and then heats and hardens to harden the polymer bump 114. The temperature of this hardening process is between 150 degrees ( ℃) to 300 degrees (℃), and the material of the polymer bump 114 can be selected from polyimide (polyimide, PI), phenylcyclobutene (benzocyclobutene, BCB), parylene (parylene ), epoxy-based material (epoxy-based material), such as epoxy resin or photoepoxySU-8 provided by Sotec Microsystems in Renens, Switzerland, elastic material (elastomer), such as silicone (silicone). Wherein when the polymer layer 112 is an optically sensitive material, the polymer layer 112 can be patterned only by lithography (no etching process), and the thickness of the polymer bump 114 is between 5 microns and 50 microns, The polymer bump 114 has a maximum lateral dimension ranging from 10 microns to 60 microns.

Referring to FIG. 5 c , an adhesion/barrier layer (adhesion/barrier layer) 116 is formed on the protection layer 34 , the pad 32 and the polymer bump 114 on the entire integrated circuit 100 . In addition, the adhesion/barrier layer 116 can be formed by means of electroplating, electroless plating, chemical vapor deposition or physical vapor deposition (such as sputtering), among which physical vapor deposition is a preferred form. methods, such as metal sputtering process. In addition, the thickness of the adhesion barrier layer 116 is between 0.02 micron and 0.8 micron, and preferably between 0.05 micron and 0.2 micron.

Please refer to FIG. 5d, and then form a seed layer (seed layer) 118 with a thickness between 0.005 micron and 2 microns (preferably between 0.1 micron and 0.7 micron) on the adhesion/barrier layer 116. On the other hand, the method of forming the seed layer 118 is, for example, sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. The seed layer 118 is beneficial to the setting of subsequent metal circuits, so the material of the seed layer 118 will vary with the material of the subsequent metal circuits. For example, when the metal layer of copper material is formed by electroplating on the seed layer 118, the material of the seed layer 118 is copper; when the metal layer of gold material is formed by electroplating on the seed layer 118, the material of the seed layer 118 is gold. When the metal layer of palladium material is formed by electroplating on the seed layer 118, the material of the seed layer 118 is preferably palladium; when the metal layer of platinum material is formed by electroplating on the seed layer 118, the material of the seed layer 118 is based on platinum Good; when the metal layer of rhodium material is formed by electroplating on the seed layer 118, the material of the seed layer 118 is preferably rhodium; when the metal layer of the ruthenium material is formed by electroplating on the seed layer 118, the material of the seed layer 118 is preferably ruthenium When the metal layer of rhenium material is formed by electroplating on the seed layer 118, the material of the seed layer 118 is preferably rhenium; when the metal layer of nickel material is formed by electroplating on the seed layer 118, the material of the seed layer 118 is preferably nickel .

Referring to FIG. 5e, a photoresist layer 120 is formed on the seed layer 118, and the photoresist layer 120 is patterned by exposure (exposure) and development (development) processes to form several photoresist layer openings 120a in the light. In the resist layer 120 and exposed on the seed layer 118 above the pads 32 and the polymer bumps 114, and in the process of forming the photoresist layer opening 120a, for example, one time (1X) exposure machine (steppers) or Scanners perform exposure and development.

The photoresist layer 120 has two types, which are: (1) wet film photoresist (liquid photoresist), which is formed by single or multiple spin coating or printing. The thickness of the wet film photoresist is between 3 microns and 60 microns, preferably between 5 microns and 40 microns; and (2) dry film photoresist (dry film photo resist), which It is formed by laminating method. The thickness of the dry film photoresist is between 30 microns and 300 microns, preferably between 50 microns and 150 microns. In addition, the photoresist can be positive-type or negative-type, and positive-type thick photoresist is better for better resolution. Expose the photoresist using an aligner or a one-fold (1X) stepper. This double (1X) means that when the beam is projected from a mask (usually made of quartz or glass) onto the wafer, the pattern on the mask is reduced to the ratio of the wafer, and the pattern on the mask The scale is the same as the pattern scale on the wafer. The beam wavelengths used by the aligner or double stepper are 436nm (g-line), 397nm (h-line), 365nm (i-line), g/h line (combined with g-line and h-line) or g/h/i line (combined g-line, h-line and i-line). Using a double stepper (or double aligner) with a beam wavelength of g/h line or g/h/i line can be used for exposure of thick photoresist or thick photo sensitive polymer. In addition, the shape of the opening 120a of the patterned photoresist layer 120 may also include coil shape, square, circle, polygon or irregular shape.

5f, a metal layer 122 is formed on the seed layer 118 in the opening 120a by electroplating, and the metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 114, and the metal layer 122 Such as gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium or nickel single-layer metal layer structure or composite metal layer structure, the thickness of the metal layer 122 is between 1 micron to 20 microns, preferably The thickness can be between 1.5 microns and 15 microns, and the combination of the composite metal layer structure includes combinations of copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/platinum, etc., in this embodiment The metal layer 122 is a single layer, and the material of the metal layer 122 is gold. The surface of the metal layer 122 on the polymer bump 114 defines a region as a bonding pad 124 , and the bonding pad 124 can be used to connect external circuits.

Referring to FIG. 5 g , the patterned photoresist layer 120 and the seed layer 118 and the adhesion barrier layer 116 not under the metal layer 122 are removed.

5h, the integrated circuit 100 is cut to produce several semiconductor chips (chips) 126, and the bonding pads 124 on the semiconductor chips 126 can be automatically bonded (tape automatedbonded, TAB), COG (chip) on glass), tape carrier package (Tape Carrier Package, TCP) or COF (chip on film) connected to an external circuit 128, the external circuit 128 has at least one bonding metal layer 129, bonding pads 124 Connect to bonding metal layer 129 .

As shown in FIG. 5 i , this embodiment is connected to the external circuit 128 in a COG manner, and the bonding pad 124 on the semiconductor chip 126 is bonded to the bonding metal layer 129 of the external circuit 128 by using an anisotropic conductive adhesive 130 .

Please refer to FIG. 5j. If this embodiment is connected to the external circuit 128 in a COF manner, the bonding pad 124 on the semiconductor chip 126 is also bonded to the bonding metal layer 129 of the external circuit 128 by using an anisotropic conductive adhesive 130. As shown in FIG. 5k, another method of COF bonding is shown in FIG. The gold on the bonding pad 124 and the tin layer 132 on the bonding metal layer 129 form a tin-gold alloy layer 134 to form a solid bond. This method of thermocompression bonding can also be applied to tape automated bonded, TAB) and Tape Carrier Package (TCP).

The second implementation mode of the second embodiment:

The structure and manufacturing method of the second embodiment are quite similar to those of the first embodiment, so the materials and manufacturing processes of the same components in the following embodiments will not be described repeatedly.

Please refer to FIG. 6a, the difference between the second embodiment and the first embodiment is that the integrated circuit 100 of the second embodiment has two pads 32, 32', and the polymer layer 112 is also formed on the entire integrated circuit 100. The protection layer 34 is on the pads 32, 32'.

Referring to FIG. 6 b, the polymer layer 112 is patterned through exposure, development and etching processes, so that the polymer layer 112 forms several polymer bumps (polymer bumps) 114 (in the figure). Only one shown), the opening 112a exposes the protective layer 34 and the pads 32, 32', followed by heat curing to harden the polymer bump 114. Wherein when the polymer bump 114 is an optically sensitive material, the polymer bump 114 can be patterned only by lithography (no etching process), and the thickness of the polymer bump 114 is between 5 microns and 50 μm. microns, the maximum lateral dimension of the polymer bump 114 is between 10 microns and 60 microns.

Referring to FIG. 6c, an adhesion barrier layer (adhesion/barrier layer) 116 is formed on the protection layer 34, the pads 32, 32' and the polymer bump 114 on the entire integrated circuit 100. The adhesion barrier layer 116 The thickness is between 0.02 micron and 0.8 micron, and preferably between 0.05 micron and 0.2 micron.

See also shown in Figure 6d, then form a seed layer (seed layer) 118 with a thickness between 0.005 microns and 2 microns (preferably between 0.1 microns and 0.7 microns) on the adhesion/barrier layer 116 .

Referring to FIG. 6e, a photoresist layer 120 is formed on the seed layer 118, and the photoresist layer 120 is patterned by exposure and development (development) processes to form several photoresist layer openings 120a, 120b. The photoresist layer 120 exposes the seed layer 118 above the pads 32 , 32 ′ and the polymer bump 114 respectively.

6f, the metal layer 122 is formed on the seed layer 118 in the openings 120a, 120b by electroplating. The metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 114, and the metal layer 122 Such as gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium or nickel single-layer metal layer structure or composite metal layer structure, the thickness of the metal layer 122 is between 1 micron to 20 microns, preferably The thickness can be between 1.5 microns and 15 microns, and the combination of the composite metal layer structure includes combinations of copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/platinum, etc., in this embodiment The metal layer 122 is a single layer, and the material of the metal layer 122 is gold. The two regions defined on the surface of the metal layer 122 are the bonding pad 124 and a bonding pad 136 respectively. The bonding pad 124 is located on the polymer bump 114. , and the bonding pad 136 is located on the pad 32 ′, the bonding pad 124 and the bonding pad 136 can be used to connect external circuits.

Referring to FIG. 6 g , the patterned photoresist layer 120 is removed and the seed layer 118 and the adhesion barrier layer 116 not under the metal layer 122 are removed.

6h and 6i, the integrated circuit 100 is diced to produce several semiconductor chips (chips) 126, and the bonding pads 124 on the semiconductor chips 126 can be bonded to the semiconductor chips 126 via flip-chip (Flip Chip, FC) technology. On the other external substrate 138, the external substrate 138 is, for example, a semiconductor chip. When the external substrate 138 is a semiconductor chip, the external substrate 138 has several bonding pads 140, and a bonding metal layer 142 is provided on the bonding pads 140. The material of the bonding metal layer 142 includes a single-layer metal layer structure or a composite metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, tin or nickel. The material of the layer 122 is changed. For example, when the material of the metal layer 122 is gold, the material of the bonding metal layer 142 is gold or a metal layer containing tin, and then the external substrate 138 is stacked by Flip Chip (FC) technology. It is arranged on the semiconductor chip 126, and the way of bonding can be thermocompression bonding, so that the bonding metal layer 142 and the metal layer 122 are fused or alloyed (gold/gold bonding or gold-tin alloy) bonding, and on the external substrate 138 An encapsulation layer 144 is formed between the semiconductor chip 126 to cover it, and the material of the encapsulation layer 144 is a polymer material, such as epoxy resin. In addition, the wire bonding pad 136 is connected to another external circuit (not shown) through a wire bonding process to form a wire 146 .

Please refer to FIG. 6j. In addition, the wire bonding pad 136 can be connected to another external circuit by using the wire 146 formed by the wire bonding process, and can also be connected to the solder ball 147 of the external circuit. The thickness of the solder ball 147 is Between 50 microns and 300 microns, this connection can be bonded by thermocompression.

The third implementation mode of the second embodiment:

The structure and manufacturing method of the third embodiment are quite similar to those of the second embodiment and the first embodiment, so the materials and manufacturing processes of the same components in the following embodiments will not be described repeatedly.

7a and 7b, the only difference between the third embodiment and the second embodiment is that the position of the bonding pad 136 is different, and the position of the bonding pad 136 of the third embodiment is viewed from a top perspective view (Fig. 9b) It can be seen that the position of the bonding pad 136 is different from the position of the bonding pad 32', wherein at least one active component may be provided on the substrate 10 in the integrated circuit 100 under the bonding pad 136, and the active component includes a diode , transistors, etc., the active components have been described in detail in the above-mentioned component layer 12, and will not be repeated here.

The fourth implementation mode of the second embodiment:

The structure and manufacturing method of the fourth embodiment are quite similar to those of the third embodiment and the first embodiment, so the materials and manufacturing processes of the same components in the following embodiments will not be described repeatedly.

Referring to FIG. 8a, the polymer layer 112 is also formed on the protection layer 34, the pads 32, and the pads 32' on the entire integrated circuit 100. Referring to FIG.

Please refer to FIG. 8 b, and pattern the polymer layer 112 through exposure (exposure), development (development) process and etching process, so that the polymer layer 112 forms several openings 112a and several polymer islands. ) 142, the opening 112a exposes the protective layer 34, the pads 32 and the pads 32', and then heats and hardens to harden the polymer block 148. The temperature of this hardening process is between 150 degrees (°C) and 300 degrees (°C) ), and the material of the polymer block 148 can be selected from polyimide (polyimide, PI), phenylcyclobutene (benzocyclobutene, BCB), parylene (parylene), epoxy-based material (epoxy -based material) such as epoxy resin or photoepoxySU-8 provided by Sotec Microsystems in Renens, Switzerland, elastic material (elastomer), such as silicone (silicone). When the polymer layer 112 is an optically sensitive material, the polymer layer 112 can be patterned only by lithography (no etching process), and the thickness of the polymer block 148 is between 5 microns and 50 microns.

8c and 8d, another polymer layer 150 is then formed in the polymer block 148 and the opening 112a. The material of this polymer layer 150 is the same as that of the polymer layer 112. (development) process and etching process to pattern the polymer layer 150 to form several polymer bumps (polymer bump) 152 (only one is shown in the diagram), wherein when the polymer layer 150 is an optically sensitive material, The polymer layer 150 can be patterned using only a lithography process (no etching process is required), and the thickness of the polymer bumps is between 5 microns and 50 microns, and the maximum lateral dimension of the polymer bumps 152 is between 10 microns and 60 microns .

Referring to FIG. 8e , an adhesion/barrier layer 116 is formed on the pads 32 , the pads 32 ′, the polymer bump 152 and the polymer block 148 on the entire integrated circuit 100 .

See also shown in Figure 8f, then form a seed layer (seed layer) 118 with a thickness between 0.005 microns and 2 microns (preferably between 0.1 microns and 0.7 microns) on the adhesion/barrier layer 116 .

Referring to FIG. 8g, a photoresist layer 120 is formed on the seed layer 118, and the photoresist layer 120 is patterned by exposure (exposure) and development (development) processes to form several photoresist layer openings 120a on the photoresist layer. layer 120 and exposes the seed layer 118 above the pads 32, 32', polymer bumps 152 and polymer blocks 148, and the process of forming the photoresist layer opening 120a is, for example, doubled (1× ) exposure machine (steppers) or scanners (scanners) for exposure and development.

Please refer to FIG. 8h, the metal layer 122 is formed on the seed layer 118 in the opening 120a by electroplating, and the metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 152, and the metal layer 122 is, for example, A single-layer metal layer structure or a composite metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium or nickel, the thickness of the metal layer 122 is between 1 micron and 20 microns, and the preferred thickness can be Between 1.5 microns and 15 microns, and the combination of the composite metal layer structure includes copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/platinum and other combinations, in this embodiment the metal The layer 122 is a single layer, and the material of the metal layer 122 is gold. The surface of the metal layer 122 on the polymer bump 152 defines a region as a bonding pad 124. This bonding pad 124 can be used to connect to an external circuit. The surface of the metal layer 122 on the object 148 defines a region as the wire bonding pad 136, and the wire bonding pad 136 is connected to an external circuit through a wire bonding process, wherein the polymer block 148 located under the wire bonding pad 136 is used for wire bonding. It can buffer the stress generated by wire bonding during the manufacturing process, and has sufficient buffering effect on the thinner substrate 10, which can prevent the substrate 10 of the integrated circuit 100 and the active components of the component layer 12 from being damaged during the wire bonding process. In addition, this embodiment The positions of the bonding pads 148 and the bonding pads 32' are different from the top perspective view, but the bonding pads 136 can also be located above the bonding pads 32', so the discussion will not be repeated here.

Referring to FIG. 8 i , the patterned photoresist layer 120 is removed, the seed layer 118 and the adhesion barrier layer 116 not under the metal layer 122 are removed.

Referring to FIG. 8 j , the integrated circuit 100 is subjected to a dicing step to produce several semiconductor chips (chips) 126 .

Please refer to FIG. 8k. This FIG. 8k is similar to the above-mentioned FIG. 6i. It is to bond the semiconductor chip 126 to another external substrate 138 via Flip Chip (FC) technology. The description of the bonding is as described in the above-mentioned FIG. 6i same, so it will not be repeated here.

The fifth implementation mode of the second embodiment:

The structure and production method of the fifth embodiment are quite similar to the structure and production method of the fourth embodiment, and the structure of the fourth embodiment is a change of the first embodiment, so the following examples and the same components in the examples Materials and processes will not be described repeatedly.

Please refer to FIG. 9a, the difference between the fifth embodiment and the fourth embodiment lies in the steps of exposure (exposure), development (development) process and etching process to pattern the polymer layer 112 and heat hardening. These two steps are to form the polymer block 148 and the polymer bump 114 at the same time, that is, the thickness of the polymer block 148 and the polymer bump 114 is the same, and the thickness of the polymer block 148 and the polymer bump 114 is between 5 microns to 50 microns.

Please refer to FIG. 9 b , sequentially form an adhesion barrier layer (adhesion/barrier layer) 116 and a seed layer with a thickness between 0.005 microns and 2 microns (preferably between 0.1 microns and 0.7 microns). The (seed layer) 118 is on the pads 32 , 32 ′, polymer bumps 114 and polymer blocks 148 throughout the integrated circuit 100 .

Referring to FIG. 9c, a photoresist layer 120 is formed on the seed layer 118, and the photoresist layer 120 is patterned by exposure and development processes to form several photoresist layer openings 120a on the photoresist layer. layer 120 and exposes the seed layer 118 above the pads 32, 32', polymer bumps 114 and polymer blocks 148, and the process of forming the photoresist layer opening 120a is, for example, doubled (1× ) exposure machine (steppers) or scanners (scanners) for exposure and development.

Referring to FIG. 9d, a metal layer 122 is formed on the seed layer 118 in the opening 120a by electroplating. The metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 114. The metal layer 122 is, for example, gold. , copper, silver, palladium, platinum, rhodium, ruthenium, rhenium or nickel single-layer metal layer structure or composite metal layer structure, the thickness of the metal layer 122 is between 1 micron and 20 microns, and the preferred thickness can be between Between 1.5 microns and 15 microns, and the combination of the composite metal layer structure includes combinations of copper/nickel/gold, copper/gold, copper/nickel/palladium and copper/nickel/platinum, etc. In this embodiment, the metal layer 122 is a single layer, and the metal layer 122 is made of gold. The surface of the metal layer 122 on the polymer bump 114 defines a region as a bonding pad 124. This bonding pad 124 can be used to connect to an external circuit. The surface of the metal layer 122 on the block 148 defines an area as the wire bonding pad 136, and the wire bonding pad 136 is connected to the external circuit through the wire bonding process, wherein the polymer block 148 located under the wire bonding pad 136 is in the wire bonding process. It can buffer the stress generated by wire bonding, and has a sufficient buffer effect for the thinner substrate 10, which can prevent the substrate 10 of the integrated circuit 100 and the active components of the component layer 12 from being damaged during the wire bonding process. In addition, this embodiment consists of The positions of the wire bonding pads 136 and the pads 32 ′ are different from the top perspective view, but the wire bonding pads 136 can also be located above the pads 32 ′, and the discussion will not be repeated here.

Referring to FIG. 9 e , the patterned photoresist layer 120 is removed and the seed layer 118 and the adhesion barrier layer 116 not under the metal layer 122 are removed.

Referring to FIG. 9 f , the integrated circuit 100 is subjected to a dicing step to produce several semiconductor chips (chips) 126 .

Please refer to FIG. 9g. This FIG. 9g is similar to the above-mentioned FIG. 6i. The semiconductor chip 126 is bonded to another external substrate 138 through flip-chip (Flip Chip, FC) technology, and the bonding description is as described in the above-mentioned FIG. 6i. same, so it will not be repeated here.

The sixth embodiment of the second embodiment:

The structure and production method of the sixth embodiment are quite similar to the structure and production method of the first embodiment, and the structure of the sixth embodiment is a change of the first embodiment, so the following examples and the same components in the examples Materials and processes will not be described repeatedly.

This embodiment is a continuation of the process in Figure 5e of the first embodiment. After completing Figure 5e, please refer to Figure 10a to form a metal layer 154 on the seed layer 118 in the opening 120a by electroplating. Copper, the thickness of the metal layer 154 is between 1 micron and 20 microns, preferably between 1.5 microns and 15 microns.

Please refer to FIG. 10b, and then electroplate a metal layer 156 on the metal layer 148. The material of this metal layer 156 is nickel, for example. The thickness of this metal layer 156 is between 0.1 micron and 20 microns, and the preferred thickness can be between Between 1 micron and 15 microns.

10c, another photoresist layer 158 is formed on the photoresist layer 120 and the metal layer 156, and the photoresist layer 158 is patterned by exposure and development processes to form several photoresist layers. The resist layer opening 158a is in the photoresist layer 158 and exposes the metal layer 156 above the polymer bump 114, and the process of forming the photoresist layer opening 158a is, for example, with a double (1X) exposure machine (steppers). Or scanners (scanners) for exposure and development.

Another way to form the photoresist layer 158 can also remove the original photoresist layer 120 first, and then form the photoresist layer 158 on the seed layer 40 and the metal layer 156, and through exposure (exposure) and development (development) ) process to pattern the photoresist layer 158 to form a photoresist layer opening 158a in the photoresist layer 158 and expose the metal layer 156 above the polymer bump 114, as shown in FIG. 10d.

Continuing as shown in FIG. 10e, a metal layer 160 is electroplated on the metal layer 156 in the opening 158a of the photoresist layer. The material of the metal layer 160 is, for example, a tin-containing metal, a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy layer. , lead-free solder, etc., the thickness of the metal layer 160 is between 1 micron and 300 microns, preferably between 5 microns and 200 microns.

Referring to FIG. 10f, the patterned photoresist layer 158 and the photoresist layer 120 are removed, and the seed layer 118 and the adhesion barrier layer 116 not under the metal layer 156 are removed.

Referring to FIG. 10g, a reheating process is performed to make the metal layer 160 reach the melting point and cohere into a spherical shape.

Referring to FIG. 10h, the substrate 10 is subjected to a dicing step to produce several semiconductor chips (chips) 126, and the metal layer 160 on the semiconductor chips 126 can be bonded to another external substrate.

The above description is only illustrative of the present invention, rather than restrictive. Those of ordinary skill in the art understand that many modifications, changes or equivalents can be made without departing from the spirit and scope defined in the claims, but All will fall within the scope defined by the claims of the present invention.

Claims (31)

1. A line assembly, characterized in that, comprising: A first semiconductor substrate, the first semiconductor substrate has at least one first metal pad; a first protective layer located on the first semiconductor substrate, the first protective layer has at least one opening exposing the first metal pad; A first metal layer, located on the first protective layer and electrically connected to the first metal pad, the first metal layer has a first bonding pad and a second bonding pad pad; a first bonding wire, located on the first bonding pad and connected to a first external circuit; and A second bonding wire is located on the second bonding pad and connected to a second external circuit. 2. The circuit assembly according to claim 1, wherein the first semiconductor substrate comprises a first fine interconnect structure, and the first fine interconnect structure comprises: A plurality of first dielectric layers with a thickness less than 3 microns are located on the semiconductor substrate, and the first dielectric layer has a plurality of first via holes; and a plurality of first thin circuit layers with a thickness less than 3 microns, and the first thin circuit layer is located on one of the first dielectric layers, wherein the first fine circuit layer relies on the The first via holes are electrically connected to each other. 3. The circuit assembly according to claim 2, wherein the first thin circuit layer comprises an aluminum layer or a copper layer with a thickness between 0.05 microns and 2 microns. 4 . The circuit assembly according to claim 1 , wherein the material of the first protective layer comprises one of a silicon nitride compound and a silicon oxide compound or a combination thereof. 5. The circuit assembly according to claim 1, wherein the material of the first metal layer includes gold. 6. The circuit assembly according to claim 1, wherein the material of the first metal layer comprises copper. 7. The wiring assembly according to claim 1, wherein the material of the first metal layer comprises one of silver, platinum, palladium and nickel or a combination thereof. 8. The circuit assembly according to claim 1, wherein the thickness of the first metal layer is between 1 micron and 20 microns. 9. The circuit assembly according to claim 1, characterized in that: the first wire bonding pad and the second wire bonding pad and the first metal pad are seen from a top perspective view 28 in different positions. 10. The circuit assembly according to claim 1, wherein a first adhesion/barrier layer is further provided between the first metal layer and the first metal pad. 11 . The circuit assembly according to claim 10 , wherein the first adhesion/barrier layer comprises a titanium-tungsten alloy layer or a titanium metal layer with a thickness ranging from 0.02 μm to 0.8 μm. 12. The circuit assembly according to claim 10, characterized in that: a seed layer is provided between the first adhesive/barrier layer and the first metal layer, and the seed layer and the The first metal layer is the same material. 13. The circuit assembly according to claim 1, wherein the first semiconductor substrate comprises an active component, and the active component is located on the first bonding pad or the second bonding pad. below the wire pad. 14. The circuit component according to claim 13, wherein the active component comprises a transistor. 15. The circuit assembly according to claim 1, wherein the first external circuit and the second external circuit include semiconductor chips, printed circuit boards, metal substrates, glass substrates, flexible substrates and ceramics one of the substrates. 16. The circuit assembly according to claim 1, wherein a polyimide compound layer is further provided between the protective layer and the first metal layer, and its thickness is between 2 microns and 100 microns between. 17. The circuit assembly according to claim 1, wherein a second polymer layer is further provided on the first metal layer, and the thickness thereof is between 2 micrometers and 100 micrometers. 18. A line assembly, characterized in that it comprises: A first semiconductor substrate, a first protective layer is located on the first semiconductor substrate, at least one first opening of the first protective layer exposes a first pad of the first semiconductor substrate, and a first metal layer is located on the first protective layer and connected to the first pad through the first opening, and the first metal layer includes a plurality of first bonding pads; A second semiconductor substrate, located on the first semiconductor substrate and exposing at least one side of the first semiconductor substrate and the first bonding pad, and a second protection layer located on the first semiconductor substrate On the second semiconductor substrate, at least one second opening of the second protection layer exposes a second pad of the second semiconductor substrate, and a second metal layer is located on the second protection layer and connecting the second pad through the second opening, the second metal layer includes a plurality of second bonding pads; A third semiconductor substrate, located on the second semiconductor substrate and exposing at least one side of the second semiconductor substrate and the second bonding pad, and a third protection layer located on the second semiconductor substrate On the third semiconductor substrate, at least one third opening of the third protection layer exposes a third pad of the third semiconductor substrate, and a third metal layer is located on the third protection layer and connecting the third pad through the third opening, the third metal layer includes a plurality of third bonding pads; A fourth semiconductor base, located on the third semiconductor base and exposing at least one side of the third semiconductor base and the third bonding pad, and a fourth protection layer located on the third semiconductor base On the fourth semiconductor substrate, at least one fourth opening of the fourth protective layer exposes a fourth pad of the fourth semiconductor substrate, and a fourth metal layer is located on the fourth protective layer and connecting the fourth pad through the fourth opening, the fourth metal layer includes a plurality of fourth bonding pads; Several bonding wires are located on the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad, so that the The first bonding pad and the second bonding pad, the second bonding pad and the third bonding pad, the third bonding pad and the The fourth bonding pads are connected to each other via the bonding wires; and An external circuit, connected to the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad through the bonding wire at least one of the pads. 19. The circuit assembly according to claim 18, wherein the first semiconductor substrate, the second semiconductor substrate, the third semiconductor substrate and the fourth semiconductor substrate respectively comprise a Fine online structure, described fine online structure includes: a plurality of dielectric layers with a thickness of less than 3 microns are respectively located on the first semiconductor substrate, the second semiconductor substrate, the third semiconductor substrate and the fourth semiconductor substrate, and the The dielectric layer has a plurality of via holes; and Several thin circuit layers with a thickness less than 3 microns, and the thin circuit layers are located on one of the dielectric layers, wherein the thin circuit layers are electrically connected to each other by the via holes. 20. The circuit assembly according to claim 19, wherein the thin circuit layer comprises an aluminum layer or a copper layer with a thickness between 0.05 microns and 2 microns. 21. The circuit assembly according to claim 18, wherein the material of the first protective layer, the second protective layer, the third protective layer and the fourth protective layer includes One or a combination of a silicon nitrogen compound and a silicon oxide compound. 22. The wiring assembly according to claim 18, wherein the material of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer comprises gold. 23. The wiring assembly according to claim 18, wherein the material of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer comprises One or a combination of copper, silver, platinum, palladium and nickel. 24. The circuit assembly according to claim 18, wherein the thicknesses of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are respectively Between 1 micron and 20 microns. 25. The circuit assembly according to claim 18, wherein the thicknesses of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are respectively Between 1.5 microns and 15 microns. 26. The circuit assembly according to claim 18, wherein the first metal layer and the first pad, the second metal layer and the second pad, the third An adhesion/barrier layer is respectively provided between the metal layer and the third pad, and between the fourth metal layer and the fourth pad. 27. The circuit assembly according to claim 26, wherein the adhesion/barrier layer comprises a titanium-tungsten alloy layer or a titanium metal layer with a thickness ranging from 0.02 μm to 0.8 μm. 28. The circuit assembly according to claim 27, characterized in that: the adhesive/barrier layer and the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are respectively A seed layer is provided. 29. The circuit assembly according to claim 18, wherein the external circuit comprises one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate and a semiconductor chip. 30. The circuit assembly according to claim 18, characterized in that: the first protection layer and the first metal layer, the second protection layer and the second metal layer, the A first polymer layer is arranged between the third protection layer and the third metal layer and the fourth protection layer and the fourth metal layer, and the thickness of the polymer layer is between Between 2 microns and 100 microns, which includes polyimide compounds. 31. The circuit assembly according to claim 18, characterized in that: the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are respectively provided with There is a second polymer layer, the thickness of the second polymer layer is between 2 microns and 100 microns, which includes polyimide compound.

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