CN101231998B - a circuit assembly - Google Patents

Abstract

The invention provides a circuit component structure, which enables an internal circuit below a protective layer to transmit signals to a plurality of components or circuit units on the same chip through a metal circuit or plane above the protective layer, or distributes power supply voltage or ground reference voltage to a plurality of components or circuit units on the same chip through the metal circuit or plane above the protective layer.

Description

a circuit assembly

technical field

What the present invention relates to is a kind of circuit component, what particularly relate to is a kind of on an integrated circuit (integrated circuit, IC) chip, utilizes the metal circuit or the plane that forms above the passivation layer (passivation layer) to pass the signal from a chip built-in circuit The (on-chip circuit) unit transmits to other circuit units, or the structure and method for transmitting power supply voltage or ground reference voltage to other circuit units.

Background technique

Many of today's electronic components need to operate at a high speed and/or low power consumption. In addition, current electronic systems, modules or circuit boards contain many different types of chips, such as central processing units (Central Processing Units, CPUs), digital signal processors (Digita Signal Processors, DSPs), analog chips (analog chip), dynamic random access memory (DRAMs), static random access memory (SRAMs) or flash memory (Flashs), etc. Each chip is fabricated using a different type and/or generation of integrated circuit processing technology. For example, in today's notebook personal computer (notebook personal computer), the central processing unit may use an advanced 65 nanometer (nm) technology to manufacture, its power supply voltage is 1.2 volts (V), and the analog chip uses a 0.25 micron ( μm) integrated circuit processing technology to manufacture, its power supply voltage is 3.3 volts, dynamic random access memory chip is manufactured using a 90 nanometer integrated circuit processing technology, its power supply voltage is 1.5 volts, and the flash memory chip uses a 0.18 micron technology, its power supply voltage is 2.5 volts. Since there are multiple supply voltages in a single system, an on-chip voltage regulator, a voltage converter, or a circuit design including voltage regulation and transformation is required, For example, a DRAM chip requires an on-chip transformer to convert 3.3 volts to 1.5 volts, while a flash memory chip requires an on-chip transformer to convert 3.3 volts to 2.5 volts. Among them, the on-chip voltage regulator, transformer or circuit design including voltage stabilization and voltage transformation provide a stable voltage to semiconductor components at different positions on the same chip through the on-chip power/ground reference voltage bus (power/ground bus) . In addition, if a low-resistance power supply/ground reference voltage line is added to a chip built-in voltage stabilizer, transformer, or circuit design including voltage stabilization and voltage transformation, it can not only minimize energy consumption, but also reduce the load due to Noise caused by capacitance and resistance fluctuations.

In US Pat. No. 6,495,442, it discloses a post-passivation structure on top of a wafer. The back cover structure on the IC protection layer is used as a global, power supply, ground reference voltage or signal distribution network. Wherein, the power/ground reference voltage comes from an external (outside the chip) power supply.

U.S. Patent No. 6,649,509 discloses an embossing process for forming a post-passivation interconnection structure on the protective layer of an integrated circuit, which can be used as a power supply, ground reference voltage, frequency (clock) or a comprehensive distribution network for signals.

Contents of the invention

One object of the present invention is to enable the built-in circuit unit under the passivation to transmit signals to several components or circuit units on the same chip (IC chip) through metal lines or planes on the passivation.

An object of the present invention is to enable the on-chip voltage regulator under the protection layer to transmit power to several components or circuit units on the same chip through the metal lines or planes on the protection layer.

An object of the present invention is to enable the on-chip transformer under the protection layer to transmit power to several components or circuit units on the same chip through the metal lines or planes on the protection layer.

It is an object of the present invention to reduce the loss of signals transmitted to several components or circuit units due to parasitic effects.

It is an object of the present invention to reduce the loss of power transmitted to several components or circuit units due to parasitic effects.

It is an object of the present invention to transmit power to several components or circuit units through the protective layer openings and metal circuits or planes formed on the protective layer.

An object of the present invention is to distribute a signal, power supply, or ground reference voltage output from at least one internal circuit or internal component to at least one other internal circuit or internal component through metal lines or planes on the protective layer.

An object of the present invention is to distribute a signal, power supply, or ground reference voltage output from at least one internal circuit or internal component to at least one other internal circuit or internal component through metal lines or planes on the protective layer without Connect to electrostatic discharge (ESD) protection circuits, driver circuits, or receiver circuits.

An object of the present invention is to distribute a signal, power supply, or ground reference voltage output from at least one internal circuit or internal component to at least one other internal circuit or internal component through metal lines or planes on the protective layer without Connect to external (outside chip) circuitry.

One object of the present invention is to transmit signals generated by internal circuits or internal components to external circuits through the fine-line metal structure under the protective layer and the metal lines or planes on the protective layer.

An object of the present invention is to distribute a signal, power supply, or ground reference voltage output from at least one internal circuit or internal component to at least one other internal circuit or internal component through metal lines or planes on the protective layer, and to protect The contact structures on the layer are respectively connected to an off-chip circuit and an external circuit.

It is an object of the present invention to distribute power and ground reference voltages from an external power supply to internal circuits and a contact structure to the external power supply through metal lines or planes on the protective layer.

According to the object of the present invention, a circuit assembly includes a metal line or plane on a protective layer, and the metal line or plane can be used to distribute the voltage and/or current output from a voltage regulator to the internal circuit.

According to the purpose of the present invention, a line component includes a metal line or plane on a protective layer, and can use this metal line or plane to distribute a signal, power, or ground reference voltage output from at least one internal circuit or internal component to at least one - another internal circuit or internal component.

According to the object of the present invention, a circuit assembly includes a metal line or plane on a protective layer, which metal line or plane can distribute a signal, power, or ground reference voltage output from at least one internal circuit or internal component to at least one other An internal circuit or internal component, and uses a contact structure on a protective layer to connect a chip with an external circuit to an external circuit.

According to the object of the present invention, a circuit assembly comprises a metal line or plane on a protective layer, and uses this metal line or plane to distribute the power and ground of an external power supply to the internal circuit and a contact structure to the external power supply reference voltage.

In order to achieve the above object, the technical solution adopted by the present invention is that the first solution provides a line assembly, a line assembly, which includes:

an internal circuit;

A chip connected to an external circuit, including an output node connected to an external circuit;

a first metal line, connected to an output node of the internal circuit;

A second metal line, connected to an input node of the chip connected to an external circuit;

a protective layer, located on the internal circuit, the external circuit of the chip, the first metal line and the second metal line; and

A third metal circuit is located on the protection layer and connects the first metal circuit and the second metal circuit.

Scheme 2 provides a line assembly, a line assembly, which includes:

A first metal oxide semiconductor device, the channel width to channel length ratio of the first metal oxide semiconductor device is between 0.1 and 10;

a second metal oxide semiconductor component;

a first metal line, connected to the first metal oxide semiconductor component;

a second metal line, connected to the second metal oxide semiconductor device;

a protection layer located on the first metal oxide semiconductor component, the second metal oxide semiconductor component, the first metal line and the second metal line; and

A third metal circuit is located on the protection layer and connects the first metal circuit and the second metal circuit.

Solution 3 provides a line assembly, a line assembly, which includes: an electrostatic discharge protection circuit, including a power node and a ground node;

an internal circuit including a power node and a ground node;

a first metal line, connected to the power node of the internal circuit;

a second metal line connected to the ground node of the internal circuit;

A third metal line, connected to the power node of the electrostatic discharge protection circuit;

A fourth metal line, connected to the ground node of the electrostatic discharge protection circuit;

A protective layer, located on the electrostatic discharge protection circuit, the internal circuit, the first metal circuit, the second metal circuit, the third metal circuit and the fourth metal circuit superior;

a fifth metal line, located on the protection layer, and connected to the first metal line and the third metal line; and

A sixth metal circuit is located on the protection layer and connects the second metal circuit and the fourth metal circuit.

Description of drawings

FIG. 1A is a schematic diagram of an existing circuit with a voltage regulator or transformer;

FIG. 1B is a schematic circuit diagram of a voltage regulator or a transformer of the present invention;

Fig. 1C is a schematic circuit diagram of the present invention using metal lines or planes above the protective layer to transmit the voltage Vcc and the ground reference voltage Vss structure;

FIG. 2A is a schematic top view of a conventional voltage regulator or transformer;

FIG. 2B is a schematic top view of a voltage stabilizer or transformer of the present invention;

FIG. 2C is a schematic top view of the structure of the present invention utilizing metal lines or planes above the protective layer to transmit the voltage Vcc and the ground reference voltage Vss;

FIG. 3A is a schematic cross-sectional view of a conventional voltage regulator or transformer;

3B is a schematic cross-sectional view of a voltage stabilizer or transformer of the present invention;

3C is a schematic cross-sectional view of the structure of the present invention using the metal line or plane above the protective layer to transmit the voltage Vcc and the ground reference voltage Vss;

3D is a schematic cross-sectional view of a voltage stabilizer or transformer of the present invention;

Fig. 4 is the transformer of the present invention;

5A is a schematic circuit diagram of an existing internal circuit;

5B is a schematic circuit diagram of the second embodiment of the present invention;

Fig. 5C is the inverter of the present invention;

Figure 5D is the internal driver of the present invention;

FIG. 5E is an internal tri-state buffer of the present invention;

5F is a schematic circuit diagram of a memory unit connected to an internal circuit through an internal tri-state buffer, metal lines or planes on the protective layer, and thin line metal structures under the protective layer of the present invention;

5G is a schematic circuit diagram of a memory unit of the present invention connected to an internal circuit through the circuit, the metal line or plane on the protective layer, and the thin line metal structure under the protective layer;

5H is a schematic circuit diagram of a memory cell connected to an internal circuit through a latch circuit, metal lines or planes on the protective layer, and thin line metal structures under the protective layer according to the present invention;

5I is a schematic circuit diagram of a memory cell connected to an internal circuit through a pass circuit, an internal driver, a metal line or a plane on the protective layer, and a thin line metal structure under the protective layer according to the present invention;

5J is a schematic circuit diagram of a memory cell connected to an internal circuit through a latch circuit, an internal driver, a metal line or plane on the protective layer, and a thin line metal structure under the protective layer according to the present invention;

5K is a schematic circuit diagram of the second embodiment of the present invention;

Figure 5L is the internal receiver of the present invention;

FIG. 5M is an internal tri-state buffer of the present invention;

5N is a schematic circuit diagram of an internal circuit connected to a memory unit through a metal structure of thin lines under the protective layer, metal lines or planes on the protective layer, and an internal tri-state buffer according to the present invention;

FIG. 50 is a circuit schematic diagram of an internal circuit of the present invention connected to a memory unit through the thin line metal structure under the protective layer, the metal line or plane on the protective layer, and the circuit;

5P is a schematic circuit diagram of an internal circuit connected to a memory unit through a metal structure of thin lines under the protective layer, metal lines or planes on the protective layer, and a latch circuit according to the present invention;

5Q is a schematic circuit diagram of an internal circuit of the present invention connected to a memory unit through a thin line metal structure under the protective layer, a metal line or plane on the protective layer, an internal receiver, and a circuit;

5R is a schematic circuit diagram of an internal circuit connected to a memory unit through a thin line metal structure under the protective layer, a metal line or plane on the protective layer, an internal receiver, and a latch circuit of the present invention;

FIG. 5S is a schematic circuit diagram of the present invention using metal lines or planes above the protective layer to connect analog circuits;

Fig. 5T is the operational amplifier of the present invention;

FIG. 6A is a schematic top view of an existing internal circuit;

6B is a schematic top view of the second embodiment of the present invention;

7A is a schematic cross-sectional view of an existing internal circuit;

7B is a schematic cross-sectional view of a single patterned metal layer according to the second embodiment of the present invention;

7C is a schematic cross-sectional view of a second embodiment of the present invention having two patterned metal layers;

7D is a schematic cross-sectional view of a polymer layer between the passivation layer and the bottommost patterned metal layer according to the second embodiment of the present invention;

FIG. 8A is a schematic circuit diagram of an existing wafer;

8B is a schematic circuit diagram of a third embodiment of the present invention;

8C is a schematic circuit diagram of a third embodiment of the present invention;

8D is a schematic circuit diagram of a third embodiment of the present invention;

8E is a schematic circuit diagram of a third embodiment of the present invention;

FIG. 8F is a schematic circuit diagram of a third embodiment of the present invention;

FIG. 9A is a schematic top view of an existing wafer;

9B is a schematic top view of the third embodiment of the present invention;

9C is a schematic top view of the third embodiment of the present invention;

FIG. 9D is a schematic top view of the third embodiment of the present invention;

10A is a schematic cross-sectional view of an existing wafer;

10B is a schematic cross-sectional view of a single-layer patterned metal layer according to the third embodiment of the present invention;

10C is a schematic cross-sectional view of a third embodiment of the present invention having two patterned metal layers;

10D is a schematic cross-sectional view of a third embodiment of the present invention having a polymer layer between the passivation layer and the bottommost layer of the single-layer patterned metal layer;

10E is a schematic cross-sectional view of a third embodiment of the present invention having a polymer layer between the passivation layer and the bottommost layer of the two patterned metal layers;

10F is a schematic cross-sectional view of a conventional wafer with a wire bond;

10G is a schematic cross-sectional view of a third embodiment of the present invention with a wire bonding;

10H is a schematic cross-sectional view of a third embodiment of the present invention with a wire bonding;

10I is a schematic cross-sectional view of a third embodiment of the present invention with a wire bonding;

Fig. 11A is a chip connected with an external driver of the present invention;

FIG. 11B is a chip connected to an external receiver of the present invention;

Fig. 11C is a chip tri-state buffer of the present invention;

FIG. 11D is a chip connected to an external driver of the present invention;

Fig. 11E is the chip tri-state buffer of the present invention;

Fig. 11F is the electrostatic discharge protection circuit of the present invention;

Fig. 11G is the serial driver of the present invention;

12A is a schematic circuit diagram of an existing external power supply directly inputting voltage to the internal circuit and having an electrostatic discharge protection circuit to prevent voltage or current surges generated by the external power supply;

12B is a schematic circuit diagram of a fourth embodiment of the present invention;

12C is a schematic circuit diagram of a fourth embodiment of the present invention;

FIG. 12D is a schematic circuit diagram with two electrostatic discharge protection circuits according to the fourth embodiment of the present invention;

Fig. 12E is the electrostatic discharge protection circuit of the present invention;

13A is a schematic top view of an existing external power supply directly inputting voltage to the internal circuit and having an electrostatic discharge protection circuit to prevent voltage or current surges generated by the external power supply;

13B is a schematic top view of a fourth embodiment of the present invention;

13C is a schematic top view of the fourth embodiment of the present invention;

14A is a schematic cross-sectional view of an existing external power supply directly inputting voltage to the internal circuit and having an electrostatic discharge protection circuit to prevent voltage or current surges generated by the external power supply;

14B is a schematic cross-sectional view of a fourth embodiment of the present invention;

14C is a schematic cross-sectional view of a fourth embodiment of the present invention;

14D is a schematic cross-sectional view of a fourth embodiment of the present invention;

15A is a schematic cross-sectional view of a wafer;

15B is a schematic cross-sectional view of a wafer;

15C to 15K are a processing step for forming the structure above the protective layer according to the present invention;

16A to 16L are a processing step for forming the structure above the protective layer according to the present invention;

17A to 17J are a processing step for forming the structure above the protective layer according to the present invention;

18A to 18I are a processing step for forming the structure above the protective layer according to the present invention;

19A to 19I are a processing step for forming the structure above the protective layer according to the present invention;

Fig. 20 is a schematic cross-sectional view of the present invention.

Explanation of reference signs: 1-substrate; 2-component layer; 2'-metal oxide semiconductor transistor; 5-protective layer; 6-thin line structure; 8-structure above the protective layer; 10-wafer; 10'-chip; 19-pad; 20 internal circuit; 21-internal circuit; 22 internal circuit; 23-internal circuit; 24 internal circuit; 30-thin line dielectric layer; 30' opening; 40-chip connected to external circuit; 41 voltage regulator 42- chip connected to external circuit; 43 chip connected to external circuit; 44- electrostatic discharge protection circuit; 45 electrostatic discharge protection circuit; 50- protective layer opening; 60 thin line metal layer; 60'- conductive plug; Line metal structure; 61'-fine line metal structure; 62 thin line metal structure; 63-fine line metal structure; 66 metal top layer; 69-fine line metal structure; 71 photoresist layer; 72-photoresist layer; layer; 74-photoresist layer; 80 patterned metal layer; 81-metal line or plane; 82 metal line or plane; 83-metal line or plane; 83r metal line or plane; 83t-reconfiguration metal line; 89 contact structure ; 89t-tin-lead bump; 90 polymer layer; 97-polymer layer; 98 polymer layer; 200-internal structure; 201 source; 202-drain; 203 gate; 211-inverter; 212 internal driver; 212'-internal receiver; 213 internal tri-state buffer; 213'-internal tri-state buffer; 214 sense amplifier; 215-SRAM unit; Latch circuit; 217'-latch circuit; 218 operational amplifier; 219-differential circuit; 400-chip external structure; 410-reference voltage generator; 410'current mirror circuit; 421-chip external driver; 1st level; 421"-second level; 422 chip connected to external receiver; 422'-first level; 422"second level; 511-protective layer opening; 512 protective layer opening; 514-protective layer opening; 519 protective layer Opening; 519'-protective layer opening; 521 protective layer opening; 522-protective layer opening; 524 protective layer opening; 529-protective layer opening; 531 protective layer opening; 531'-protective layer opening; 532 protective layer opening; 532' - cover opening; 534 cover opening; 534' - cover opening; 539 cover opening; 539' - cover opening; 549 cover opening; 549' - cover opening; 559 cover opening; 559' - protection Layer opening; 600 metal pad; 601w-fine line metal layer; 602 fine line metal layer; 602x-fine line metal layer; 602y fine line metal layer; 602z-fine line metal layer; Line metal structure; 612a thin line metal structure; 612b-fine line metal structure; 612c thin line metal structure; 614-fine line metal structure; 618 thin line Metal structure; 619-fine line metal structure; 619'fine line metal structure;621-fine line metal structure;622fine line metal structure;622a-fine line metal structure;622bfine line metal structure;622c-fine line metal structure; 624 thin line metal structure; 629-fine line metal structure; 631 thin line metal structure; 631'-fine line metal structure; 632 thin line metal structure; 632a-fine line metal structure; Metal structure; 632a' thin line metal structure; 632b'-fine line metal structure; 632c' thin line metal structure; 634-fine line metal structure; 634' thin line metal structure; Structure; 639'-fine line metal structure; 649 thin line metal structure; 649'-fine line metal structure; 659 fine line metal structure; 659'-fine line metal structure; 661 metal top layer; 669-metal top layer 669' metal top layer; 710-photoresist opening; 720 photoresist opening; 720'-photoresist opening; 730 photoresist opening; 730'-photoresist opening; 740'-photoresist layer opening; 801 patterned metal layer; 801a-patterned metal layer; 801b patterned metal layer; 801w-patterned metal layer; 802 patterned metal layer; 802x-patterned metal layer; 802y patterned Metal layer; 802z-patterned metal layer; 803 patterned metal layer; 811-patterned metal layer; 812 patterned metal layer; 821-patterned metal layer; 831 patterned metal layer; 831a-patterned metal layer; 831b patterned metal layer; 832-patterned metal layer; 832a patterned metal layer; 832b-patterned metal layer; 891 bump bottom metal layer; 897-metal plug; 897' metal layer; 898-metal plug; layer; 950-polymer layer opening; 980 polymer layer opening; 990-polymer layer opening; 2101-N type metal oxide semiconductor transistor; 2102-P type metal oxide semiconductor transistor; '-N-type metal-oxide-semiconductor transistor; 2104-P-type metal-oxide-semiconductor transistor; 2104'-P-type metal-oxide-semiconductor transistor; 2107-N-type metal-oxide-semiconductor transistor; 2110'-P-type MOS transistor; 2111-N-type MOS transistor; 2112P-type MOS transistor; 2113-N-type MOS transistor; 2114-P-type MOS transistor; 2115-N metal oxide semiconductor transistor; 2116-P metal oxide semiconductor transistor; 2117-N metal oxide semiconductor transistor; 2118-P metal oxide semiconductor transistor; 2119-N metal oxide semiconductor transistor; 2120-N MOS transistor; 2121-N MOS transistor; 2122-row selection transistor; 2123-row selection transistor; 2124-N MOS transistor; 2124'-N MOS transistor; 2125-N type MOS transistor; 2126-P MOS transistor; 2127-N MOS transistor; 2128-P MOS transistor; 2129-N MOS transistor; 2129'-N MOS transistor ;2130-N MOS transistor; 2130'-N MOS transistor; 2131-P MOS transistor; 2132-P MOS transistor; 2133-capacitor; 2134-resistor; 2135-N MOS transistor; 2136-P MOS transistor; 4101-P MOS transistor; 4102-P MOS transistor; 4103-P MOS transistor; 4104-P MOS transistor ;4105-P MOS transistor; 4106-P MOS transistor; 4107-N MOS transistor; 4108-N MOS transistor; 4109-P MOS transistor; 4110-P type Metal oxide semiconductor transistor; 4111-conductance transistor; 4112-conductance transistor; 4199-node; 4201-N type metal oxide semiconductor transistor; 4202-P type metal oxide semiconductor transistor; 4203-N type metal oxide semiconductor transistor; Metal oxide semiconductor transistor; 4205-N metal oxide semiconductor transistor; 4206-P metal oxide semiconductor transistor; 4207-N metal oxide semiconductor transistor; 4208-P metal oxide semiconductor transistor; 4209-N metal oxide semiconductor transistor; 4210-P-type metal oxide semiconductor transistor; 4331-reverse bias diode; 4332-reverse bias diode; 4333-pass bias diode; 6111-fine line metal structure; 6121-fine line metal structure; 6121a-fine line metal structure ;6121b-fine line metal structure;6121c-fine line metal structure;6141-fine line metal structure;6190-metal pad;6190'-metal pad;6290-metal pad;6191-fine line metal structure;6311- 6321-fine line metal structure; 6321a-fine line metal structure; 6321b-fine line metal structure; 6321c-fine line metal structure; 6341-fine line metal structure; 6390-metal pad; 6391-fine line Metal structure; 6391'-fine line metal structure; 6490-metal pad; 6490'-metal pad; 8011'-recess; 8011a-adhesion/barrier/seed layer; 8011b-adhesion/barrier/seed layer; 8012a-thick metal layer; 8012b-thick metal layer; 8021-adhesion/barrier/seed layer; 8022-thick metal layer; 8031-adhesion/barrier/seed layer; 8032-thick metal layer; 8110-contact pad; 811 1-adhesion/barrier/seed layer; 8112-thick metal layer; 8120-contact pad; 8121-adhesion/barrier/seed layer; 8122-thick metal layer; 8211-adhesion/barrier/seed layer; 8212- thick metal layer; 8310-contact pad; 8311-adhesion/barrier/seed layer; 8311a-adhesion/barrier/seed layer; 8311b-adhesion/barrier/seed layer; layer; 8312b-thick metal layer; 8320-contact pad; 8321-adhesion/barrier/seed layer; 8321a-adhesion/barrier/seed layer; 8321b-adhesion/barrier/seed layer; 8322-thick metal layer; 8322a-thick metal layer; 8322b-thick metal layer; 9511-polymer layer opening; 9512-polymer layer opening; 9514-polymer layer opening; 9519-polymer layer opening; 9519'-polymer layer opening; 9532-polymer layer opening; 9534-polymer layer opening; 9539-polymer layer opening; 9539'-polymer layer opening; 9549-polymer layer opening; 9829-polymer layer opening; 9831- 9834-polymer layer opening; 9839-polymer layer opening; 9849'-polymer layer opening; 9919-polymer layer opening; 9929-polymer layer opening; 9939-polymer layer opening; 9939' - polymer layer opening; 9949 - polymer layer opening; 9949' - polymer layer opening.

Detailed ways

The above and other technical features and advantages of the present invention will be described in more detail below in conjunction with the accompanying drawings.

The circuit assembly of the present invention includes a monolithic wafer, a chip, or a packaged monomer.

First Embodiment: Connect the over-paeeivation power/ground reference voltage bus of a voltage regulator or transformer.

Please refer to FIG. 1B to FIG. 1C , FIG. 2B to FIG. 2C and FIG. 3B to FIG. 3D at the same time, which disclose the first embodiment of the present invention. Wherein, Fig. 1B and Fig. 1C present a simplified schematic circuit diagram, which utilizes metal lines or planes 81 and/or metal lines or planes 82 on the protective layer 5 to connect voltage regulators (voltage regulator) or transformers (voltage converters) 41 and the internal circuit 20 (including 21, 22, 23, 24), and use this metal line or plane 81 and/or metal line or plane 82 to distribute the voltage output by a voltage regulator or transformer 41 and/or a grounding reference voltage. FIG. 2B and FIG. 2C respectively present a schematic top view of the circuit shown in FIG. 1B and FIG. 1C . FIG. 3B and FIG. 3C are schematic cross-sectional views of the circuits shown in FIG. 1B and FIG. 1C , respectively. In addition, in the series of Fig. 1 and Fig. 2, the protective layer 5 is represented by a dotted line, the circuit or plane formed on the protective layer 5 is represented by a "thick line", while the circuit formed under the protective layer 5 is represented by a "thin line". line", and this representation is also applicable to all embodiments of the present invention.

In this embodiment, the power is transmitted to several components (circuits) on the same integrated circuit chip (integrated circuit, IC) by means of a built-in voltage regulator or transformer 41 via metal lines or planes above the protective layer. . Through metal lines or planes deposited on the protective layer, power can be delivered with low losses to several components or circuit units. Such a design of adding regulation voltage and using the metal line or plane above the protection layer to transmit the voltage can precisely control the voltage level output to the internal circuit at a voltage level. In addition, the output voltage of the voltage stabilizer is between plus or minus 10% of a set target voltage in the voltage stabilizer (that is, when the voltage stabilizer outputs a voltage value, the voltage value is between this voltage value and the set target voltage value. The percentage of the difference divided by the set target voltage value is less than 10%), and it is better to be between plus and minus 5% of the set target voltage, where the set target voltage value of the regulator is such as Between 0.5 volts and 10 volts or between 0.5 volts and 5 volts. Therefore, by means of this method, the input node (input node) can be prevented from being subjected to voltage surges or large voltage fluctuations generated by an external power supply, and thus the circuit performance can be improved through this design. However, in some applications, since the chip requires a voltage different from that provided by the external power supply, in addition to the voltage regulator, a transformer is also required to convert the voltage provided by the external power supply into the required voltage in the chip. voltage. This transformer can convert an input voltage into an output voltage, and the output voltage is different from the input voltage, and the percentage of the difference between the input voltage and the output voltage divided by the output voltage is greater than 10%, wherein the output voltage is, for example, between 1 volt to 10 volts or between 1 volt and 5 volts. In addition, the type of the transformer can be a step-down transformer or a boost transformer.

1A, 2A and 3A disclose a circuit diagram, a top view diagram and a cross-sectional diagram showing how a voltage regulator or transformer 41 is connected to the internal circuit 20 (including 21 , 22 , 23 and 24 ). This prior art utilizes fine line metal structures 619, 6191 and 61 (including 618, 6111, 6121 and 6141, 6121 including 6121a, 6121b and 6121c) under the protection layer 5 to enable the voltage regulator or transformer 41 to accept external supply The power supply inputs a voltage Vdd, outputs a voltage Vcc, and transmits the voltage Vcc to the internal circuit 20 (including 21 , 22 , 23 and 24 ). However, the fine line metal structure 61 under the passivation layer 5 and fabricated using wafer processing and materials cannot easily provide a thick metal layer (eg, a metal layer with a thickness of 5 microns) or a thick dielectric layer (eg, a thickness of 5 microns). micron dielectric layer). In addition, the high resistance per unit length and high capacitance per unit length of the fine line metal layer will lead to power supply voltage drop (IR voltage drop), noise (noises), signal distortion (signal distortion), propagation time delay (propagation time delay), high power consumption (high power consumption) and high heat generation (high heat generation).

Please refer to FIG. 1B , which is a schematic circuit diagram of the first embodiment of the present invention. In this embodiment, a voltage regulator or transformer 41 receives the voltage Vdd input from the external power supply through the protective layer opening 519 and the thin line metal structure 619, and outputs a voltage Vcc to the internal circuit 20 (including 21, 22, 23 and twenty four). The voltage Vcc output by the voltage stabilizer or transformer 41 at the node P is distributed to the voltage nodes Tp, Up, Vp, Wp of the internal circuits 21, 22, 23, 24 in the following way, firstly through the thin wire metal structure 619' to Pass through the protective layer opening 519' located in the protective layer 5, then pass through a metal line or plane 81 on the protective layer 5, then pass through the protective layer openings 511, 512, 514, and then pass through the thin line metal structure 61' (including 611, 612, 614, wherein 612 includes 612a, 612b, 612c) to the internal circuit 20, wherein to the internal circuit 21 through the thin line metal structure 611; to the internal circuit 22 through the thin line metal structure 612a and the thin line metal structure 612b; The internal circuit 23 is passed through the thin-line metal structure 612 a and the thin-line metal structure 612 c , and the internal circuit 24 is passed through the thin-line metal structure 614 .

In addition, the internal circuit 20 (including 21, 22, 23, 24) is composed of at least one metal oxide semi-transistor (MOS transistor), and the above-mentioned thin line metal structure is connected to the internal circuit 20 (including 21, 22, 23, 24 ) metal-oxide-semiconductor transistor, such as connected to the source of the metal-oxide-semiconductor transistor (source), and this metal-oxide-semiconductor transistor can have a "channel width (Channel width)/channel length (Channel length)" ratio between 0.1 and 5 or an NMOS transistor between 0.2 and 2, or a "channel width/channel length" ratio between 0.2 and 10 or between 0.4 and 4 P-type metal oxide semiconductor transistor (PMOStransistor). In addition, the current flowing through the metal line or plane 81 is between 50 microampere and 2 milliampere or between 100 microampere and 1 milliampere.

Therefore, the structure shown in FIG. 1B is to use a metal line or plane 81 as a power supply line or plane. In addition, because the metal line or plane 81 on the protective layer 5 is a thick metal conductor, the thick metal conductor has the advantage of low resistance , so the voltage drop (voltage drop) generated by the metal line or the plane 81 can be greatly reduced, and the power supply voltage provided by the metal line or the plane 81 can be stabilized.

1B to 1C, 2B to 2C and 3B to 3D, the internal circuit 20 includes an internal circuit 21, an internal circuit 22, an internal circuit 23 and an internal circuit 24, wherein the internal circuits 22 and 24 are NOR gates (NOR gate), and the internal circuit 23 is a NAND gate (NAND gate), and each of the NOR gate and the NAND gate has three input nodes Ui, Wi, Vi, an output node Uo, Wo, Vo, and a voltage Vcc power supply nodes Up, Wp, Vp and a ground reference voltage Vss ground nodes Us, Ws, Vs, while the internal circuit 21 has an input node Xi, an output node Xo, a voltage Vcc power supply node Tp and a ground reference voltage Vss ground node Ts. Therefore, the internal circuit 20 (including 21 , 22 , 23 and 24 ) usually has a signal node, a power node and a ground node. However, the internal circuit 20 (including 21, 22, 23 and 24) can also be any type of integrated circuit, and the content of this part will be described in the subsequent series of Figure 15. The internal circuit 20 (including 21, 22, 23 and 24); and some application examples of the internal circuit 21 will be described in the following FIGS. 5C to 5J and 5M to 5R.

Please refer to FIG. 2B and FIG. 3B at the same time, which are respectively a schematic top view and a schematic cross-sectional view shown in FIG. 1B of the present invention. In FIG. 3B , the fine-line metal structures 611, 612, 614, 619, 619' can be formed by the thin-line metal layer 60 and the conductive plugs 60' filled in the opening 30', for example, in a roughly aligned manner. Formed in a stacking manner, that is to say, the upper and lower openings 30' are roughly aligned, the upper and lower thin line metal layers 60 are roughly aligned, and the upper and lower conductive plugs 60' are also roughly aligned. In addition, the fine line metal layers 60 are separated by the thin line dielectric layer 30 (such as silicon oxide), and the description about the above thin line metal structure is also applicable to all embodiments of the present invention. In FIG. 2B, the metal line or plane 81 on the protective layer 5 may be a single-layer patterned metal layer (such as the patterned metal layer 811 in FIG. 3B ) or a multi-layer patterned metal layer (not shown), and when When the metal line or plane 81 is a multi-layer patterned metal layer, the patterned metal layers are separated by a polymer layer, and the polymer layer can be polyimide (polyimide, PI), phenylcyclobutene (benzo cyclo butene, BCB), parylene (parylene), epoxy-based material (epoxy-based material), such as epoxy resin or photoepoxy SU-8 provided by Sotec Microsystems in Renens, Switzerland, elastic Material (elastomer), such as silicone (silicone). In addition, metal line or plane 81 includes an adhesion/barrier/seed layer (adhesion/barrier/seed layer) and a thick metal layer. For example, in FIG. 3B, patterned metal layer 811 includes an adhesion/barrier/seed layer layer 8111 and a thick metal layer 8112. The method for forming the metal circuit or the plane 81 and the detailed description of the metal circuit or the plane 81 will be described in the subsequent series of FIGS. 15 , 16 , 17 , 18 and 19 . In addition, the fine-line metal structure 612 includes a thin-line metal structure 612a, a thin-line metal structure 612b, and a thin-line metal structure 612c, which are used for distributing local power, and the metal lines or planes 81 are used for As global power distribution, it is connected to the thin line metal structure 61' (including 611, 612, 614) and the thin line metal structure 619'. Please refer to FIG. 1B, FIG. 2B and FIG. 3B at the same time. The external power supply provides a voltage Vdd at the contact pad 8110, and after passing through a protective layer opening 519 and a thin line metal structure 619, it is input to the voltage regulator or Transformer 41 , wherein the fine-line metal structure 619 includes a metal pad 6190 on the topmost layer of the thin-line metal layer 60 , and the metal pad 6190 is exposed through the protective layer opening 519 and connected to the contact pad 8110 .

The present invention utilizes a top polymer layer 99 to cover the metal line or plane 81, and this top polymer layer 99 may be polyimide, phenylcyclobutene, parylene, epoxy-based material (such as epoxy resin or photoepoxy SU-8), elastic material (such as silicone), such as shown in FIG. 3B , a patterned metal layer 811 covers a top polymer layer 99. In addition, a polymer layer 95 can also be selectively added between the protective layer 5 and the metal circuit or the plane 81. The polymer layer 95 can be polyimide, phenylcyclobutene, parylene, epoxy Base material (such as epoxy resin or photoepoxy SU-8), elastic material (such as silicone), such as shown in Figure 3D, a polymer layer 95 is added between the protective layer 5 and the patterned metal layer 811, wherein the polymer Layer openings 9519 , 9519 ′, 9511 , 9512 , 9514 are respectively aligned with protective layer openings 519 , 519 ′, 511 , 512 , 514 in protective layer 5 . In the present invention, the size of the bottom of the opening of the polymer layer may be smaller than the size of the opening of the protective layer below, and the polymer layer covers part of the exposed pads of the opening of the protective layer. For example, in FIG. 3D, the polymer layer opening 9519 The size of the bottom of , 9519' is smaller than the size of the openings 519, 519' of the protective layer below, and the polymer layer 95 covers the metal pads 6190, 6190' exposed by the openings 519, 519' of the protective layer. The size of the layer openings 519, 519' is between 20 microns and 100 microns, and the size of the polymer layer openings 9519, 9519' is between 20 microns and 100 microns; The size of the opening of the object layer can also be larger than the size of the opening of the protective layer below, and expose all the parts exposed by the opening of the protective layer through the opening of the polymer layer. For example, the sizes of the openings of the polymer layer 9511, 9512, and 9514 are is larger than the size of the lower protective layer openings 511, 512, 514, and the polymer layer openings 9511, 9512, 9514 respectively expose all parts exposed by the protective layer openings 511, 512, 514. In addition, the protective layer openings 511, 512, The size of 514 is between 10 microns and 50 microns, and the size of polymer layer openings 9511, 9512, 9514 is between 20 microns and 100 microns. The above descriptions are also applicable to all embodiments of the present invention.

In addition, the metal line or plane 81 used to distribute the stable or switching voltage Vcc can be a single-layer patterned metal layer (such as the patterned metal layer 811 shown in FIG. 3B ), or a polymer layer deposited on There are multiple patterned metal layers between each metal layer, and the patterned metal layers of different layers can be connected together through the openings between the polymer layers.

Again, please refer to Fig. 1A, Fig. 2A and Fig. 3A at the same time, which are related technologies in the prior art, as shown in the figure, the external power supply is to provide the input voltage required by the voltage stabilizer or transformer 41 in the following manner , which is: use the metal pad 6190 exposed by the protective layer opening 519 to receive the voltage Vdd input from the external power supply, then pass down the thin line metal structure 619 , and finally input the voltage Vdd to the voltage regulator or transformer 41 . Continuing, the output voltage Vcc of the voltage regulator or transformer 41 is distributed to the voltage Vcc nodes of the internal circuits 21 , 22 , 23 , 24 via the thin line metal structure 61 (including 618 , 6111 , 6121 , 6141 ). However, this prior art has the disadvantages of significant energy loss and speed reduction.

In FIG. 1B , FIG. 2B , FIG. 3B and FIG. 3D , the ground reference voltage is represented as Vss, but its circuit, layout and structure are not described in detail. Please refer to FIG. 1C, FIG. 2C and FIG. 3C at the same time, which are circuit schematic diagrams, top view schematic diagrams and cross-sectional schematic diagrams of the structure of the present invention using metal lines or planes above the protective layer to distribute voltage Vcc and ground reference voltage Vss. Wherein, except that the voltage stabilizer or transformer 41 and the internal circuit 20 (including 21, 22, 23, 24) share a ground reference voltage, that is, except the ground nodes Ts, Us of the internal circuit 20 and the voltage stabilizer or transformer 41 , Vs, Ws, and Rs are all connected to the same ground reference voltage node Es, and the structure and connection method of the ground reference voltage Vss are similar to the voltage Vcc mentioned above. In FIG. 1C, FIG. 2C and FIG. 3C, the ground node Es receiving the ground reference voltage Vss is connected to the voltage regulator or transformer 41 via the protective layer opening 529 of the protective layer 5 and the thin line metal structure 629 under the protective layer 5. Ground node Rs, and connected via metal line or plane 82 (patterned metal layer 821 in FIG. To the ground nodes Ts, Us, Vs, Ws of the internal circuits 21, 22, 23, 24.

Please refer now to FIG. 3C , which discloses two patterned metal layers 812 and 821 above the protection layer as a power/ground reference voltage structure, wherein the bottom patterned metal layer 821 is a metal line or plane 82, It is used as a line, bus or plane for distributing a ground reference voltage Vss, and the patterned metal layer 812 on the top layer is a metal line or plane 81, which is used as a line, bus or plane for distributing a voltage Vcc. Also in FIG. 3C, the number 821 is used to represent the patterned metal layer as a ground reference voltage, wherein the number 1 on the right side of the number 821 represents the first metal layer, the number 2 in the middle of the number 821 represents ground, and the number 821 The number 8 on the left indicates over-passivation metal. Similarly, in FIG. 3C, the number 812 is used to represent the patterned metal layer as a power supply, wherein the number 2 on the right side of the number 812 represents the second metal layer, the number 1 in the middle of the number 812 represents a power supply (power), and the number 812 The number 8 on the left indicates the metal above the protective layer. Continuing, a polymer layer 98 separates the two patterned metal layers 821 and 812, and a top polymer layer 99 covers the top patterned metal layer 812, wherein the polymer layer 98 can be polyimide, phenyl Cyclobutene, parylene, epoxy-based materials (such as epoxy resin or photoepoxy SU-8), elastomeric materials (such as silicone). In addition, a polymer layer 97 (not shown in FIG. 3C ) can be optionally formed between the protection layer 5 and the bottom end of the patterned metal layer 821, and the polymer layer 97 can be polyimide, phenyl ring Butene, parylene, epoxy-based materials (such as epoxy resin or photoepoxySU-8), elastomeric materials (such as silicone). The materials and processing of the polymer layers 97 , 98 , 99 in FIG. 3C are the same as those in FIG. 3B and FIG. 3D , and related descriptions will be described in the subsequent series of FIG. 15 . In addition, the patterned metal layer 821 used for distributing the ground reference voltage Vss in FIG. 3C is connected to the internal circuit under the protection layer through the protection layer openings 521, 522, 524, 529 and thin line metal structures 621, 622, 624, 629. The ground nodes Ts, Us, Vs, Ws of 21, 22, 23, 24 and the ground node Rs of the voltage regulator or transformer 41, and the patterned metal layer 812 for distributing the voltage Vcc is through the polymer layer opening (Fig. not shown in the figure), protective layer openings (not shown in the figure), and thin line metal structures (not shown in the figure) are connected to the power supply nodes Tp, Up, Vp, Wp of the internal circuits 21, 22, 23, 24 under the protective layer And the power node of the voltage regulator or transformer 41 (not shown in the figure). In addition, the current flowing through the metal lines or planes 81 and 82 is between 50 microampere and 2 milliampere or between 100 microampere and 1 milliampere.

In some applications, in addition to the metal lines or planes 81 being used in power supply design, the lines or planes in the metal lines or planes 81 can also be used to transmit data or signals (such as digital signals or analog signals). Similarly, in addition to the metal lines or planes 82 being used for grounding, the lines or planes within the metal lines or planes 82 can also be used to transmit data or signals (such as digital signals or analog signals).

There are more other types of structures above the protective layer, which are described as follows: (1) In the application of high performance (high performance) circuits or high precision (high precision) analog circuits, the patterned metal layer 812 and the patterned metal layer 821 A patterned metal layer (not shown) for transmitting signals (such as digital signals or analog signals) can be added between them, and a polymer layer (not shown) is formed under and above the patterned metal layer respectively. ), the patterned metal layer is separated from the patterned metal layer 812 and the patterned metal layer 821; (2) in the application of high current (high current) or high precision (high precision) circuit, the patterned metal layer 812 A patterned metal layer (not shown in the figure) for distributing a ground reference voltage can be added on top of the patterned metal layer and a polymer layer is formed between the patterned metal layer and the patterned metal layer 812, and a top polymerization An object layer covers the patterned metal layer. In other words, the patterned metal layer 812 is in the middle of the patterned metal layer 821 and the patterned metal layer, thus forming a Vss/Vcc/Vss structure above the protective layer 5; (3) if necessary, further Above the patterned metal layer added in (2) above, another patterned metal layer (not shown) for distributing a power supply is formed, and the patterned metal layer and patterned metal layer added in (2) above A polymer layer is formed between the metal layers 812, another polymer layer is formed between the patterned metal layer added in (2) above and another patterned metal layer, and a top polymer layer covers another pattern On the metallization layer, a power/ground reference voltage structure of Vss/Vcc/Vss/Vcc (stacked from bottom to top) is produced. For high current circuits, high precision analog circuits, high speed circuits, low power circuits, power management circuits and high performance circuits, the above structure can provide a stable power supply .

Please refer to FIG. 4 , which discloses an example of the voltage regulator or transformer 41 shown in FIGS. 1B-1D , 2B-2C and 3B-3D. This example circuit is a transformer with both voltage stabilizing and transforming functions, and is commonly used in the book "Semiconductor Memories: Ahand book of Design, Manufacture and Application" written by B.Prince and published by John Wiley & Sons in 1991 In the design of the modern dynamic random access memory (Dynamic Random Access Memory, DRAM). As shown in Figure 4, through the voltage stabilizing and transforming functions of the transformer, the voltage Vdd input by the external power supply can be converted into an output voltage Vcc, and the difference between the output voltage Vcc and a set target voltage Vcc0 is divided by The percentage of the target voltage Vcc0 is set to be less than 10%, preferably less than 5%. As mentioned in "Background Technology", more modern integrated circuit chips need to rely on the way of built-in transformers on the chip to convert the voltage supplied by the external (system, circuit board, module or circuit card) power supply into the voltage required by the chip. Voltage. In addition, some chips, such as a dynamic random access memory chip, even require twice or three times the voltage on the same chip, for example, the peripheral control circuit uses 3.3 volts (V), and the memory cells in the memory cell array area ( memory cell) use 1.5 volts.

In FIG. 4, the transformer includes two circuit blocks, which are a voltage reference generator 410 and a current mirror circuit 410'. The reference voltage generator 410 can generate a reference voltage VR at the node R to avoid being affected by voltage fluctuation of the external power supply voltage Vdd at the node 4199 . In addition, the external power supply voltage Vdd is also an input supply voltage of the reference voltage generator 410 . The reference voltage generator 410 includes two voltage divider (voltage divider) paths, one includes three P-type metal oxide semiconductor transistors 4101, 4103, 4105 connected together, and the other includes two connected together P-type metal oxide semiconductor transistors 4102, 4104. Continuing, the reference voltage VR can be regulated by connecting the drain of the PMOS transistor 4103 to the gate of the PMOS transistor 4104 . Therefore, when the external power supply voltage Vdd fluctuates and rises, the voltage of the node G rises, resulting in a low turn-on degree of the PMOS transistor 4104 , thereby causing the reference voltage VR to drop. Likewise, when the external power supply voltage Vdd drops, the reference voltage VR rises. So far, the above contents have explained the adjustment characteristics of the reference voltage generator 410 . The output of the reference voltage generator 410 is used as a reference voltage of the current mirror circuit 410'. For an integrated circuit chip, the current mirror circuit 410' can output a stable voltage and has a large current capability, and by avoiding a direct high current path from an external power supply voltage Vdd to the ground reference voltage Vss, the current mirror circuit 410' Huge power consumption or waste can also be eliminated. In addition, the drain of the PMOS transistor 4109 is connected to the gate of the PMOS transistor 4106, and the output voltage node P is connected to the reference voltage mirror (reference-voltage-mirror) PMOS transistor The gate of 4110, the current mirror circuit 410' can regulate the output voltage Vcc, so that the output voltage Vcc can be controlled in a specified voltage. In addition, the conductance transistor (conductance transistor) 4112 is a small P-type metal-oxide-semiconductor transistor, and its gate is connected to the ground reference voltage Vss, so the conductance transistor 4112 is always on; and the conductance transistor 4111 is a large P-type transistor. type metal oxide semiconductor transistor, and its gate is controlled by a signal Φ, when the internal circuit is in the active cycle (active cycle), the conductance transistor 4111 is in the open state, so that the P type metal oxide semiconductor transistor 4109 and the N type metal oxide semiconductor transistor 4109 The current path formed by the semi-transistor 4107 and the current path formed by the PMOS transistor 4110 and the NMOS transistor 4108 have a fast response. In addition, the turn-on of the conductance transistor 4111 can reduce the large instantaneous current (transient current) of the internal circuit (such as the internal circuit 21, 22, 23, 24 in Fig. 1B to Fig. 1C, Fig. 2B to Fig. 2C, Fig. 3B to Fig. 3D). ) The instantaneous instability of the output voltage Vcc caused by the demand is minimized. When the internal circuit is in an idle cycle, the transistor 4111 is turned off to avoid power consumption.

The second embodiment: connecting the over-passivation interconnection over the protection layer of the internal circuit (internal circuit).

As disclosed in previous patents of the patentee of the present invention, such as U.S. Patent No. 6,657,310 and U.S. Patent No. 6,495,442, the thick metal conductors (or metal lines or planes above the protective layer) of the present invention can be used to Distribute signal, voltage or ground reference voltage. In addition, the term "over-passivation" used in the present invention is the term "post-passivation" chosen by the patentee of the present invention in previous patents, such as U.S. Patent No. 6,495,442. )", and the metal lines or planes "above the protective layer" can be used, for example, as the interconnection of the internal circuit of the integrated circuit. In this embodiment, thick metal conductors (or metal lines or planes above the protective layer) can carry data or signals from an output node of a first internal circuit to an input of a second internal circuit node (input node). A bundle of metal lines designed to connect a group of similar nodes (such as data, bits, or signal addresses) between two internal circuits that are separated by a long distance (such as more than 1 mm), such as to connect a processor on the same chip 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, 256-bit, 512-bit or 1024-bit data (or address) metal lines between a unit and a memory unit, usually these metal lines are called buses (bus) , the bus is, for example, a character (word) bus or a bit (bit) bus used in a memory. In addition, since the present invention provides a thick metal conductor (or metal lines or planes above the protection layer) on the protection layer to connect multiple internal circuits, and the thick metal conductor can be far away from the semiconductor components, so when the signal passes through the thick metal conductor (or metal lines or planes above the protective layer), it can reduce the situation where the signal disturbs the semiconductor components below, or it can reduce the situation where the semiconductor components below interfere with the signal, so that the signal has better signal integrity (signal integrity) ). However, in this embodiment, the thick metal conductors above the protective layer (or metal lines or planes above the protective layer) are only connected to the nodes of the internal circuit, and do not pass through any off-chip input/output circuits. /output circuit), nor connected to an external circuit. In addition, the design of the thick metal conductor over the protection layer (or the metal line or plane above the protection layer) of the present invention is different from the existing pad redistribution design. In addition, because thick metal conductors (or metal lines or planes above the protective layer) have the advantage of low resistance and the resulting parasitic (parasitic) capacitance is very low, so the signal will not be severely attenuated, making the present invention very suitable Used in high speed, low power, high current or low voltage applications. In most cases, the present invention does not require additional amplifiers, drivers/receivers, or signal relays (repeaters) to help maintain signal integrity, but in some cases, an internal driver (internal driver), Internal receiver (internal receiver), signal relay or internal tri-state buffer (internal tri-state buffer), to transmit signals over long distances, and internal driver, internal receiver, internal tri-state buffer or signal relay all include The size of the MOS transistor is smaller than the MOS transistor of the chip connected to the external circuit. As for the size of the MOS transistor related to the internal circuit, internal driver, internal receiver, internal tri-state buffer and chip connected to the external circuit , will be described and compared in detail in the following content.

Please refer to FIG. 5B , FIG. 6B and FIG. 7B at the same time, which disclose the second embodiment of the present invention. FIG. 5B presents a simplified schematic circuit diagram, which uses metal lines or planes 83 on the protective layer 5 and thin line metal structures 631, 632a, 632b, 632c, 634 under the protective layer 5 to connect the internal circuit 20 (including 21, 22, 23, 24). In FIG. 5B, the internal circuit 21 has an input node Xi and an output node Xo, and sends a signal through the output node Xo, and this signal can be obtained by means of metal lines or planes 83 and thin line metal structures 631, 632a, 632b, 632c. , 634 are transmitted to the input nodes Ui, Vi, Wi of the internal circuit 22, 23, 24, and the internal circuit 21 may be a logic gate (logic gate), such as an inverse OR (NOR) gate, an inverse AND (NAND) gate, or (OR) gate, AND (AND) gate, or an internal buffer (such as an inverter, an internal driver, or an internal tri-state buffer as shown in FIG. 5C, FIG. 5D, and FIG. 5E). FIG. 6B presents a schematic top view of the circuit shown in FIG. 5B . FIG. 7B shows a schematic cross-sectional view of the circuit shown in FIG. 5B . In addition, in FIG. 5B and FIG. 6B , the lines or planes formed on the passivation layer 5 are represented by "thick lines", while the line structures formed under the passivation layer 5 are represented by "thin lines".

In the present invention, the internal driver used to drive the metal lines above the passivation layer is the same as the intra-chip driver described in US Published Patent No. 20040089951 (previous patent of the present patentee). Three internal logic circuits (internal The circuits 22 and 24 are NOR gates, and the internal circuit 23 is an AND gate) that can receive the data or signal transmitted by the internal circuit 21 . Because the metal line or plane 83 above the protection layer has low resistance and can generate low parasitic capacitance, the voltage swing (voltage swing) of the input nodes Ui, Vi, Wi between Vdd and Vss has very little attenuation and noise. Additionally, in this embodiment, the metal lines or planes do not need to be connected to any off-chip circuits that will be used in the subsequent series of Figures 11 to connect to an external circuit, such as electrostatic discharge (ESD) protection circuits, chip-on-chip circuits, etc. External drivers, off-chip receivers, or off-chip buffer circuits (such as on-chip tri-state buffer circuits), so this embodiment can improve speed and reduce power consumption.

Please refer to FIG. 5A, FIG. 6A and FIG. 7A at the same time, which is the related prior art of this embodiment. As shown in the figure, the internal circuit 21 located under the protective layer 5 is through the thin line metal structures 6311, 638, 6321a , 6321b is connected to an internal circuit 22 (such as a NOR gate), is connected to an internal circuit 23 (such as a NAND gate) through thin line metal structures 6311, 638, 6321a, 6321c, and is connected to an internal circuit 23 (such as a NAND gate) and through thin line metal structures 6311, 638 , 6341 are connected to other internal circuits 24 (such as a NOR gate). Therefore, conventionally, the data output from the internal circuit 21 is transmitted to other internal circuits 22 , 23 , 24 by relying on the fine line metal structures 638 , 6311 , 6321 , 6341 located under the protection layer 5 . However, existing designs result in signal attenuation, reduced performance, high power consumption, and high heat generation.

Next, please refer to FIG. 5B and FIG. 6B at the same time. It is to establish a metal line or plane 83 on the protective layer 5, and replace the thin lines in FIGS. 5A and 6A by the metal line or plane 83 on the protective layer 5. The metal structure 638 makes the internal circuits 21, 22, 23, and 24 connected together by means of metal lines or planes 83. As shown in the figure, a signal is sent from an output node of the internal circuit 21 (usually a metal oxide semiconductor of the internal circuit 21 Transistor drain) output, and then transmitted through the thin line metal structure 631 below the protective layer 5, the protective layer opening 531 of the protective layer 5 and the metal line or plane 83 on the protective layer 5, and then (1) through the protective layer 5 The protective layer opening 534 and the fine line metal structure 634 under the protective layer 5 are finally transmitted down to an input node of the internal circuit 24 (such as a NOR gate) (usually a gate electrode of a metal oxide semitransistor of the internal circuit 24 , such as the gate of a metal oxide semitransistor of the NOR gate); (2) pass through the protective layer opening 532 of the protective layer 5 and the thin line metal structure 632 (including 632a, 632b, 632c) under the protective layer 5, and finally transmit An input node to the internal circuit 22 (such as a NOR gate) and the internal circuit 23 (such as a NAND gate) (usually respectively the gate of a metal oxide semiconductor transistor of the internal circuit 22 and the internal circuit 23, such as respectively NOR gate and NAND gate of a metal oxide semi-transistor gate plate).

Therefore, in summary, an output node of the internal circuit 21 (usually the drain of a metal-oxide-semiconductor transistor of the internal circuit 21) is connected to the thin line metal structure 631 under the protective layer 5, and then passes through the protective layer 5. The protective layer opening 531 is connected to the metal circuit or the plane 83 on the protective layer 5, and finally connected to the thin line metal structures 632, 634 under the protective layer 5 through the protective layer openings 532, 534 of the protective layer 5, and then connected to the internal circuits 22, 23, 24 is connected to an input node (usually a gate of a metal-oxide-semiconductor transistor of the internal circuit 22, 23, 24). Wherein, the internal circuits 21, 22, 23, 24 include a NOR gate, an OR gate, an AND gate or a NAND gate, and the internal circuits 21, 22, 23, 24 are composed of at least one metal oxide semitransistor That is to say, the NOR gate, OR gate, AND gate or NAND gate is composed of at least one metal oxide semitransistor, and the metal oxide semitransistor is, for example, the size (the ratio of the channel width divided by the channel length) between An N-type metal oxide semiconductor transistor between 0.1 and 5 or between 0.2 and 2, or a size (ratio of channel width divided by channel length) between 0.2 and 10 or between 0.4 and 4 A P-type metal-oxide-semiconductor transistor, and the current flowing through the metal line or the plane 83 is, for example, in the range between 50 μA and 2 mA, or between 100 μA and 1 mA.

To continue, please refer to Figure 7B and Figure 7C at the same time, which are two implementations of the circuit structure shown in Figure 5B, as shown in the two figures, the metal line or plane 83 above the protective layer 5 can be a single-layer pattern Metallized layer (such as the single-layer patterned metal layer 831 shown in Figure 7B), or a multi-layer patterned metal layer, and has a polymer layer between each adjacent patterned metal layer, such as shown in Figure 7C Two patterned metal layers 831 (including 831a and 831b ) and 832 are shown, and a polymer layer 98 is provided between the two patterned metal layers 831 and 832 . In addition, the metal circuit or plane 83 above the protective layer 5 can cover a top polymer layer 99 (as shown in Figure 7B, a top polymer layer 99 covers the metal layer 831; as shown in Figure 7C, a top polymer layer layer 99 covers the patterned metal layer 832), and the top polymer layer 99 has no opening to expose the metal line or plane 83, so the metal line or plane 83 above the protection layer 5 (for example, the patterned metal layer 831 or patterned Metal layer 832) cannot be connected to external circuits. In other words, in this embodiment, the metal lines or planes 83 (such as the patterned metal layer 831 or the patterned metal layer 832 ) do not have contact pads for connecting external circuits.

In FIG. 7B, the numbers of the patterned metal layer 831 represent: "8" represents the metal above the protection layer, "3" represents a signal line, and "1" represents the first metal layer above the protection layer. . In the same way, in FIG. 7C, the numbers of the patterned metal layer 832 represent: "8" represents the metal above the protective layer, "3" represents a signal line, and "2" represents the metal above the protective layer. second metal layer. In addition, the patterned metal layer 831 on the protection layer 5 includes an adhesion/barrier/seed layer (adhesion/barrier/seed layer) 8311 and a thick metal layer 8312. In addition, a polymer layer 95 can be selectively formed on the protection layer. 5 and the bottommost layer of the patterned metal layer 831, as shown in FIG. 7D. Similarly, in FIG. 7C, the patterned metal layers 831a, 831b, 832 on the protective layer 5 include an adhesion/barrier/seed layer 8311a, 8311b, 8321 and a thick metal layer 8312a, 8312b, 8322, and can also be A polymer layer 95 is selectively formed between the passivation layer 5 and the bottommost layer of the patterned metal layer 831 (including 831a, 831b).

FIG. 7C is similar to FIG. 7B except that the structure above the passivation layer includes two patterned metal layers 831 and 832 . In FIG. 7C, the single patterned metal layer 831 in FIG. 7B is replaced by two patterned metal layers 831 (including 831a, 831b) and a patterned metal layer 832, and a polymer layer 98 is used to separate the patterned Metal layer 831 and patterned metal layer 832 . In addition, in terms of signal transmission, a signal is output from the output node of the internal circuit 21 (usually the drain of a metal oxide semiconductor transistor in the internal circuit 21), and then transmitted through the thin line metal structure 631 below the protective layer 5, the protective layer 5 A protective layer opening 531 in the protective layer and the patterned metal layer 831b above the protective layer 5, then (1) in the first path: go up through the opening polymer layer 9831 in the polymer layer 98, and pass through the patterned metal layer 832 , passing through a polymer layer opening 9834, passing through the patterned metal layer 831a, passing through a protection layer opening 534 of the protection layer 5, passing through the fine line metal structure 634 below the protection layer 5, and finally passing down to the internal circuit 24 ( For example, an input node of the NOR gate (usually the gate of a metal oxide semitransistor of the internal circuit 24, such as the gate of a metal oxide semitransistor of the NOR gate); (2) in the second path: Pass through a protective layer opening 532 of the protective layer 5 and pass through the thin line metal structure 632 under the protective layer 5, and finally transmit to an input node of the internal circuit 22 (such as a NOR gate) and the internal circuit 23 (such as a NAND gate). (Usually the gates of a metal-oxide-semiconductor transistor of the internal circuit 22 and the internal circuit 23 are respectively, for example, the gates of a metal-oxide-semiconductor transistor of a NOR gate and a NAND gate, respectively).

In addition, the metal circuit or plane above the protective layer, the polymer layer and the internal circuit of the second embodiment of the present invention will be described in the subsequent series of Figures 15, 16, 17, 18 and 19. described in detail.

In addition, in FIG. 5B, FIG. 6B, FIG. 7B, FIG. 7C and FIG. 7D, metal lines or planes 83 (including 831 and/or 832) are not connected to an external circuit on the chip for connecting an external circuit, so No significant voltage drop or signal attenuation occurs on the metal lines or planes 83 .

In addition, the size of a metal-oxide-semiconductor transistor of the present invention can be defined as the ratio of the channel width (channel width) divided by the channel length (channel length), or precisely the ratio of the effective channel width divided by the effective channel length. Definitions apply in all embodiments of the invention.

Please refer to FIG. 5C to FIG. 5E at the same time, which disclose an example of the internal circuit 21 as an internal buffer (internal buffer), wherein the internal buffer is composed of at least one metal oxide semitransistor (MOStransistor), The metal oxide semiconductor transistor includes, for example, a P-type metal oxide semiconductor transistor (PMOS transistor) with a channel width/channel length ratio between 3 and 60 or between 5 and 20, or a channel width/channel length ratio between An N-type metal oxide semi-transistor (NMOS transistor) between 1.5 and 30 or between 2.5 and 10, and the current flowing through the metal line or plane 83 is between 500 microamperes and 10 milliamperes or Between 700 microamps and 2 milliamps. FIG. 5C discloses an inverter 211 used as the internal circuit 21 of FIG. 5B , FIG. 6B , FIG. 7B , FIG. 7C and FIG. 7D . In the first application, the size of the N-type MOS transistor 2101 and the P-type MOS transistor 2102 can be the same as the size of the MOS transistor used in the internal circuit, so in the inverter 211, the N-type The size of the oxygen-semiconductor transistor 2101 is between 0.1 and 5, preferably between 0.2 and 2, and the size of the P-type metal oxide semiconductor transistor 2102 is between 0.2 and 10, and The preferred one is between 0.4 and 4. In addition, the current output by the inverter 211 and passing through the metal line or plane 83 above the protective layer 5 is in the range between 50 microamperes (μA) and 2 milliamperes, and the current is between 100 microamperes (μA) and 1 milliampere. The range between is preferable. In the second application, the inverter 211 needs to output a larger drive current (drive current), for example, when the internal circuits 22, 23, 24 need a high load (heavy load), or when the internal circuits 22, 23 When the distance between , 24 and the internal circuit 21 is greater than 1 millimeter or 3 millimeters and a long-distance connecting metal line is required, the inverter 211 needs to output a relatively large driving current. In addition, the current output from the inverter 211 is higher than the general internal circuit, and the current, such as 1 mA or 5 mA, is in the range between 500 microamperes (μA) and 10 mA, A range between 700 microamperes and 2 milliamperes is preferred. Therefore, in the second application, the size of the NMOS transistor 2101 of the inverter 211 is in the range of 1.5 to 30, and preferably in the range of 2.5 to 10, The size of the PMOS transistor 2102 is in the range of 3 to 60, and preferably in the range of 5 to 20. More details about the size of the MOS transistors in (general) internal circuits or the internal circuits used to drive other high-load internal circuits will be described in detail in the subsequent series of FIG. 15 .

In addition, in FIG. 5C, the drain of the N-type metal oxide semiconductor transistor 2101 is connected to the metal line or plane 83 above the protective layer 5 (as shown in FIGS. 5B, 6B, 7B, 7C and 7D), The drain of the PMOS transistor 2102 is connected to the metal circuit or the plane 83 above the protective layer 5 (as shown in FIGS. 5B , 6B, 7B, 7C and 7D ).

In most applications, since the metal lines or planes above the protective layer have lower resistance, multiple internal circuits formed by smaller metal-oxide-semiconductor transistors can be connected to each other through the metal lines or planes on the protective layer, where The internal circuits include an N-type metal oxide semiconductor transistor with a size (the ratio of channel width divided by channel length) between 0.1 and 5 or between 0.2 and 2, or a size (channel width divided by channel length) length ratio) between 0.2 and 10 or between 0.4 and 4 for a P-type metal oxide semiconductor transistor. In addition, in some applications, when the internal circuits 22, 23, 24 require high loads, or when the distance between the internal circuits 22, 23, 24 and the internal circuit 21 is greater than 1 mm or 3 mm, a long-distance connection is required When metal lines are used, a larger driving current is required. Therefore, in the case of high load, an internal drive or an internal buffer is required.

5D and FIG. 5E disclose that the internal driver 212 or the internal tri-state buffer 213 is used as the internal circuit 21, and the internal driver 212 or the internal tri-state buffer 213 is used to drive the circuit shown in FIG. 5B, FIG. 6B, FIG. 7B, FIG. 7C and An example of metal lines or planes 83 and other internal circuits 22 , 23 , 24 on protective layer 5 is shown in FIG. 7D . The circuit shown in Fig. 5 D and Fig. 5 E except (1) internal driver 212 or internal tri-state buffer 213 are not connected with an external circuit; Except for the size of the MOS transistor which is smaller than the on-chip driver or the on-chip tri-state buffer, the rest are similar to the off-chip circuits described in FIG. 11A and FIG. 11C respectively. The internal driver 212 in FIG. 5D is an example of the intra-chip driver described in US Patent Publication No. 20040089951 by the patentee of the present invention. The internal tri-state buffer 213 provides the ability to amplify the signal (drive capability) and the ability to switch on or off (switch capability), and the internal tri-state buffer 213 is particularly helpful for metal lines above the protection layer as a data or address bus. Or planarly transmit a data signal or an address signal in a memory chip.

In FIG. 5D, the size of the N-type metal-oxide-semiconductor transistor 2103 is between 1.5 and 30, and preferably between 2.5 and 10, while the size of the P-type metal-oxide-semiconductor transistor 2104 is between Between 3 and 60, and preferably between 5 and 20, in addition, the current passing through the metal line or plane 83 on the protective layer 5 and the output node Xo of the internal driver 212 (usually a metal semiconductor component) The current output by the drain) is in the range of 500 microamperes to 10 milliamperes, and preferably in the range of 700 microamperes to 2 milliamperes. In addition, in FIG. 5D , the internal driver 212 can drive a signal output from the output node Xo, and transmit it to the input nodes Ui, Vi of the internal circuits 22, 23, 24 after passing through the metal line or the plane 83 above the protective layer 5 , Wi, but not transmitted to an external circuit.

In FIG. 5E, the size of the N-type metal-oxide-semiconductor transistor 2107 is between 1.5 and 30, and preferably between 2.5 and 10, while the size of the P-type metal-oxide-semiconductor transistor 2108 is between Between 3 and 60, and preferably between 5 and 20, in addition, the current output through the metal line or plane 83 above the protective layer 5 and the output node Xo of the internal tri-state buffer 213 is between The range between 500uA and 10mA, and preferably the range between 700uA and 2mA. In addition, in FIG. 5E, the internal tri-state buffer 213 can drive a signal output from the output node Xo, and transmit it to the input of the internal circuit 22, 23, 24 after passing through the metal line or the plane 83 above the protection layer 5 Nodes Ui, Vi, Wi, but not transmitted to an external circuit.

When the internal circuit 22, 23, 24 needs a high load, or when the distance between the internal circuit 22, 23, 24 and the internal circuit 21 is greater than 1 mm or 3 mm and a long-distance connecting metal line is required, the internal driver 212 and The output node Xo of the internal tri-state buffer 213 needs to output a large driving current.

One of the important applications of metal lines or planes above the protective layer is to connect memory cells and internal circuits (such as logic circuits) on a memory chip that are separated by a certain distance. Please refer to Fig. 5F, which discloses how a memory cell utilizes metal lines or planes 83 on the protective layer 5 and thin line metal structures under the protective layer 5 to be connected to internal circuits 22, 23, 24 as logic circuits ( 5B, 6B, 7B, 7C and 7D). Wherein, the logic circuit includes, for example, a NOR gate, an OR gate, an AND gate or a NAND gate, and the internal circuits 22, 23, and 24 may be made of at least one metal-oxide-semiconductor transistor, and the above-mentioned thin circuit The metal structure is a metal oxide semitransistor connected to the internal circuit 22, 23, 24, for example connected to the source (source), drain (drain) or gate (gate) of a metal oxide semitransistor, and the metal oxide semitransistor The half-transistor can be an N-type metal-oxide-semiconductor transistor with a channel width/channel length ratio between 0.1 and 5 or between 0.2 and 2, or a channel width/channel length ratio between 0.2 and 10 or between A P-type metal-oxide-semiconductor transistor between 0.4 and 4, and the current flowing through the metal line or the plane 83 is, for example, between 50 microamperes and 2 milliamperes or between 100 microamperes and 1 milliamperes.

In this application, the metal line or plane 83 on the protection layer 5 is used as a data bus, such as a bit line bus or an inverted bit line bus. In the design of connecting a memory array (memory array) and a logic circuit, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 or 4096 metal strips arranged in parallel can be formed on the protective layer 5 The wires or planes 83 serve as a data bus of a memory chip, and use these metal wires or planes 83 to transmit data signals between memory units and logic circuits. The metal line or plane 83 above the protective layer 5 is particularly suitable for transmission of wide-bit data, such as transmission of 64, 128, 256, 512, 1024 bit width data. In addition, when transmitting the signal between the memory unit and the logic circuit (logic circuit), the metal line or plane 83 above the protection layer 5 can also be used as an address bus (address bus) in addition to the data bus mentioned above. Used to transmit address signals. In addition, the signals transmitted by the metal lines or planes 83 on the protection layer 5 also include clock signals. Fig. 5 F is an example with a static random access memory unit 215 as memory unit, but this memory unit also can be other memory units in this embodiment, such as dynamic random access memory (DRAM) unit, can eliminate Program read-only memory (EPROM) unit, electronically erasable read-only memory (EEPROM) unit, flash memory (Flash) unit, read-only memory (ROM) unit and magnetic random access memory (magnetic RAM, MRAM) unit. The SRAM unit 215 includes six MOS transistors, which are two drive N-type MOS transistors 2115, 2117, two load P-type MOS transistors 2116, 2118, and two word codes - Line-control (word-line-control) N-type metal oxide semiconductor transistors 2119, 2120. In addition, in a memory chip, a memory array can be formed by repeating the SRAM cells 215 . When the static random access memory unit 215 is in the read state, the static random access memory unit 215 outputs complementary data, such as bit (bit) data and reverse bit (bit) data, and pass through the N-type metal oxide semiconductor transistor 2119 respectively The complementary data is transmitted to the bit line and the reverse bit line with the N-type metal oxide semiconductor transistor 2120, and then the bit data and the reverse bit data are transmitted through column selection (CS) The transistors 2122 and 2123 are then input to a sense amplifier (sense amplifier) 214 . Next, the bit line of the memory cell is connected to the gate of the NMOS transistor 2113 in the sense amplifier 214 to control the on or off of the NMOS transistor 2113 of the sense amplifier 214, when the sense amplifier 214 When the N-type metal-oxide-semiconductor transistor 2113 is turned on, the sense amplifier 214 can initially amplify the inverted bit (bit) data so that it has a better waveform or better voltage level, and output the initially amplified inverted bit. bit data to the internal tri-state buffer 213 . In FIG. 5F , it is an example of using a differential amplifier (differential amplifier) as the sense amplifier 214. This differential amplifier contains four transistors, including two N-type metal-oxide-semiconductor transistors 2111, 2113 and two P-type metal-oxide-semiconductor transistors 2112, 2114, wherein the differential amplifier uses an N-type metal-oxide-semiconductor transistor 2121 to isolate the differential amplifier from the ground reference voltage Vss, and controls the differential amplifier by means of a line selection signal to avoid power consumption . When the SRAM unit 215 is not in the read state, that is, when both the word line and the bit line connected to the SRAM unit 215 are not selected, the NMOS transistor 2121 is turned off. The inverted bit (bit) data output from the gate of the NMOS transistor 2113 of the sense amplifier 214 is an input to an internal driver, internal buffer or internal tri-state buffer 213 (as shown in FIG. 5F ). Node Xi. In addition, the control signals En, En are output from a read enable circuit (not shown in the figure), and the internal tri-state buffer 213 is controlled to be turned on or off by using the control signals En, En. In Fig. 5F, the output node Xo of the internal tri-state buffer 213 outputs more amplified bit data to the internal circuits 22, 23, 24 through the metal line or plane 83 on the protective layer 5 (as shown in Fig. 5B, Fig. 6B, Fig. 7B, Figure 7C and Figure 7D). Therefore, in summary of the above, a SRAM cell 215 is formed by passing through the sense amplifier 214, the internal tri-state buffer 213, the fine line metal structure 631 under the protection layer 5, the protection layer opening 531 in the protection layer 5, The metal lines or planes 83 on the protective layer 5, the protective layer openings 532, 534 in the protective layer 5, and the thin line metal structures 632, 634 are connected to the internal circuits 22, 23, 24 on the same chip, as shown in Fig. 5B and Fig. 6B , Figure 7B, Figure 7C and Figure 7D. Wherein, the internal circuit 21 is an internal tri-state buffer 213 here, but the internal circuit 21 can also be an internal driver 212 (as shown in FIG. 5D ) or other internal circuits, such as NOR gates, NOR gates, NAND gate, AND gate, OR gate, adder, multiplexer, diplexer, multiplier, complementary metal oxide semiconductor, bipolar complementary metal oxide semiconductor or bipolar circuit (bipolar circuit), and when the internal circuit 21 is an internal driver 212, the internal circuit 21 is at least composed of a metal oxide semitransistor, and this The metal oxide semiconductor transistor includes a P-type metal oxide semiconductor transistor with a channel width/channel length ratio between 3 and 60 or between 5 and 20, or a channel width/channel length ratio between 1.5 and 30 or between An N-type metal-oxide-semiconductor transistor between 2.5 and 10, and the current flowing through the metal line or plane 83 at this time is between 500 microamperes and 10 milliamperes or between 700 microamperes and 2 milliamperes; In addition, when the internal circuit 21 is the above-mentioned other internal circuit, the internal circuit 21 at least includes an N-type metal oxide semiconductor transistor whose channel width/channel length ratio is between 0.1 and 5 or between 0.2 and 2, Or a P-type metal-oxide-semiconductor transistor with a channel width/channel length ratio between 0.2 and 10 or between 0.4 and 4, and the current flowing through the metal line or plane 83 is between 50 microamperes and between 2mA or between 100uA and 1mA.

Please refer to FIG. 5G , before the inverse bit (bit) data output by the sense amplifier 214 reaches the output node Xo of the internal circuit 21, it will first pass through a pass circuit 216, where the internal circuit 21 That is, through the circuit 216 . The pass circuit 216 can be a simple MOS transistor, such as NMOS transistor 2124, and is controlled by a read signal. In this design, a SRAM cell 215 is passed through the sense amplifier 214, through the circuit 216, the fine line metal structure 631 under the passivation layer 5, the passivation layer opening 531 in the passivation layer 5, the The metal lines or planes 83, the protective layer openings 532, 534 in the protective layer 5 and the fine line metal structures 632, 634 under the protective layer 5 are connected to the internal circuits 22, 23, 24, as shown in Fig. 5B, Fig. 6B, Fig. 7B, Figure 7C and Figure 7D.

Please refer to FIG. 5H , before the inverted bit (bit) data output by the sense amplifier 214 reaches the output node Xo of the internal circuit 21, it will first pass through a latch circuit (latch circuit) 217. In the internal circuit 21 is the latch circuit 217. The latch circuit 217 can be a static random access memory unit, which is used to temporarily store the data output by the sense amplifier 214 before the data output by the sense amplifier 214 is sent to logic circuits (such as internal circuits 22, 23, 24). (ie the data is latched). In addition, the NMOS transistors 2129 and 2130 can be controlled by a read signal. In this design, a SRAM cell 215 is passed through the sense amplifier 214, the latch circuit 217, the fine-line metal structure 631 under the passivation layer 5, the passivation layer opening 531 in the passivation layer 5, the passivation layer 5 The metal lines or planes 83, the protective layer openings 532, 534 in the protective layer 5, and the thin line metal structures 632, 634 are connected to the internal circuits 22, 23, 24, as shown in Fig. 5B, Fig. 6B, Fig. 7B, Fig. 7C and Fig. 7D.

However, the pass circuit 216 in FIG. 5G or the latch circuit 217 in FIG. 5H does not provide a large driving capability. In order to drive the internal circuits 22, 23, 24 that require high loads, or transmit the reverse bit (bit) data output by the circuit 216 or the bit (bit) data output by the latch circuit 217 to the internal circuits 22, 23, 24. An internal driver 212 mentioned above can be added to the output node of the pass circuit (as shown in FIG. 5I) or the output node of the latch circuit (as shown in FIG. 5J), so as to use this internal driver 212 to amplify the pass The inverted bit data output by the circuit 216 or the bit data output by the latch circuit 217 .

Please refer to FIG. 5K , except that the internal circuit 21 receives a signal from the internal circuit 24 (here, a NOR gate) instead of driving the internal circuit 24 , the rest of the circuit design is similar to FIG. 5B . This internal circuit 24 (here a NOR gate) is through the fine line metal structure 634' under the protective layer 5, the protective layer opening 534' in the protective layer 5, the metal line or plane 83 on the protective layer 5, the protection The protective layer opening 531' in the layer 5 and the fine line metal structure 631' under the protective layer 5 transmit a signal or data sent from the output node Wo to the input node Xi' of the internal circuit 21 (usually the internal circuit 21 The gate of a metal-oxide-semiconductor transistor), and the internal circuit 24 (here, a NOR gate) also passes through the thin line metal structure 634' under the protective layer 5, the protective layer opening 534' in the protective layer 5, the protective layer 5, the protective layer opening 532' in the protective layer 5, and the thin line metal structures 632a', 632b' under the protective layer 5 transmit the signal or data sent by the output node Wo to the internal circuit 22 (here a NOR gate) input node Ui. Moreover, at the same time, the internal circuit 24 (here, a NOR gate) also passes through the thin line metal structure 634' under the protective layer 5, the protective layer opening 534' in the protective layer 5, and the metal lines or planes on the protective layer 5. 83. The protective layer opening 532' in the protective layer 5 and the thin line metal structures 632a', 632c' under the protective layer 5 transmit the signal or data sent by the output node Wo to the internal circuit 23 (here, a NAND Gate) input node Vi. Wherein, the thin line metal structures 634', 631' can be formed by metal lines and planes, and in this example, the thin line metal structures 634', 631' are formed by conductive plugs and metal pads in the dielectric layer and thin line The metal layers are formed, for example, in approximately aligned stacks. In some integrated circuit technologies, the conductive plug is a tungsten plug or damascene copper. Internal circuits 21, 22, 23 receive signals at input nodes Xi', Ui, Vi, and output signals at output nodes Xo', Uo, Vo to other internal circuits. In addition, the internal circuit 21 may be an internal receiver 212' (as shown in FIG. 5L), an internal tri-state buffer 213' (as shown in FIG. 5M ) or other internal circuits, such as a NOR gate ( NORgate), NAND gate, AND gate, OR gate, operational amplifier, adder, multiplexer, diplexer ), multiplier, analog/digital converter (A/D converter), digital/analog converter (D/AConverter), complementary metal oxide semiconductor, bicarrier complementary metal oxide semiconductor or dual carrier Sub-circuit (bipolar circuit), and when the internal circuit 21 is an internal receiver 212', the internal circuit 21 is composed of at least one metal oxide semitransistor, and the metal oxide semitransistor includes a channel width/channel length ratio between 3 and 60 between 5 and 20 or between 5 and 20 or an N-type MOS transistor having a channel width/channel length ratio between 1.5 and 30 or between 2.5 and 10, and this The current flowing through the metal line or the plane 83 is between 500 microamperes and 10 milliamperes or between 700 microamperes and 2 milliamperes; in addition, when the internal circuit 21 is the other internal circuits mentioned above, the internal first Road 21 at least includes an N-type metal oxide semiconductor transistor with a channel width/channel length ratio between 0.1 and 5 or between 0.2 and 2 or a channel width/channel length ratio between 0.2 and 10 or between 0.4 A P-type metal-oxide-semiconductor transistor between 4 and 4, and the current flowing through the metal line or the plane 83 is between 50 microampere and 2 milliampere or between 100 microampere and 1 milliampere. In addition, the internal circuit 21 also includes a static random access memory unit (SRAM cell), a dynamic random access memory unit (DRAM cell), a non-volatile memory unit (non-volatile memory cell), a flash memory unit (flash memory cell), programmable read-only memory cell (EPROM cell), read-only memory cell (ROM cell), magnetic random access memory (magnetic RAM, MRAM) cell, or sense amplifier (sense amplifier). In addition, the input node of the internal circuit 21 is usually the gate of a metal-oxide-semiconductor transistor. Please refer to FIG. 5L, the internal receiver 212' can receive a signal through the metal line or plane 83 on the protective layer 5, and output a signal from the output node Xo' to other internal circuits, but does not output the signal to an external circuit. Please refer to FIG. 5M, the internal tri-state buffer 213' can receive a signal through the metal line or plane 83 on the protective layer 5, and output a signal from the output node Xo' to other internal circuits, but does not transmit the signal output to an external circuit.

In FIG. 5L, the size of the N-type metal-oxide-semiconductor transistor 2103' is between 1.5 and 30, and preferably between 2.5 and 10, while the size of the P-type metal-oxide-semiconductor transistor 2104' is is between 3 and 60, and preferably between 5 and 20, and the current passing through the metal line or plane 83 above the protective layer 5 and the input node Xi of the internal receiver 212' is between The range between 500 microamperes and 10 milliamperes, and preferably the range between 700 microamperes and 2 milliamperes. In addition, the input node Xi' of the internal receiver 212' can receive a signal output by the output node Wo of the internal circuit 24 through the metal line or plane 83 on the protective layer 5, but does not receive a signal output by an external circuit, as shown in FIG. 5B, 6B, 7B, 7C and 7D.

In FIG. 5N to FIG. 5R , it discloses the design of writing the data output by the internal circuit 24 (logic gate) into a memory unit of a memory array. Please refer to FIG. 5K and FIG. 5N at the same time, the internal circuit 21 may be an internal tri-state buffer 213'. The internal tri-state buffer 213' has the function of amplifying data and switching, and the control signals En and En are output from a reading circuit (not shown in the figure), and the control signals En and En are used to control the internal tri-state buffer 213 on or off. In addition, through the metal line or plane 83 on the protection layer 5, one bit (bit) data can be transmitted to the input node Xi' of the internal tri-state buffer 213', and when an amplified inverted bit (bit) data is When a power supply voltage is reached, the amplified reverse bit (bit) data is output to the reverse bit (bit) line by the P-type metal oxide semiconductor transistor 2110', and when an amplified reverse bit (bit) data is a ground reference voltage, the amplified reverse bit (bit) data is output to the reverse bit (bit) line by the NMOS transistor 2109'. The amplified inverted bit data output from the output node Xo' can be transmitted to the SRAM unit 215 through the row select transistor 2122 controlled by the row select (CS) signal and through the NMOS transistor 2119. Please refer to FIG. 5K and FIG. 5N at the same time. The internal circuit 24 (here, a NOR gate) is passed through a metal structure 634' of thin lines, a protective layer opening 534', and a metal line or plane 83 above the protective layer 5. , a protective layer opening 531 ′, a fine line metal structure 631 ′, and an internal tri-state buffer 213 ′ to transfer data to a SRAM cell 215 in a memory array.

Please refer to FIG. 5O, the bit data output by the internal circuit 24 (here, a NOR gate) passes through a pass circuit 216', is connected to the bit line of the SRAM cell array, and then passes through the row selection transistor And writing to the static random access memory unit 215 . Wherein, the internal circuit 21 in FIG. 5K is a passing circuit 216', and the passing circuit 216' can be a simple metal oxide semiconductor transistor, such as an N-type metal oxide semiconductor transistor 2124', and is controlled by a writing signal ( write enable signal) controlled. In this design (please refer to FIG. 5K and FIG. 5O at the same time), a data output from the output node Wo of the internal circuit 24 (here, a NOR gate) is written into a static random access memory unit through the following path In 215: starting from a thin line metal structure 634', passing through a protective layer opening 534' upwards, passing through a metal line or plane 83 on the protective layer 5, passing down a protective layer opening 531', a thin line metal The structure 631', through the circuit 216', is then connected to the bit line of the SRAM cell array, and then written into the SRAM cell 215 through the row select transistor.

Please refer to FIG. 5P, which is similar to FIG. 5H, the input bit line data can be temporarily stored or latched in a latch circuit 217' before being written into the SRAM unit 215. In addition, the N-type metal-oxide-semiconductor transistors 2129' and 2130' are used for writing control. In this design (please refer to FIG. 5K and FIG. 5P at the same time), a data output from the output node Wo of the internal circuit 24 (here, a NOR gate) is written into a static random access memory unit through the following path In 215: starting from a thin line metal structure 634', passing through a protective layer opening 534' upwards, passing through a metal line or plane 83 on the protective layer 5, passing down a protective layer opening 531', a thin line metal The structure 631', a latch circuit 217', is then connected to the bit line of the SRAM cell array, and then written to the SRAM cell 215 through the row select transistor.

However, the pass circuit 216' of FIG. 50 or the latch circuit 217' of FIG. 5P may not provide sufficient sensitivity to detect weak signals at the input nodes. In order to restore (restore) weak data signal (weak datasignal), can increase an internal receiver 212' at the input terminal of pass circuit 216' (as shown in Figure 5Q) or at the input terminal of latch circuit 217' (as shown in Figure 5R shown).

Another important application of the connection line above the protection layer is in the transmission of accurate analog signals (analogsignal). The low resistance and capacitance per unit length characteristics of the metal lines or planes above the protective layer provide a digitally simulated analog signal with low signal distortion. Please refer to FIG. 5S , which discloses an analog design using metal lines or planes 83 on the protective layer 5 to connect analog circuits. Except that the internal circuits 21, 22, 23, 24 are analog circuits or mixed-mode circuits, the signals transmitted by metal lines or plane 83 are digital simulation analog signals and the internal circuits 21, 22, 23, 24 output/receive The signal of FIG. 5S is similar to that of FIG. 5B except that the signal is a digital simulation of an analog signal. In FIG. 5S , an output node Yo of the internal circuit 21 is connected to the thin line metal structure 631 , then passes through the protective layer opening 531 of the protective layer 5 to connect to the metal line or plane 83 on the protective layer 5 , and then passes through the protective layer opening 532 , 534 is connected to the thin line metal structure 632 (including 632a, 632b, 632c), 634, and finally the thin line metal structure 632 (including 632a, 632b, 632c), 634 is connected to an input node of the internal circuit 22, 23, 24 Ui', Vi', Wi', wherein the internal circuits 21, 22, 23, 24 as analog circuits include a P-type metal oxide semiconductor transistor, an N-type metal oxide semiconductor transistor, a NOR gate (NOR gate), One NAND gate, one AND gate, one OR gate, one sense amplifier, one operational amplifier, one analog/digital conversion A/D converter, a digital/analog converter (D/A Converter), a pulse reshaping circuit, a switched-capacitor filter, a resistor-capacitor filter (RC filter) or other types of analog circuits, etc. For other relevant parts, please refer to FIG. 5B for description, and will not be described in detail here.

Please refer to FIG. 5T, which discloses an example in which the internal circuit 21 in FIG. 5S is an operational amplifier 218, and its output node Yo is connected to the metal line or plane 83 on the protective layer 5. This operational amplifier is an operational amplifier. It is designed based on a complementary metal oxide semiconductor (CMOS) technology, please refer to "CMOS Digital Circuit Technology" written by M.Shoji in 1987 and issued by Prentice-Hall Company. The differential analog signal is input to the input nodes Yi+ and Yi- of a differential circuit (differential circuit) 219 formed by two N-type MOS transistors 2125, 2127 and two P-type MOS transistors 2126, 2128. , wherein the input nodes Yi+ and Yi− are respectively connected to the gates of the PMOS transistor 2126 and the PMOS transistor 2128 . The output of the drain of the N-MOS transistor 2127 and the drain of the P-MOS transistor 2128 of the differential circuit 219 is connected to the gate of the N-MOS transistor 2135 and the first capacitor (capacitor) 2133. on the electrode. An output node Yo is connected to the second electrode of the capacitor 2133 , the drain of the NMOS transistor 2135 and the drain of the PMOS transistor 2136 . Therefore, the signal at the output node Yo can be controlled by the turn-on degree of the NMOS transistor 2135 , wherein the NMOS transistor 2135 is also controlled by the output of the differential circuit 219 . The power supply node P of the differential circuit 219 is connected to the drain of the P-type metal oxide semiconductor transistor 2132, wherein the source of the P-type metal oxide semiconductor transistor 2126 and the source of the P-type metal oxide semiconductor transistor 2128 are used in the differential circuit 219 pole is connected to the power node P. In addition, the voltage level of the gate of the PMOS transistor 2132 is controlled by the resistor 2134 . In addition, the signal output by the differential circuit 219 can be amplified by the capacitor 2133 . The capacitor 2133 is often used in the design of an analog circuit, and is usually formed by a MOS capacitor or a poly-to-poly capacitor, wherein the MOS capacitor A polysilicon gate (poly gate) and a silicon substrate (silicon substrate) are used as the two electrodes of the capacitor 2133, and a polysilicon-to-polysilicon capacitor uses a first polysilicon (polysilicon) and a second polysilicon as a capacitor Two electrodes of 2133. Resistors are also often used in an analog circuit, and are usually impurity-doped diffusion areas in the silicon substrate, such as n-well, p-well, N+ diffusion, P+ diffusion, and/or Impurity doped polysilicon (impurity-doped polysilicon) to form.

The third embodiment: the complete structure of the present invention.

The technique of forming thick metal conductors (or metal lines or planes above the passivation layer) above the passivation layer can provide additional benefits to the chip. The material of the thick metal conductor above the protective layer (or the metal circuit or plane above the protective layer) includes gold, copper, silver, palladium, rhodium, platinum, ruthenium or nickel, which can be formed not only as a conductor body, but also as a other contact structures. Utilize various types of contact structures such as solder bumps, solder pads, solder balls, Au bumps, gold pads, palladium pads (Pd pad), aluminum pad (Al pad) or wire bonding pad (wire bonding pad), the chip can easily use different methods to bond with the external circuit. In FIG. 5B, FIG. 5K, FIG. 5S, FIG. 7B, FIG. 7C and FIG. 7D, the metal lines or planes above the protective layer are used to transmit the output or input signals of the internal circuit, and the internal circuit is not connected to the external circuit. . However, a chip must be connected to and communicate with external circuits. Next, please refer to FIG. 8B to FIG. 8F , FIG. 9B to FIG. 9D and FIG. 10B to FIG. 10I , which disclose a complete structure of the present invention, and use it as the third embodiment of the present invention. 8B to 8F, FIG. 9B to FIG. 9D and FIG. 10B to FIG. 10I describe how the signal generated by the internal circuit is transmitted to the external circuit through the metal line or plane above the protective layer and the thin line metal structure below the protective layer, or It is how the signal generated by the external circuit is transmitted to the internal circuit through the metal line or plane above the protective layer and the thin line metal structure below the protective layer. 8B to 8F, FIG. 9B to FIG. 9D and FIG. 10B to FIG. 10I are respectively the circuit structure, top view and cross-sectional diagram of this embodiment, which disclose the use of the present invention by connecting the internal circuit to the overall chip design of the external circuit. Complete structure of fine line metal structure and metal over capping layer. In addition, the internal circuit 20 (including 21, 22, 23, 24) described in relation to Fig. 5B to Fig. 5T, Fig. 6B and Fig. 7B to Fig. 7D is also applicable to the internal circuit 20 (comprising 21, 22, 24) in this embodiment 23, 24).

In this embodiment, the signal of the internal structure 200 is transmitted to the external circuit (not shown in the figure) through an off-chip structure 400, as shown in FIG. 8B, or the external circuit (not shown in the figure) The signal is transmitted to the internal structure 200 through the off-chip structure 400, as shown in FIG. 8C. The metal lines or planes 83r above the protective layer 5 can be used as reconfiguration lines for the (input/output) pads of the thin line metal structure (such as the metal pad 6390 in FIG. 10B ), in other words, the thin line metal structure The (input/output) pads are relocated to a different location pad (such as the contact pad 8310 in FIG. 10B ) using a reconfiguration line, and then connected to an external circuit using a wire or bump on this pad, Therefore, viewed from the top perspective view, the position of this pad is different from the position of the (input/output) pad of the fine line metal structure. For example, in FIG. 10B, the position of the contact pad 8310 is viewed from the top perspective view. Unlike the location of the metal pad 6390, in addition, the thickness of the reconfiguration lines used to form the contact pad 8310 is greater than 1.5 microns. In addition, the metal line or plane 83r on the passivation layer 5 and the metal line or plane 83 on the passivation layer 5 can be formed simultaneously. The current flowing through the metal line or the plane 83 at this time is between 50 microamperes and 10 milliamperes.

The contact pads 8310 exposed by a polymer opening 9939 in the top polymer layer 99 can be connected to external circuitry using wire bonding or other bonding methods as described later in the series of FIGS. 15 . In addition, for flip-chip assembly (flip-chip assembly), tape automated bonding (Tape Automated Bonding, TAB) or other bonding methods as described in the subsequent series of Figure 15, the contact pad 8310 and the polymer A contact structure 89 is formed in the layer opening 9939, and the method for forming the contact structure 89 and its detailed description will also be described in the subsequent series of FIG. 15 . The contact pads 8310 can be connected to the external circuit 40 on the chip. Therefore, based on the above description, the chip-connection structure 400 includes a chip-connection circuit 40, a metal pad 6390, a contact structure 89 (optional), and a reconfiguration circuit 83r (optional) above the protection layer.

The chip connection external circuit 40 includes a chip connection external input/output (I/O) circuit as the chip connection external circuit 42, and at least one electrostatic discharge (Electrostatic Discharge, ESD) protection circuit as the chip connection external circuit 43, such as As shown in FIG. 8D , the chip connection circuit 43 includes two electrostatic discharge protection circuits. In the above content, the off-chip input/output circuit can be an off-chip driver, an off-chip receiver or an off-chip buffer (such as on-chip tri-state buffer), and the related contents are respectively shown in FIG. 11A , described in FIG. 11B, FIG. 11C and FIG. 11E; in addition, the electrostatic discharge protection circuit may be a structure composed of two reverse-biased diodes (reverse-biased diode) 4331, 4332, as shown in FIG. 11F. The size of the MOS transistor in the chip-connected external input/output circuit versus the size of the MOS transistor in the internal circuit will be described in the subsequent series of Figure 15.

Fig. 8A, Fig. 9A and Fig. 10A are the design structures of existing wafers, as shown in the figure, all circuits (including internal circuits 21, 22, 23, 24 and chip-connected external circuit 40) are connected through thin line metal structure 638 , 6311, 6321 (including 6321a, 6321b, 6321c), 6341, 6391' are connected to each other. However, there is no use of metal lines or planes above the protective layer to connect all circuits. Only when the contact structure is tin When the lead bump 89t is used, a reconfiguration metal line 83t above the protective layer is used to reconfigure the position of the external connection pad.

Please also refer to FIG. 9B and FIG. 10B , which are a schematic top view and a schematic cross-sectional view of the circuit design shown in FIG. 8B , respectively. An internal circuit 21 is connected to the contact pad 8310 or the contact structure 89 through the following path, so that the signal generated by the internal circuit 21 is transmitted to an external circuit: the internal circuit 21 first passes through a thin line metal structure 631, and then passes through A passivation layer opening 531 continues to pass through a single layer (such as the patterned metal layer 831 in FIG. 10B ) or a multi-layer metal line or plane 83, and then passes through a passivation layer opening 539' and a fine line metal structure 639' downward. It is connected to the input node of the chip external circuit 42, and the output node of the chip external circuit 42 is connected to the signal contact of the chip external circuit 43 as an electrostatic discharge protection circuit through a thin line metal structure 69, and then passes through a The fine line metal structure 639 and a passivation layer opening 539 are finally connected to the contact pad 8310 or the contact structure 89 through a metal line or plane 83r as a reconfiguration line over the passivation layer. In addition, the connection between the chip-connected external circuit 42 and the chip-connected external circuit 43 can also be achieved by using metal lines or planes above the protective layer, that is, using both the thin line metal structure and the metal lines or planes above the protective layer. Substitute fine line metal structure 69 .

Please refer to FIG. 10C , which discloses that the metal line or plane 83 has two patterned metal layers 831 , 832 similar to those shown in FIG. 7C . In addition, FIG. 10D and FIG. 10E are similar to FIG. 10B and FIG. 10C except that a polymer layer 95 is added between the protection layer 5 and the bottom end of the patterned metal layer 831 . Referring to FIG. 10D , the original metal pad 6390 can be reconfigured to the contact pad 8310 on the passivation layer 5 by using the metal line or plane 83r as the reconfiguration line. Using reconfiguration lines to reconfigure I/O pads is particularly useful on stacked package flash, DRAM or SRAM chips. In addition, the I/O pads of a DRAM chip are usually designed roughly along the center line of the chip, so it cannot be used in a stacked package. However, reconfiguring the central pads to the periphery of the chip using metal lines or planes 83r as reconfiguration lines allows the chip to be used on wire bonds in packages such as stacked packages.

Please also refer to FIG. 10F and FIG. 10G , which are specific examples of the contact pads 8310 having a wire bond respectively. In FIG. 10F and FIG. 10G, a static random access memory unit, a flash memory unit or a dynamic random access memory unit is connected to the input node Xi in the internal circuit 21, and the relevant internal circuit 21 and the memory unit are connected to the internal circuit 21 has been illustrated in FIG. 5F to FIG. 5J respectively. First please refer to FIG. 10F, a static random access memory unit, a flash memory unit or a dynamic random access memory unit is connected to the external circuit through: (1) sense amplifier; (2) internal buffer, through circuit , latch circuit, through circuit and internal driver or latch circuit and internal driver; (3) thin line metal structure 6311; (4) thin line metal structure 638; (5) connected to a The input node of the chip connected to the external circuit 42; (6) connect the thin line metal structure 6391 via the output node of the chip connected to the external circuit 42, and connect to a chip connected to the external circuit 43 as an electrostatic discharge protection circuit through the thin line metal structure 69; (7) a protective layer opening 539; (8) pass through a metal line or plane 83r as a reconfiguration line; (9) pass through a contact pad 8310 exposed by a polymer layer opening 9939; and (10) pass through A bond wire 89' on the contact pad 8310 is connected to external circuitry. Again, referring to Fig. 10G, a static random access memory unit, a flash memory unit or a dynamic random access memory unit is connected to the external circuit via: (1) sense amplifier; (2) internal tri-state buffer , through circuit, latch circuit, through circuit and internal driver or latch circuit and internal driver; (3) thin line metal structure 631; (4) pass through protective layer opening 531 upward; (5) polymer layer opening 9531 (6) patterned metal layer 831; (7) down through the polymer layer opening 9539'; (8) protective layer opening 539'; (9) connected to a chip connected to the external circuit 42 through the thin line metal structure 639' (10) connect the thin line metal structure 639 via the output node of the chip connection external circuit 42, and connect to a chip connection external circuit 43 as an electrostatic discharge protection circuit through the thin line metal structure 69; (11) protective layer Opening 539; (12) polymer layer opening 9539; (13) through a metal line or plane 83r as a reconfiguration line; (14) through contact pad 8310 exposed by a polymer layer opening 9939; and ( 15) Connect to an external circuit through a bonding wire 89 ′ on the contact pad 8310 .

In addition, a polymer layer may be formed below or above the metal line or plane 83r as a reconfiguration line. For example, in FIG. A top polymer layer 99 is formed. In addition, the metal line or plane 83r as the reconfiguration line can be formed (by electroplating or electroless plating), or formed by a copper layer (formed by electroplating) with a thickness ranging from 2 microns to 100 microns (preferably between 3 microns to 20 microns). Wherein, there is a nickel layer (thickness between 0.5 micron and 5 micron) and an assembly metal layer of gold, palladium or ruthenium (thickness between 0.05 micron and 5 micron) on top of the copper layer. A wire bond is performed on the surface of the gold, palladium or ruthenium layer on the contact pad 8310 .

When signals are transmitted to external circuits or components, some chips need to be connected to external circuits to (1) drive external circuits or components that require high current loads; (2) detect noise-containing signals (noisysignal) from external circuits or components; And (3) protecting the internal circuit from being damaged by surge signals from external circuits or components. Please refer to FIG. 11A , FIG. 11B , and FIG. 11E and FIG. 11G , which respectively disclose an example of using the off-chip driver 421 , the off-chip driver 422 and the internal tri-state buffer as the off-chip circuit 42 . In FIG. 11A , it is a chip-connected external driver 421 in two-stage cascade. In order to drive external circuits (packaging, other chips or components, etc.) that require heavy loads, the chip-connected external driver 421 is designed to generate a large current. Alternatively, the off-chip driver can be formed using a CMOS serial driver. The series driver may include several stages of inverters. The output current of an on-chip driver is related to the number of stages and the size of the transistors used in each stage of the on-chip driver (W/L, the ratio of channel width to channel length of metal oxide semiconductor transistors, more precisely refers to metal oxide The ratio of the effective channel width of a half transistor to the effective channel length) is proportional.

In FIG. 11A, the first stage 421' of the chip-connected external driver 421 is an inverter, which is formed by an N-type metal-oxide-semiconductor transistor 4201 and a P-type metal-oxide-semiconductor transistor 4202, and the N-type metal-oxide-semiconductor transistor 4201 The size of the P-type metal oxide semiconductor transistor 4202 is greater than the size of the internal circuit (such as the size of the internal circuits 21, 22, 23, 24 of the first embodiment, the second embodiment, the third embodiment and the subsequent fourth embodiment ). In addition, the first stage 421' of the off-chip driver 421 receives a signal from the internal circuit 21, 22, 23, 24 at the input node F. In addition, the second stage 421" of the chip-connected external driver 421 is also an inverter, which is formed by a larger-sized N-type metal-oxide-semiconductor transistor 4203 and a P-type metal-oxide-semiconductor transistor 4204. The chip-connected external driver 421 provides A driving current, the driving current is in the range between 5 milliamps (milia amperes, mA) to 5 amperes (amperes, A), and preferably in the range between 10 milliamperes and 100 milliamperes In order to achieve these target output drive currents, the size of the NMOS transistor 4203 of the second stage 421″ (in other words, the output stage of the on-chip driver 421) is in the range of 20 to 20,000, and A range between 30 and 300 is preferred. In addition, because the driving current of a P-type MOS transistor is about half of that of an N-type MOS transistor. Therefore, the size of the P-type metal-oxide-semiconductor transistor 4204 of the second stage 421″ (in other words, the output stage of the chip connected to the external driver 421) is between 40 and 40,000, and the size is between 60 and 600. The range between is better. However, for a power chip (power chip) or a power management chip (power management chip), the drive current must be larger, such as 10 amps or 20 amps, and its drive current is between In the range between 500 milliamps and 50 amps, and preferably between 500 milliamperes and 5 amps. Therefore, a chip of a power supply chip or a power management chip is connected to the N-type gold of the external driver Oxygen-semiconductor transistors range in size from 2,000 to 200,000, preferably in the range of 2,000 to 20,000, and P-type metal-oxide-semiconductor transistors range in size from 4,000 to 400,000 range, and the range between 4,000 and 40,000 is the preferred one. In addition, please refer to FIG. 11D , the chip-connected external driver 421 can connect multiple inverters in parallel in the second stage 421 ", so that the first The two-stage 421" driver can provide N-type MOS transistors and P-type MOS transistors with larger dimensions (the ratio of the channel width to the channel length), so the chip-connected external driver 421 can provide a larger drive current , wherein in the driver of the second stage 421", the N-type metal oxide semiconductor transistors of multiple inverters are connected to the gates of P-type metal oxide semiconductor transistors, and the N-type metal oxide semiconductor transistors of multiple inverters are connected to each other. The half transistor is connected with the drain of the PMOS transistor. In addition, FIG. 8E , FIG. 9C , and FIG. 10H are a schematic circuit diagram, a top view schematic diagram, and a cross-sectional schematic diagram, respectively, of this embodiment applying the circuit design of FIG. 11D . Please refer to FIG. 11G , the chip-connected external driver 421 can also form a cascaded driver (cascaded driver) by means of connecting multiple inverters in series after the first stage 421', and increase the size of the inverter step by step. device to make the chip connect to the external driver 421 to amplify the signal step by step, wherein the size of the N-type MOS transistor and the P-type MOS transistor (the ratio of the channel width divided by the channel length) of the subsequent inverter is respectively greater than The size of the N-type metal-oxide-semiconductor transistor and the P-type metal-oxide-semiconductor transistor of the previous stage inverter (the ratio of the channel width divided by the channel length), the optimal magnification is the magnification of the natural exponent (e, natural exponent), In addition, the connection mode is that the drains of the N-type MOS transistor and the P-type MOS transistor of the previous stage inverter are connected to the N-type MOS transistor and the P-type MOS transistor of the subsequent stage inverter. The gate of the oxygen-semiconductor transistor. In addition, FIG. 8F , FIG. 9D and FIG. 10I are circuit schematic diagrams, top view schematic diagrams, and cross-sectional schematic diagrams, respectively, of this embodiment applying the circuit design of FIG. 11G .

Please refer to FIG. 11B , which is a two-stage series-connected chip external receiver 422. This chip external receiver 422 can receive signals from an external circuit (not shown in the figure) and output the signal to the input of the internal circuit. node. The first stage 422' of the off-chip receiver 422 (close to the external circuit) is an inverter, which is formed by an N-type metal oxide semiconductor transistor 4205 and a P-type metal oxide semiconductor transistor 4206, and the N-type metal oxide semiconductor transistor 4206 The half transistor 4205 and the PMOS transistor 4206 have dimensions designed to detect an external signal including noise. The first stage 422' of the off-chip receiver 422 receives a noise-containing signal from an external circuit or component at point E (it may be a signal from another chip). The second stage 422″ of the chip-connected external receiver 422 is also an inverter, which is formed by a larger-sized N-type metal-oxide-semiconductor transistor 4207 and a P-type metal-oxide-semiconductor transistor 4208. The chip-connected external receiver 422 The second stage 422" is used to restore the integrity of the noisy external signal to the internal circuit.

Please refer to FIG. 11C , which is an example of an on-chip tri-state buffer as an on-chip external driver, and the on-chip tri-state buffer can output signals to a bus (bus), and then transmit them to multiple logic gates . The on-chip tri-state buffer in FIG. 11C can be regarded as a gate inverter. When the enabling signal (enabling signal) En is high level (En is low level), the chip tri-state buffer allows the signal from the internal circuit to be transmitted to the external circuit, and when the signal En is low level, the internal circuit It is cut off from the external circuit. In this case, on-chip tri-state buffers are used to drive the external data bus. In addition, the size range of the NMOS transistor 4209 and the PMOS transistor 4210 related to the on-chip tri-state buffer used as the external driver of the chip has been described in FIG. 11A and will be further illustrated in the series of FIG. 15 .

Please refer to FIG. 11E , which is an example of an on-chip tri-state buffer as an off-chip receiver. When the enabling signal En is at a high level (En is at a low level), the chip tri-state buffer allows the signal from the external circuit to be transmitted to the internal circuit, and when the signal En is at a low level, the internal circuit communicates with the external circuit cut off. In this case, the on-chip tri-state buffer is at node E receiving the signal from the external data bus. In addition, the size range of the NMOS transistor 4209 and the PMOS transistor 4210 related to the on-chip tri-state buffer used as the off-chip receiver is described in FIG. 11B and will be further explained in the series of FIG. 15 .

The above examples are for CMOS level signals. If the external signal is a transistor-transistor logic (TTL) level, a CMOS/TTL buffer is required, and if the external signal is an emitter coupled logic (ECL) level, then A CMOS/ECL interface buffer is required. A single-pole or multi-pole inverter can be added between the internal circuit and the on-chip tri-state buffer.

Please refer to FIG. 11F , which further discloses an example of an OEO receiver 422 having an OEO receiver 43 as an ESD protection circuit. In this example, the off-chip circuit 43 serving as the ESD protection circuit includes two reverse-biased diodes 4331 , 4332 . The bottom reverse biased diode 4331 can be reverse biased between the external input voltage (the voltage at point E) and the ground reference voltage Vss, while the top reverse biased diode 4332 can be reverse biased between the external input voltage and the power supply voltage Vdd for reverse bias. When the external input voltage from an external circuit suddenly increases to exceed the supply voltage Vdd, the current will be discharged through the top reverse bias diode 4332, and when the external input voltage is lower than the ground reference voltage Vss, the current will be discharged Through the reverse biased diode 4331 at the bottom. Therefore, the input voltage to the internal circuit will be maintained between the power supply voltage Vdd and the ground reference voltage Vss, and the off-chip receiver 422 or semiconductor components in the internal circuit 20 will be protected from electrostatic damage.

Fourth embodiment: design structure of power/ground reference voltage bus.

In the first embodiment of the present invention, an external power supply is input voltage to the internal circuit 20 (including 21, 22, 23, 24) via a voltage stabilizer or transformer 41, and in this embodiment, an external power supply It is a direct input voltage to the internal circuit 20 (including 21, 22, 23, 24), but in this case, it is necessary to use an electrostatic discharge protection circuit 44 to prevent the voltage or current surge (surge) generated by the external power supply. ).

First, please refer to FIG. 12A , which is the related prior art of this embodiment. In FIG. 12A, an external voltage Vdd is input through a protective layer opening 549, and then distributed to the internal circuit 21 through the thin line metal structures 618, 6111, 6121 (including 6121a, 6121b, 6121c), 6141 located under the protective layer 5. , 22, 23, 24 a power supply node Tp, Up, Vp, Wp. The power node Dp of an ESD protection circuit 44 is connected to the thin-line metal structure 618 via a thin-line metal structure 6491 . 13A and 14A are schematic top views and schematic cross-sectional views corresponding to FIG. 12A .

Next, as shown in Figures 12B to 12C, Figures 13B to 13C and Figures 14B to 14D, they are respectively a schematic diagram of the circuit structure, a schematic top view and a schematic cross section of the fourth embodiment of the present invention, as shown in the figure, a The electrostatic discharge protection circuit 44 is connected in parallel with the internal circuits 21, 22, 23, 24 through the metal lines or the plane 81 and/or the metal lines or the plane 82 on the protective layer 5, wherein the internal circuits 21, 22, 23, 24 are such as NOR gate, NAND gate, AND gate, OR gate, operational amplifier, adder, multiplexer, Duplexer (diplexer), multiplier (multiplier), analog/digital converter (A/D converter), digital/analog converter (D/A Converter), complementary metal oxide semiconductor, bicarrier complementary metal Oxide semiconductor, bipolar circuit, static random access memory cell (SRAM cell), dynamic random access memory cell (DRAM cell), non-volatile memory cell (non-volatile memory cell), flash memory cell (flash memory cell), programmable read-only memory cell (EPROM cell), read-only memory cell (ROM cell), magnetic random access memory (magnetic RAM, MRAM) cell, or sense amplifier (sense amplifier). The internal circuits 21, 22, 23, 24 are at least composed of an N-type metal oxide semiconductor transistor (NMOS transistor) with a channel width/channel length ratio between 0.1 and 5 or between 0.2 and 2, or a channel width A P-type metal-oxide-semiconductor transistor (PMOS transistor) with a channel length ratio between 0.2 and 10 or between 0.4 and 4, and the current flowing through the metal lines or the planes 81 and 82 at this time is, for example, the intervening Between 50 microamperes and 2 milliamperes or between 100 microamperes and 1 milliamperes, and the metal lines or planes 81, 82 are formed on the metal lines or planes 81, 82, such as by using a wire, and then electrically connected to a External power supply; in addition, the electrostatic discharge protection circuit 44 is, for example, a reverse-biased diode (reverse-biased diode) 4333, as shown in FIG. 12E, which has a power contact and a ground contact. In addition, in the first embodiment shown in the series of Figures 1, 2 and 3, an electrostatic discharge protection circuit can also be added, and the voltage stabilizer or transformer 41 and the internal circuits 21, 22, 23, 24 can be connected in parallel .

In Fig. 12B and Fig. 13B, the electrostatic discharge protection circuit 44 and the internal circuit 20 (including 21, 22, 23, 24) all include a power node (power node) and a ground node (ground node), wherein an external voltage Vdd The input node Ep is via the metal line or plane 81 on the protective layer 5, the protective layer openings 511, 512, 514 of the protective layer 5, and the thin line metal structures 611, 612 (including 612a, 612b, 612c) under the protective layer 5 , 614, connected to a power node (power node) Tp, Up, Vp, Wp of the internal circuit 21, 22, 23, 24, and then distribute the external voltage Vdd to the power node Tp of the internal circuit 21, 22, 23, 24 , Up, Vp, Wp. In addition, the node Ep is also connected to a power node Dp of an ESD protection circuit 44 via the metal line or plane 81 on the passivation layer 5 , the passivation layer opening 549 of the passivation layer 5 and the thin line metal structure 649 under the passivation layer 5 .

FIG. 14B is a schematic cross-sectional view corresponding to FIG. 12B . In FIG. 14B , patterned metal layer 811 as metal line or plane 81 includes an adhesion/barrier/seed layer 8111 and a thick metal layer 8112 . FIG. 12C discloses the connection of a ground reference voltage Vss in addition to the connection of the external voltage Vdd as shown in FIG. 12B.

In FIG. 12C and FIG. 13C , the node Eg where the ground reference voltage Vss is input is via the metal line or plane 82 on the protective layer 5 , the protective layer openings 521 , 522 , 524 of the protective layer 5 and the fine line metal under the protective layer 5 . The structures 621 , 622 (including 622 a , 622 b , 622 c ), 624 are connected to a ground node Ts, Us, Vs, Ws of the internal circuits 21 , 22 , 23 , 24 . In addition, the node Eg is also connected to a ground node Dg of the ESD protection circuit 44 via the metal 82 on the passivation layer 5, the passivation layer opening 549' of the passivation layer 5, and the thin line metal structure 649' under the passivation layer 5.

FIG. 14C is a schematic cross-sectional view corresponding to FIG. 12C . FIG. 14C discloses that there are two patterned metal layers above the protection layer, wherein the patterned metal layer 821 is used for the ground reference voltage Vss connection, and the patterned metal layer 812 is used for the power Vdd connection. The patterned metal layer 821 includes an adhesion/barrier/seed layer 8211 and a thick metal layer 8212 , while the patterned metal layer 812 includes an adhesion/barrier/seed layer 8121 and a thick metal layer 8122 . FIG. 14D is similar to FIG. 14B except that a polymer layer 95 is formed between the passivation layer 5 and the bottommost end of the patterned metal layer 811 as the metal line or plane 81 .

Please refer to Fig. 12D, which is similar to Fig. 12C, the difference is that Fig. 12C has only one ESD protection circuit 44, while Fig. 12D has two ESD protection circuits 44, 45, wherein this ESD protection circuit 45 is, for example, a reverse biased diode. In FIG. 12D, the electrostatic discharge protection circuits 44, 45 and the internal circuit 20 (including 21, 22, 23, 24) all include a power supply node and a ground node, and an external voltage Vdd is passed through the metal line on the protective layer 5 or The plane 81, the protective layer openings 511, 512, 514 of the protective layer 5 and the thin line metal structures 611, 612a, 612b, 612c, 614 under the protective layer 5 are input to a power supply node of the internal circuit 21, 22, 23, 24 Tp, Up, Vp, Wp, and then distribute the external voltage Vdd to the power supply nodes Tp, Up, Vp, Wp of the internal circuits 21 , 22 , 23 , 24 . In addition, the external voltage Vdd is also input to the electrostatic discharge protection circuits 44, 45 via the metal lines or planes 81 on the protective layer 5, the protective layer openings 549, 559 of the protective layer 5, and the thin line metal structures 649, 659 under the protective layer 5. A power supply node Dp, Dp'. In addition, a ground reference voltage Vss is passed through the metal line or plane 82 on the protective layer 5, the protective layer openings 521, 522, 524 of the protective layer 5, and the thin line metal structures 621, 622a, 622b, 622c, 624 is input to a ground node Ts, Us, Vs, Ws of the internal circuits 21, 22, 23, 24. In addition, the ground reference voltage Vss is also connected to the electrostatic discharge protection circuit 44 via the metal 82 on the protective layer 5, the protective layer openings 549', 559' of the protective layer 5, and the thin line metal structures 649', 659' under the protective layer 5. , a ground node Dg, Dg' of 45 .

In addition, other relevant content of this embodiment is the same as that of the first embodiment, the second embodiment and the third embodiment, and will be described in the subsequent series of Fig. 15, Fig. 16, Fig. 17, Fig. 18 and Fig. 19 in further detail.

In addition, the reconfiguration circuit described in the third embodiment can also be applied to the first embodiment and the fourth embodiment of the present invention, that is, in the first embodiment and the fourth embodiment, it is used to accept external voltage Contact pads for Vdd or ground reference voltage Vss (such as contact pads 8110, 8120 in FIGS. Contact pads at different positions, so that the positions of the contact pads at different positions are consistent with the metal pads of the thin line metal structure (such as the metal pads 6190, 6290 in FIGS. 3B to 3D, and the metal pads in FIGS. 14B to 14D). The pads 6490, 6490') are located in different positions, and then use a wire or bump on the contact pads in the different positions to connect to the external circuit.

Formation method of over-paeeivation structure and related description

In all embodiments of the invention (first, second, third and fourth embodiments), the over-passivation structure is mainly characterized by a thick patterned metal layer (thickness between 2 microns and 200 microns) and thick dielectric layers (thickness between 2 microns and 300 microns). Figure 15 series and Figure 16 series disclose an embossing (embossing) process and a double embossing (double embossing) process, which can be used to fabricate the patterned metal layer and dielectric above the protective layer in all embodiments of the present invention. layer. In these two processes (Figure 15 series and Figure 16 series), it uses polymer material (polymer material) as the dielectric layer, and is formed on each patterned metal layer, between each patterned metal layer And/or under each patterned metal layer. In addition, the series of FIGS. 15 and 16 are based on FIG. 10E in the third embodiment, and use it as an example to illustrate the methods for forming structures above the protective layer in all embodiments of the present invention. In other words, the methods described below and their related descriptions are applicable to all embodiments of the present invention.

The processing of forming the structure above the protective layer starts after the processing of the integrated circuit wafer (IC wafer). Please refer to FIG. 15A, which discloses a starting material (starting material) for forming the structure above the protective layer. As shown in the figure, the process of forming the structure above the protective layer is started in a traditional semiconductor manufacturing plant (IC On an integrated circuit wafer 10 manufactured by fab), this wafer 10 includes:

(1) Substrate1

The substrate 1 is usually a silicon substrate, and the silicon substrate can be an intrinsic silicon substrate, a p-type silicon substrate or an n-type silicon substrate. For high-performance chips, silicon-germanium (SiGe) or silicon-on-insulator (SOI) substrates are used. Wherein, the silicon germanium substrate includes a silicon germanium epitaxial layer (epitaxial layer) on the surface of the silicon substrate, and the silicon substrate on the insulating layer includes an insulating layer (preferably silicon oxide) on a silicon substrate, and a An epitaxial layer of silicon or silicon germanium is formed on the insulating layer.

(2) Component layer (device layer) 2

The device layer 2 generally includes at least one semiconductor device, and the device layer 2 is in and/or on the surface of the substrate 1 . Wherein, the semiconductor component can be a metal oxide semitransistor (MOS transistor) 2 ', for example N type metal oxide semitransistor (NMOS transistor, n-channel MOS transistor) or P type metal oxide semitransistor (PMOS transistor, p-channel MOS transistor) transistor), and the metal-oxide-semiconductor transistor 2' includes a source 201, a drain 202, and a gate 203, and the gate 203 is usually a polysilicon (poly silicon), a polycrystalline tungsten silicide (tungstenpolycide), A tungsten silicide, a titanium silicide, a cobalt silicide or a salicide gate. In addition, the semiconductor component can also be bipolar transistor, diffused metal oxide semiconductor (Diffused MOS, DMOS), lateral diffused metal oxide semiconductor (Lateral Diffused MOS, LDMOS), charge coupled device (Charged-Coupled Device , CCD), complementary metal oxide semiconductor (CMOS) sensing components, photo-sensitive diodes (photo-sensitive diode), resistance components (formed due to the polysilicon layer or diffusion region in the silicon substrate). Various circuits can be formed using these semiconductor components, such as complementary metal oxide semiconductor (CMOS) circuits, N-type metal oxide semiconductor circuits, P-type metal oxide semiconductor circuits, bicarrier complementary metal oxide semiconductor (BiCMOS) circuit, complementary metal oxide semiconductor sensor circuit, diffused metal oxide semiconductor power supply circuit, lateral diffused metal oxide semiconductor circuit, etc. In addition, the component layer 2 also includes an internal circuit 20 (including 21, 22, 23, 24) in all embodiments, a voltage regulator or a transformer 41. In the first embodiment, the chip is connected to an external circuit 40 (including 42, 43) In the third embodiment, and the electrostatic discharge protection circuit 44 is in the fourth embodiment.

(3) Fine-line scheme 6

The fine-line structure 6 includes a plurality of fine-line metal layers (fine-line metal layer) 60, a plurality of fine-line dielectric layers (fine-line dielectric layer) 30 and a plurality of openings 30' in the fine-line dielectric layer 30 The conductive plug (fine-line via plug) 60' inside. In addition, the thin-line metal structure 63 includes the thin-line metal layer 60 and the conductive plug 60', and the thin-line metal structure 63 includes in the present invention: (1) thin-line metal structures 611, 612 (including 612a, 612b, and 612c) , 614, 619, 619', 621, 622 (including 622a, 622b and 622c), 624, 629 in the first embodiment; (2) fine line metal structures 631, 632 (including 632a, 632b and 632c), 634 in The second embodiment; (3) thin line metal structures 631, 632 (including 632a, 632b and 632c), 634, 639, 639' in the third embodiment; (4) thin line metal structures 611, 612 (including 612a, 612b and 612c), 614, 649, 659, 621, 622 (including 622a, 622b and 622c), 624, 649' and 659' are in the fourth embodiment.

The fine line metal layer 60 may be an aluminum layer or a copper layer, or more specifically, may be an aluminum layer formed by sputtering or a copper layer formed by damascene. Therefore, the thin line metal layer 60 can be: (1) all the thin line metal layers 60 are aluminum layers; (2) all the thin line metal layers 60 are copper layers; (3) the bottom thin line metal layer 60 or (4) the bottom metal layer 60 is a copper layer, and the top metal layer 60 is an aluminum layer. In addition, the thickness of each fine line metal layer 60 is between 0.05 micron (μm) and 2 micron, and preferably between 0.2 micron and 1 micron, and the thin line metal layer 60 is if If it is a circuit, its lateral design standard (width) is between 20 nanometers (nano-meter) and 15 micrometers, and preferably between 20 nanometers and 2 micrometers.

In the above content, the aluminum layer is usually formed by physical vapor deposition (Physical Vapor Deposition, PVD), for example, by sputtering (sputtering), and then deposited with a thickness between 0.1 microns and 4 microns. A photoresist layer (preferably between 0.3 microns and 2 microns) is used to pattern the aluminum layer, and then a wet etching or a dry etching (dry etching) is performed on the aluminum layer, preferably The method is dry plasma (dry plasma) etching (usually containing fluorine plasma). In addition, an adhesion/barrier layer (adhesion/barrier layer) can be selectively formed under the aluminum layer, wherein the adhesion/barrier layer can be titanium, titanium-tungsten alloy, titanium nitride or a composite layer formed of the above materials ; On the aluminum layer, an anti-reflection layer (such as titanium nitride) can also be selectively formed. In addition, the opening 30' can be selectively filled by chemical vapor deposition (CVD) tungsten metal, and then the tungsten metal layer is polished by chemical mechanical polishing (CMP) to form the metal plug 60' .

In addition, in the above content, the copper layer is usually formed by electroplating and damascene process, which is described as follows: (1) Deposit a copper diffusion barrier layer (for example, the thickness is between 0.05 micron and 0.25 micron (2) using plasma-assisted chemical vapor deposition (plasmaenhanced CVD, PECVD), spin-oncoating (spin-oncoating) or high-density plasma chemical vapor deposition (High Density Plasma CVD, HDPCVD) deposits a thin line dielectric layer 30 with a thickness between 0.1 micron and 2.5 microns, wherein the thin line dielectric layer 30 is preferably with a thickness between 0.3 micron and 1.5 micron; (3) Patterning the fine line dielectric layer 30 by depositing a photoresist layer with a thickness between 0.1 micron and 4 microns, wherein the thickness of the photoresist layer is preferably between 0.3 micron and 2 microns Or, then expose and develop the photoresist layer to form multiple openings and/or multiple trenches in the photoresist layer, and then remove the photoresist layer; (4) deposit the photoresist layer by sputtering or chemical vapor deposition An adhesion/barrier layer and a seed layer. Wherein, the adhesion/barrier layer includes tantalum, tantalum nitride, titanium nitride, titanium or titanium-tungsten alloy, or a composite layer formed of the above materials. In addition, the seed layer is usually a copper layer, and the copper layer can be formed by sputtering copper metal, chemical vapor deposition of copper metal, or first depositing a copper metal by chemical vapor phase, and then sputtering a copper metal. (5) Electroplating a copper layer with a thickness between 0.05 micron and 2 microns on the seed layer, wherein a copper layer with an electroplated copper layer thickness between 0.2 micron and 1 micron is preferred; (6) Remove the copper layer, seed layer and adhesion/barrier layer that are not in the openings or trenches of the thin-line dielectric layer 30 by grinding (preferably chemical mechanical grinding) the wafer until exposed The fine line dielectric layer 30 under the adhesion/barrier layer. After chemical mechanical polishing, only the metal in the opening or trench remains, and the remaining metal is used as a metal conductor (line or plane) or a conductive plug 60' (connecting two adjacent thin line metal layer 60). In addition, a double-damascene process can also be used to simultaneously form the conductive plug 60' and the metal lines or metal planes in one electroplating process and one chemical mechanical polishing process. Two photolithography processes and two electroplating processes are applicable to dual damascene processes. Dual damascene processing adds more processing steps to deposit and pattern another dielectric layer between the step (3) of patterning a dielectric layer and the step (4) of depositing a metal layer in the single damascene processing described above.

The thin line dielectric layer 30 is formed by chemical vapor deposition, plasma assisted chemical vapor deposition, high density plasma chemical vapor deposition or spin-on. The material of the thin-line dielectric layer 30 includes silicon oxide, silicon nitride, silicon oxynitride, and tetraethoxysilane (PECVD TEOS) formed by plasma-assisted chemical vapor deposition. , spin-on glass (SOG, silicon oxide or siloxane), fluorosilicate glass (Fluorinated Silicate Glass, FSG) or a low dielectric constant (low-K) material, such as black diamond film (Black Diamond, which is Applied Materials' products, the company's translation name is Applied Materials Corporation), ULK CORAL (a product of Novellus) or SiLK (IBM Corporation) low dielectric constant dielectric material. Silicon oxide formed by plasma-assisted chemical vapor deposition, tetraethoxysilane formed by plasma-assisted chemical vapor deposition, or oxide formed by high-density plasma has a dielectric constant K between 3.5 and 4.5; Fluoro-silicate glass formed by plasma-assisted chemical vapor deposition or high-density plasma has a dielectric constant value between 3.0 and 3.5, while low-k dielectric materials have a dielectric constant value between 1.5 Dielectric constant values between to 3.5. Low-k dielectric materials, such as black diamond films, are porous and contain hydrogen, carbon, silicon, and oxygen, and their molecular formula is HwCxSiyOz. The fine-line dielectric layer 30 usually includes inorganic materials to achieve a thickness greater than 2 microns. The thickness of each fine-line dielectric layer 30 is between 0.05 microns and 2 microns. In addition, the opening 30' in the thin line dielectric layer 30 is formed by etching the patterned photoresist layer by wet etching or dry etching, wherein the preferred etching method is dry etching. Types of dry etching include fluorine plasma.

(4) Passivation layer 5

The protective layer 5 plays a very important role in the present invention. Protection layer 5 is an important component in the integrated circuit industry, as described in Volume 2 of "Silicon Processing in the VLSI era" written by S.Wolf in 1990 and issued by Lattice Press, protection layer 5 is in the integrated circuit In-process is defined as the final layer and is deposited on the overall top surface of the wafer. The protective layer 5 is an insulating and protective layer, which can prevent mechanical and chemical damage caused during assembly and packaging. In addition to preventing mechanical scratches, the protective layer 5 can also prevent mobile ions, such as sodium ions, and transition metals, such as gold and copper, from penetrating into the underlying integrated circuit components . In addition, the protection layer 5 can also protect the underlying components and connection lines (fine-line metal structure and thin-line dielectric layer) from moisture intrusion.

The protection layer 5 usually includes a silicon nitride (silicon nitride) layer and/or a silicon oxynitride (siliconoxynitride) layer, and its thickness is between 0.2 microns to 1.5 microns, and the thickness is between 0.3 microns to 1.0 microns The thickness in between is the better one. Other materials used in the protective layer 5 include silicon oxide formed by plasma-assisted chemical vapor deposition, plasma-enhanced tetraethylorthosilicate (PETEOS) oxide, and phosphosilicate glass. (phosphosilicate glass, PSG), borophospho silicate glass (BPSG), oxide formed by high-density plasma (HDP). Next, describe some examples that the protective layer 5 is composed of composite layers, the order from the bottom to the top is: (1) the thickness is between 0.1 micron and 1.0 micron (the preferred thickness is between 0.3 micron and 0.7 micron) oxide/silicon nitride with a thickness between 0.25 microns and 1.2 microns (preferably between 0.35 microns and 1.0 microns), this type of protective layer 5 is usually covered on a metal formed of aluminum On the connection line, the metal connection line formed of aluminum usually includes the processing of sputtering aluminum and etching aluminum; Nitride/Oxide between 0.2 micron and 1.2 micron thick (preferably between 0.1 micron and 0.2 micron thick)/Oxide between 0.2 micron and 1.2 micron thick (preferably between 0.3 micron and 0.5 micron thick) microns)/oxide with a thickness between 0.2 microns and 1.2 microns (preferably between 0.3 microns and 0.6 microns), this type of protective layer 5 is usually covered with copper On the metal connection circuit, the metal connection circuit formed by copper usually includes electroplating, chemical mechanical polishing and damascene processing. In addition, the oxide layer in the above two examples can be silicon oxide formed by plasma-assisted chemical vapor deposition, oxide of plasma-enhanced tetraethyl orthosilicate (Plasma-enhanced tetraethyl orthosilicate, PETEOS), Oxide formed by high-density plasma. The above content is applicable to all the embodiments (the first embodiment, the second embodiment, the third embodiment and the fourth embodiment) of the present invention.

The protection layer opening 50 is formed by wet etching or dry etching, wherein dry etching is a preferred method. In the present invention, the protective layer opening 50 includes: (1) protective layer openings 511, 512, 514, 519, 519', 521, 522, 524 and 529 in the first embodiment; (2) protective layer openings 531, 532 and 534 in the second embodiment; (3) protective layer openings 531, 532, 534, 539 and 539' in the third embodiment; (4) protective layer openings 511, 512, 514, 549, 521, 522 , 524, 549', 559 and 559' in the fourth embodiment. In addition, the size of the protective layer opening 50 is between 0.1 micron and 200 microns, preferably between 1 micron and 100 microns or between 5 microns and 30 microns, and the shape of the protective layer opening 50 can be It is circular, square, rectangular or polygonal, so the size of the above-mentioned protective layer opening 50 refers to the diameter of the circle, the side length of the square, the longest diagonal of the polygon or the width of the rectangle, wherein the length of the rectangle The size is between 1 micron and 1 cm, preferably between 5 microns and 200 microns. For internal circuits, the size of the protective layer openings 531, 532, 534 is between 0.1 micron and 100 microns, preferably between 0.3 micron and 30 microns, for voltage regulators or transformers 41's protective layer openings 519, 519', 529 or for the protective layer openings 539, 539' of the chip-connected external circuits 42, 43 or for the protective layer openings 549, 549', 559, 559' of the electrostatic discharge protection circuit 44 , the size of the opening is relatively large, ranging from 1 micron to 150 microns, preferably 5 microns to 100 microns. In addition, the protective layer opening 50 exposes a metal pad on the uppermost layer of the thin circuit metal layer 60 for electrically connecting the metal circuit or plane on the over-passivation of the protective layer.

A chip 10, such as a silicon wafer (silicon wafer), is manufactured using different generations of integrated circuit processing technology, such as 1 micron, 0.8 micron, 0.6 micron, 0.5 micron, 0.35 micron, 0.25 micron, 0.18 micron, 0.25 micron, 0.13 microns, 90 nanometers (nm), 65 nanometers, 45 nanometers, 35 nanometers, and 25 nanometers technologies, and the generations of these integrated circuit processing technologies are based on the gate length (gatelength) or effective channel length ( channel length) to define. In addition, the size of the wafer 10 is, for example, 5 o'clock, 6 o'clock, 8 o'clock, 12 o'clock, or 18 o'clock. Wafer 10 is fabricated using a photolithographic process that includes coating, exposing, and developing photoresist. The thickness of the photoresist used to fabricate the wafer 10 is between 0.1 μm and 0.4 μm, and the photoresist is exposed by a 5X stepper or scanner. Among them, the multiple of the stepper means that when the light beam is projected from a mask (usually made of quartz) onto the wafer, the figure on the mask is reduced to the ratio of the wafer, and five times (5X) is It means that the proportion of the pattern on the mask is five times that of the pattern on the wafer. Scanners used in the advanced generation of integrated circuit processing technology are usually scaled down by four times (4X) to improve the resolution. The beam wavelengths used by steppers or scanners are 436 nm (g-line), 365 nm (i-line), 248 nm (deep ultraviolet, DUV), 193 nm (DUV), 157 nm (DUV) Or 13.5 nm (extremely short ultraviolet, EUV). In addition, high-index immersion photolithography technology can also be used to complete the thin circuit features of the wafer 10 .

In addition, wafer 10 is fabricated in a cleanroom with class 10 or better (eg, class 1). The maximum number of dust particles per cubic foot allowed in a class 10 clean room is: no more than 1 dust particle greater than or equal to 1 micron, no more than 10 dust particles greater than or equal to 0.5 micron, and no more than 10 dust particles greater than or equal to No more than 30 dust particles of 0.3 micron, no more than 75 dust particles greater than or equal to 0.2 micron, no more than 350 dust particles greater than or equal to 0.1 micron, and the clean room of class 1 allows per cubic foot The maximum number of dust particles per foot is: no more than 1 dust particle greater than or equal to 0.5 micron, no more than 3 dust particles greater than or equal to 0.3 micron, no more than 7 dust particles greater than or equal to 0.2 micron, Contain no more than 35 dust particles greater than or equal to 0.1 micron.

Please refer to Fig. 15B, when copper is used as the fine line metal layer 60, a metal cap 66 (including 661, 662, 664, 669 and 669') is required to protect the exposed part of the protective layer opening 50. The out copper pad (copper pad) prevents the copper pad from being corroded and damaged by oxidation, and can be used as a wire bonding for subsequent chips. The metal top layer 66 includes an aluminum (aluminum) layer, a gold (gold) layer, a titanium (Ti) layer, a titanium-tungsten alloy layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer or a nickel (Ni) layer. Wherein, when the metal top layer 66 is an aluminum layer, a barrier layer (barrier layer) is formed between the copper pad and the metal top layer 66, and the barrier layer includes titanium, titanium-tungsten alloy, titanium nitride, tantalum, Tantalum Nitride, Chromium (Cr) or Nickel. In all embodiments of the present invention, wafer 10 may optionally be formed with metal top layer 66 .

Please refer to FIG. 15C to FIG. 15K , which disclose the processing steps of manufacturing a protective layer upper structure (over-passivation scheme) 8 on the wafer 10 as shown in FIG. 15A or FIG. 15B, wherein this processing step is Two patterned metal layers are formed on the protection layer, and the two patterned metal layers are used to connect the internal circuit and connect the chip to the external circuit. However, although this example only discloses that there are two patterned metal layers above the protective layer, it is also possible to form a patterned metal layer, Three patterned metal layers, four patterned metal layers or more patterned metal layers. In addition, the content described below is applicable to all embodiments of the present invention.

First please refer to shown in FIG. 15K, a structure 8 above a protective layer is formed on a starting material (starting material), and this starting material is a wafer 10 made by a semiconductor manufacturing plant (as shown in FIG. 15A or FIG. 15B) . In addition, the structure 8 above the protective layer includes two parts: a patterned metal layer 80 and a polymer layer (or insulating layer) 90, wherein the patterned metal layer 80 includes one, two, three, four or more layers The metal layer, and the patterned metal layer 80 can be, for example, copper layer and its adhesion/barrier layer (such as chromium or titanium-tungsten alloy) except the topmost patterned metal layer is a gold layer.

All embodiments of the present invention are exemplified by the patterned metal layer 80 comprising one or two patterned metal layers, which include:

(1) Patterned metal layer 801, including (1) 811 and 821 in the first embodiment; (2) 831 (including 831a, 831b) in the second embodiment; (3) 83r, 831 (including 831a, 831b) in the third embodiment; and (4) 811 and 821 in the fourth embodiment.

(2) patterned metal layer 802, including (1) 812 in the first embodiment; (2) 832 in the second embodiment; (3) 832 (including 832a, 832b) in the third embodiment; and (4) 812 in the fourth embodiment.

In addition, the material of the patterned metal layer 80 includes gold, silver, copper, palladium, platinum, rhodium, ruthenium, nickel, and the patterned metal layer 80 constituting the metal circuit or plane is usually a composite layer formed by stacking metals. In FIG. 15K, the patterned metal layer 801 and the patterned metal layer 802 are both a composite layer, wherein the bottom layer of the composite layer is an adhesion/barrier/seed layer (adhesion/barrier/seed layer) 8011, 8021, which are Including: (1) 8111, 8121 and 8211 in the first embodiment; (2) 8311, 8311a, 8311b and 8321 in the second embodiment; (3) 8311, 8311a, 8311b, 8321a and 8321b in the third embodiment and (4) 8111, 8211 and 8121 in the fourth embodiment; in addition, the top layer of the composite layer is a thick metal layer 8012, 8022, which is composed of: (1) 8112, 8122 and 8212 in the first embodiment (2) 8312, 8312a, 8312b and 8322 in the second embodiment; (3) 8312, 8312a, 8312b, 8322a and 8322b in the third embodiment; and (4) 8112, 8212 and 8122 in the Four examples.

In the above content, the adhesion/barrier/seed layer 8011, 8021 includes an adhesion/barrier layer (not shown in the figure) and a seed (seed) layer (not shown in the figure) on the adhesion/barrier layer, The material of the adhesion/barrier layer can be titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten alloy, vanadium, chromium, copper, chrome-copper alloy, tantalum, tantalum nitride, an alloy formed of the above materials or It is a composite layer composed of the above materials. In addition, the adhesion/barrier layer can be formed by means of electroplating, electroless plating, chemical vapor deposition or physical vapor deposition (such as sputtering), among which physical vapor deposition is a preferred formation method , such as metal sputtering processing. In addition, the thickness of the adhesion/barrier layer is between 0.02 micron and 0.8 micron, and preferably between 0.05 micron and 0.2 micron.

The seed layer on the top layer of adhesion/barrier/seed layer 8011, 8021 can facilitate the subsequent electroplating process, and the seed layer is usually formed by physical vapor deposition or sputtering process. In addition, the material used in the seed layer can be gold, copper, silver, nickel, palladium, rhodium, platinum or ruthenium, and is usually the same material as the thick metal layer in the subsequent electroplating process. In addition, the seed layer can be formed by means of electroplating, electroless plating, chemical vapor deposition or physical vapor deposition (such as sputtering), among which physical vapor deposition is a preferred formation method, such as metal sputtering. The thickness of the seed layer is between 0.05 micron and 1.2 micron, preferably between 0.05 micron and 0.8 micron.

The thick metal layers 8012, 8022 are formed of low-resistance conductors, and are usually formed by electroplating. In addition, the thickness of the thick metal layers 8012, 8022 is usually between 0.5 microns and 100 microns, and the thickness is between 3 microns and 100 microns. The thickness between 20 microns is preferred, and the material of the thick metal layer 8012, 8022 can be gold, copper, silver, nickel, palladium, rhodium, platinum or ruthenium, wherein gold, silver, palladium, rhodium, platinum or ruthenium The preferred thickness of copper is between 1.5 microns and 15 microns, the preferred thickness of copper is between 1.5 microns and 50 microns, and the preferred thickness of nickel is between 0.5 microns and 6 microns. In addition, a cap/barrier layer (not shown) can also be optionally formed on the thick metal layers 8012, 8022 for protection or diffusion barrier. The protective/barrier layer can be formed by electroplating, electroless plating, chemical vapor deposition or physical vapor deposition (such as sputtering), and is preferably deposited by electroplating. In addition, the thickness of the protection/barrier layer is in the range of 0.05 microns to 5 microns, and the thickness of 0.5 microns to 3 microns is preferred. The protective/barrier layer can be a nickel layer, cobalt layer or vanadium layer. In addition, an assembly-contact layer (not shown) can be optionally formed on the thick metal layers 8012, 8022 or protection/barrier layers (not shown) on the assembly or package. , especially formed on the topmost thick metal layer or protective/barrier layer (not shown) of the patterned metal layer 80 . This assembly contact layer can be used as wire bonding or as a solder wettable, and then used for wire bonding, gold connection, solder ball mounting or solder connection ). In addition, the assembly contact layer can be gold, silver, platinum, palladium, rhodium or ruthenium. Polymer layer opening 990 (including 9919 and 9929 in the first embodiment; 9939 and 9939' in the third embodiment; and 9949 and 9949' in the fourth embodiment) in the top polymer layer (polymer layer) 99 ) exposing the contact pad (contact pad) 8000 of the topmost patterned metal layer 80 (including 8110 and 8120 in the first embodiment; 8310 and 8320 in the third embodiment; and 8110 and 8120 in the fourth embodiment Example) surface. The exposed assembly contact layer connected to the polymer layer opening 990 can be a bonding wire, a solder ball (formed by electroplating or connected to a solder ball by soldering), a metal ball (such as A tin-silver alloy formed by electroplating or a tin-silver alloy connected by soldering), a metal bump on other substrates or chips, a gold bump on other substrates or chips , a metal post on other substrates or chips, or a copper post on other substrates or chips. For integrated circuit contact pads made of sputtered aluminum or electroplated copper (formed by chemical mechanical polishing damascene processing), the metal lines or planes above the protective layer can be as follows One of the types, from bottom to top is: (1) titanium tungsten alloy/gold seed layer formed by sputtering/gold formed by electroplating; (2) titanium/gold formed by sputtering Seed layer/gold by electroplating; (3) tantalum/seed layer of gold by sputtering/gold by electroplating; (4) chromium/copper seed layer by sputtering/formation by electroplating (5) titanium-tungsten alloy/copper seed layer formed by sputtering/copper formed by electroplating; (6) tantalum/copper seed layer formed by sputtering/copper formed by electroplating; ( 7) Titanium/copper seed layer formed by sputtering/copper formed by electroplating; (8) chromium, titanium-tungsten alloy, titanium or tantalum/copper seed layer formed by sputtering/copper formed by electroplating / nickel formed by electroplating; (9) chromium, titanium-tungsten alloy, titanium or tantalum / copper seed layer formed by sputtering / copper formed by electroplating / nickel formed by electroplating / gold and silver formed by electroplating , platinum, palladium, rhodium or ruthenium; and (10) chromium, titanium-tungsten alloy, titanium or tantalum/copper seed layer formed by sputtering/copper formed by electroplating/nickel formed by electroplating/nickel formed by electroless plating Formed gold, silver, platinum, palladium, rhodium or ruthenium. The thickness of each patterned metal layer 80 is between 2 microns and 50 microns, and preferably between 3 microns and 20 microns. If the patterned metal layer 80 is a metal circuit, its The lateral design criteria (width) is between 1 micron and 200 microns, preferably between 2 microns and 50 microns, and the patterned metal layer 80 is a metal plane, especially as a power or ground reference The horizontal design standard (width) of the voltage plane is preferably greater than 200 microns. In addition, the minimum distance between two adjacent metal lines or planes is between 1 micron and 500 microns, preferably between 2 microns and 150 microns.

In some applications of the present invention, the metal lines or planes may only include sputtered aluminum with a thickness between 2 microns and 6 microns (preferably between 3 microns and 5 microns) and the A selective adhesion/barrier layer (including titanium, titanium-tungsten alloy, titanium nitride, tantalum or tantalum nitride layer) under the aluminum layer.

Continuing, a contact structure 89 can be optionally formed on the pad 8000 of the patterned metal layer 80 . This contact structure 89 can be a metal bump (metal bump), a solder bump (solder bump), a solder ball (solder ball), a gold bump (gold bump), a copper bump (copper bump), a metal pad, a solder pad, a gold pad, a metal post, a solder post, a gold post or A copper post. An under bump metal (UBM) layer is located under the contact structure 89, and the under bump metal layer includes titanium, titanium-tungsten alloy, titanium nitride, chromium, copper, chrome-copper alloy, tantalum, tantalum nitride , nickel, nickel vanadium alloy, vanadium or cobalt layer, or a composite layer composed of the above materials. The contact structure 89 (including the UBM layer) can be one of the following types, from bottom to top: (1) Titanium/gold pads (the thickness of the gold layer is between 1 micron and 15 microns); (2) titanium-tungsten alloy/gold pads (the thickness of the gold layer is between 1 micron and 15 microns); (3) nickel/gold pads (the thickness of the nickel layer is between 0.5 microns between 0.2 microns and 15 microns); (4) titanium/gold bumps (thickness of the gold layer is between 7 microns and 40 microns); (5) Titanium-tungsten alloy/gold bump (the thickness of the gold layer is between 7 microns and 40 microns); (6) nickel/gold bumps (the thickness of the nickel layer is between 0.5 microns and 10 microns, and the gold layer The thickness is between 7 microns and 40 microns); (7) Titanium, titanium-tungsten alloy or chromium/copper/nickel/gold pads (the thickness of the copper layer is between 0.1 microns and 10 microns, and the gold layer (8) Titanium, titanium-tungsten alloy, chromium, chrome-copper alloy or nickel-vanadium alloy/copper/nickel/gold bump (thickness of copper layer is between 0.1 micron to 10 microns, and the thickness of the gold layer is between 7 microns and 40 microns); (9) titanium, titanium-tungsten alloy, chromium, chrome-copper alloy or nickel-vanadium alloy/copper/nickel/solder pad (copper The thickness of the layer is between 0.1 micron and 10 microns, and the thickness of the solder layer is between 0.2 micron and 30 microns); (10) Titanium, titanium-tungsten alloy, chromium, chrome-copper alloy or nickel-vanadium alloy/copper /Nickel/Solder bumps or solder balls (thickness of the copper layer is between 0.1 micron and 10 microns, and the thickness of the solder layer is between 10 microns and 500 microns); (11) Titanium, titanium-tungsten alloy, Chromium, chrome-copper or nickel-vanadium alloy/copper pillars (the thickness of the copper layer is between 10 microns and 300 microns); (12) titanium, titanium-tungsten alloy, chrome, chrome-copper alloy or nickel-vanadium alloy/copper pillars / Nickel (the thickness of the copper layer is between 10 microns and 300 microns); (13) Titanium, titanium-tungsten alloy, chromium, chrome-copper alloy or nickel-vanadium alloy/copper pillar/nickel/solder (the thickness of the copper layer is between 10 microns and 300 microns, and the thickness of the solder layer is between 1 micron and 20 microns); (14) titanium, titanium-tungsten alloy, chromium, chrome-copper alloy or nickel-vanadium alloy/copper pillar/nickel/ Solder (the thickness of the copper layer is between 10 microns and 300 microns, and the thickness of the solder layer is between 20 microns and 100 microns). In addition, the assembly method can be wire bonding, tape automated bonding (TAB), glass-on-glass packaging (chip-on-glass, COG), chip direct packaging (chip-on-board, COB), goal Flip chip on BGA substrate, chip-on-film (COF), stacked multi-chip package structure (chip-on-chip stack interconnection), stacked chip package structure on silicon substrate (chip-on-Si-substrate stack interconnection) and so on.

Another important feature of the structure 8 above the passivation layer is that polymer material is used as a dielectric layer or insulating layer on, under or between the patterned metal layer 80 . The use of polymeric materials allows the fabrication of dielectric layers with a thickness greater than 2 microns. The thickness of the polymer layer formed of polymer material may be between 2 microns and 100 microns, preferably between 3 microns and 30 microns. The polymer layer 90 (including 95, 98, 99) used on the protective layer 5 can be polyimide (polyimide, PI), phenylcyclobutene (benzocyclobutene, BCB), parylene (parylene), Epoxy-based material, such as epoxy resin or photoepoxy SU-8 provided by Sotec Microsystems in Renens, Switzerland, and elastomer, such as silicone. Alternatively, a solder mask material used in the printed circuit board industry can be used as the top polymer layer 99 (the topmost polymer layer on top of all patterned metal layers 80). Polyimide can be a photosensitive material. In addition, the polyimide may be a non-ionic polyimide, such as ether-based polyimide (PIMEL ^™ ) provided by Asahi Chemical of Japan. In addition, since copper does not diffuse or penetrate into nonionic polyimide, direct contact between copper and polyimide is allowed, and due to the relationship between nonionic polyimide, the protective layer The distance between the copper lines or planes in the structure 8 can be as close as 1 micron, for example, between 1 micron and 5 microns. In other words, the distance between two metal lines or planes can be greater than 1 micron. In addition, when the metal circuit or plane made of copper and the polymer layer covering the metal circuit or plane are non-ionic polyimides, the metal circuit or plane may optionally not need a protective layer (protection cap) ), such as a Ni cap layer. Of course, when forming metal lines or planes, a protective layer such as nickel can also be formed on the copper layer, which can prevent copper ions from diffusing into the polymer layer.

As shown in FIG. 15K, the purpose of forming openings in the polymer layer is to connect different patterned metal layers 80 to each other, to connect to the underlying fine line metal layer 60, or to connect to external circuits. . The polymer layer openings include (1) 9919, 9929, 9829, 9519, 9519', 9511, 9512 and 9514 in the first embodiment; (2) 9831, 9834, 9531, 9532 and 9534 in the second embodiment (3) 9939, 9939', 9831, 9834, 9839, 9539, 9539', 9531, 9532 and 9534 in the third embodiment; and (4) 9949, 9949', 9849', 9549, 9511, 9512 and 9514 in the fourth embodiment. The polymer material can be photo-sensitive or non-photo-sensitive. For photosensitive polymers, it uses exposure and development to define and pattern the openings in the polymer layer, while for non-sensitive photopolymers, it uses a photoresist layer for the first time to polymerize Openings are defined on the object layer, then the photoresist is exposed and developed to form openings in the photoresist, and then the polymer layer exposed by the photoresist openings is wet-etched or dry-etched to form openings in the polymer layer In the process, the formation of openings in the polymer layer is finally completed by removing the photoresist. The size of the openings in the polymer layer is between 2 microns and 1000 microns, preferably between 5 microns and 200 microns. In some designs, however, it is possible for the polymer layer openings to exceed a size of 1,000 microns. In addition, the opening of the polymer layer can be designed as a circle, a corner-rounded square, a rectangle or a polygon.

The polymer layer 95 is located between the passivation layer 5 and the bottommost end of the patterned metal layer 801 . Through the polymer layer opening 950 in the polymer layer 95 , signals, power (Vdd or Vcc) and/or ground reference voltage (Vss) can be transmitted between the fine line metal layer 60 and the patterned metal layer 80 . For the internal circuit 20 (including 21, 22, 23, 24), the polymer layer openings 9531, 9532, 9534 are respectively aligned with the protective layer openings 531, 532, 534, and the size of the polymer layer openings 9531, 9532, 9534 It is between 1 micron and 300 microns, preferably between 3 microns and 100 microns. For voltage regulator or transformer 41, polymer layer openings 9519, 9519', 9511, 9512, 9514 are respectively aligned with protective layer openings 519, 519', 511, 512, 514; 43), the polymer layer openings 9539, 9539', 9531, 9532, 9534 are respectively aligned with the protective layer openings 539, 539', 531, 532, 534; for the electrostatic discharge protection circuit 44, the polymer layer openings 9549, 9511, 9512, 9514 are respectively aligned with the protective layer openings 549, 511, 512, 514, the other polymer layer openings 9519, 9519', 9511, 9512, 9514, or the polymer layer openings 9539, 9539', 9531, 9532, 9534 or The size of the polymer layer openings 9549, 9511, 9512, 9514 can be larger, ranging from 5 microns to 1000 microns, preferably 10 microns to 200 microns. The polymer layer opening 950 on the protective layer opening 50 has two opening types. In the first opening type, the polymer layer opening, such as the polymer layer opening 9531, is larger than the lower protective layer opening 531, and the polymer layer The polymer sidewalls of the layer opening 9531 are located on the protective layer 5 . In this type, a smaller protective layer opening 531 can be formed, thereby forming a smaller contact pad on the top of the thin line metal layer, so this type of opening allows the thin lines of the topmost thin line metal layer to have Higher winding density (routing density); In the second opening pattern, the bottom of the polymer layer opening, such as the bottom of the polymer layer opening 9539, is smaller than the protective layer opening 539 below, and the polymer layer opening ( For example, the polymer sidewall of the polymer layer opening 9539) is on the metal pad on top of the fine line metal layer. In this type, the polymer layer 95 covers the sidewall of the protective layer opening, and the slope of the sidewall of the polymer layer opening (such as the polymer layer opening 9539) is smaller than the slope of the sidewall of the protective layer opening, and the subsequent metal The adhesion/barrier/seed layer 8011 formed by sputtering has better step coverage. Better adhesion/barrier/seed metal step coverage is important for chip reliability because better adhesion/barrier/seed metal step coverage prevents metal from thick metal layers from diffusing into underlying lines or In the polymer layer, to prevent the generation of inter-metallic compound (IMC) or the phenomenon of metal diffusion.

The polymer layer opening 980 in the polymer layer 98 is located between the patterned metal layer 801 and the patterned metal layer 802 . For the internal circuits 21, 22, 23, 24, the size of the polymer layer openings 9831, 9834 is between 1 micron and 300 microns, preferably between 3 microns and 100 microns. For the polymer layer opening 9829 of the voltage regulator or transformer 41, or the polymer layer opening 9831, 9834, 9839 of the chip external circuit 40 (including 42, 43) or the polymer layer opening 9849' of the electrostatic discharge protection circuit 44 The size can be larger, ranging from 5 microns to 1,000 microns, preferably between 10 microns to 200 microns.

The topmost pads of the patterned metal layer 802 exposed by the polymer layer openings 990 in the top polymer layer 99 can be used to connect external circuits, or serve as contact points for probes in chip testing. For the internal circuits 21, 22, 23, 24, the top polymer layer 99 is not provided with polymer layer openings; in addition, the polymer layer openings 9919, 9929 of the voltage regulator or transformer 41, or the chip is connected to the external circuit 40 (including 42, 43) of the polymer layer opening 9939 or the polymer layer opening 9949, 9949' of the ESD protection circuit 44 can be larger in size, ranging from 5 microns to 1,000 microns, and in the range of 10 microns Preferably between 200 microns.

Signals, power or ground reference voltages input into the structure 8 above the protective layer are transmitted to the internal circuit 20 , voltage regulator or transformer 41 , chip-connected external circuit 40 or ESD protection circuit 44 through the thin circuit structure 6 . In addition, the thin-line metal structure 63 may be the thin-line metal layer 60 and the conductive plug 60' formed in the shortest path (for example, in a roughly aligned stack), as shown in 631, 632, 634, and 639 in FIG. 15A with 639'.

The photolithographic technique for fabricating the structures 8 above the protective layer is significantly different from the lithographic technique for fabricating the integrated circuits below the protective layer. The photolithography process above the protective layer also includes coating, exposing and developing the photoresist. There are two types of photoresist used to form the structure 8 above the protective layer, which are: (1) wet film photoresist (liquid photoresist), which is formed by a single or multiple spin coating method or a printing method . The thickness of the wet film photoresist is between 3 microns and 60 microns, preferably between 5 microns and 40 microns; and (2) dry film photoresist (dry film Photoresist), which is Formed by laminating method. The thickness of the dry film photoresist is between 30 microns and 300 microns, preferably between 50 microns and 150 microns. In addition, the photoresist can be positive-type or negative-type, and positive-type thick photoresist is better for better resolution. When the polymer layer is an optically active material, the polymer layer can be patterned only by photolithography (no etching process). The photoresist is exposed using an aligner or a one-fold (1X) stepper. This double (1X) means that when the beam is projected from a mask (usually made of quartz or glass) onto the wafer, the pattern on the mask is reduced to the ratio of the wafer, and the pattern on the mask The scale is the same as the pattern scale on the wafer. The beam wavelengths used by the aligner or double stepper are 436nm (g-line), 397nm (h-line), 365nm (i-line), g/h line (combined with g-line and h-line) or g/h/i line (combined g-line, h-line and i-line). Using a stepper exposure machine (or a double aligner) with a beam wavelength of g/h line or g/h/i line can provide greater exposure for thick photoresists or thick optically active polymers The light intensity (light intensity).

Since the protective layer 5 can protect the metal oxide semiconductor transistor and the thin circuit structure 6 below from the intrusion of water vapor and the penetration of sodium or other mobile ions and gold, copper or other transition metals, so on an integrated circuit wafer The overprotective structure 8 can be processed in a class 10 or less stringent environment (eg class 100) clean room. A class 100 clean room allows the maximum number of dust particles per cubic foot: no more than 1 dust particle greater than or equal to 5 microns, no more than 10 dust particles greater than or equal to 1 micron, and no more than 10 dust particles greater than or equal to No more than 100 dust particles equal to 0.5 microns, no more than 300 dust particles greater than or equal to 0.3 microns, no more than 750 dust particles greater than or equal to 0.2 microns, no more than 0.1 microns dust particles 3500 pieces.

Component layer 2 includes internal circuit 20 (including 21, 22, 23 and 24) in all embodiments, and (1) voltage regulator or transformer 41 in the first embodiment; (2) chip-connected external circuit 40 ( Including 42, 43) in the third embodiment; (3) ESD protection circuit 44 in the fourth embodiment. In all embodiments of the present invention, the internal circuit 20 (including 21 , 22 , 23 , 24 ) includes a signal node, and the signal node is not connected to the external (outside the chip) circuit. And when the signal of the internal circuit 20 needs to be connected to an external circuit, before being connected to the external circuit, the signal must first pass through an on-chip external circuit, such as an on-chip tri-state buffer, an on-chip external driver, an on-chip external receiver or Other chips are connected to external input/output (I/O) circuits. Therefore, the internal circuit does not include the chip connected to the external circuit.

In the present invention, the internal circuit 20 (comprising 21, 22, 23, 24) can also be an inverter (inverter) except that it can be a NOR gate or a NAND gate. ), an AND gate (AND gate), an OR gate (OR gate), a static random access memory unit (SRAM cell), a dynamic random access memory unit (DRAM cell), a non-volatile memory unit (non -volatile memory cell), a flash memory cell, a programmable read-only memory cell (EPROM cell), a read-only memory cell (ROM cell), a magnetic random access memory (magnetic RAM, MRAM ) unit, a sense amplifier (sense amplifier), an operational amplifier (operational amplifier, OpAmp, OPA), an adder (adder), a multiplexer (multiplexer), a duplexer (diplexer), A multiplier (multiplier), an analog/digital converter (A/D converter), a digital/analog converter (D/A converter), a complementary metal oxide semiconductor sensing element unit (CMOS sensor cell), a A photo-sensitive diode, a complementary metal oxide semiconductor, a bipolar complementary metal oxide semiconductor, a bipolar circuit or an analog circuit.

In addition, the internal circuit 20 (including 21, 22, 23, 24) is made of at least one MOS transistor (MOS transistor), for example, a NOR gate, an OR gate, an AND gate or a NAND gate is made of at least one MOS transistor. The other metal oxide semiconductor transistor can be an N-type metal oxide semiconductor transistor with a "channel width (Channel width)/channel length (Channel length)" ratio between 0.1 and 5 or between 0.2 and 2. A transistor, or a P-type metal-oxide-semiconductor transistor with a "channel width/channel length" ratio between 0.2 and 10 or between 0.4 and 4. In the first embodiment, the internal circuit 20 (including 21, 22, 23, 24) can be a power management chip (power management chip) or a power supply chip (power supply chip), the power management chip and the power supply chip It is composed of at least one metal-oxide-semiconductor transistor, and the metal-oxide-semiconductor transistor can be a P-type metal-oxide-semiconductor transistor with a "channel width/channel length" ratio between 4,000 and 400,000 or between 4,000 and 40,000, Or an N-type metal-oxide-semiconductor transistor with a ratio of "channel width/channel length" between 2,000 and 200,000 or between 2,000 and 20,000, and the current flowing through the metal lines or planes 81, 82 is between Between 500mA and 50A or between 500mA and 5mA.

In addition, the internal circuit 20 can be defined by its peak input or output current (that is, the current flowing through the metal line or plane), or by its metal oxide semiconductor transistor size (the ratio of the channel width divided by the channel length) . A chip connects external circuit 40 (comprising 42, 43), also can utilize its peak value input or output current (that is to flow through the electric current of metal line or plane) to define, or with its metal oxide semitransistor size (channel width divided by the ratio of the channel length) to define. The definitions of the internal circuit 20 and the on-chip external circuit 40 (including 42 and 43 ) are applicable to all embodiments of the present invention.

Therefore, the present invention can respectively connect the gate and the gate, the gate and the source, and the gate of at least two metal-oxide-semiconductor transistors in the same line component through the thin line metal structure below the protective layer and the metal line or plane above the protective layer. and drain, source and source, source and drain, or drain and drain.

The dimensional characteristics and electrical characteristics between the patterned metal layer 80 and the fine line metal layer 60 of the overpass structure 8 in all embodiments of the present invention will be described and compared below.

(1) The thickness of the metal circuit

The thickness of each patterned metal layer 80 is between 2 microns and 150 microns, preferably between 3 microns and 20 microns, and the thickness of each fine line metal layer 60 is between 0.05 between microns and 2 microns, and preferably between 0.2 microns and 1 micron.

For a wafer designed according to an embodiment of the present invention, the thickness of the patterned metal layer above a passivation layer is greater than the thickness of any fine line metal layer, and the thickness ratio between the two is between 2 and 250 range, and a range between 4 and 20 is preferred.

(2) The thickness of the dielectric layer

The thickness of the dielectric layer (typically an organic material such as a polymer) above each protective layer, such as the thickness of the polymer layer 90, is between 2 microns and 150 microns, and between 3 microns and 30 microns. The interval is preferred, and the thickness of each thin-line dielectric layer 30 (usually an inorganic material such as oxide or nitride) is between 0.05 micron and 2 micron, and the thickness is between 0.2 micron and 1 micron. Between is the better one.

For the wafer designed according to the embodiment of the present invention, the thickness of the dielectric layer above a passivation layer is greater than the thickness of any thin line dielectric layer, and the thickness ratio between the two is in the range between 2 and 250 , and the range between 4 and 20 is preferred.

(3) sheet resistance (sheet resistance) and resistance of the metal layer

The sheet resistance of a metal layer is calculated by dividing the metal resistivity by the metal thickness. The sheet resistance of a patterned metal layer over a passivation layer of copper (5 microns thick) is approximately 4 mili-ohms per square, while that of gold (4 microns thick) The sheet resistance of the patterned metal layer above the passivation layer is approximately 5.5 milliohms per square. The sheet resistance of the patterned metal layer over a passivation layer is in the range of 0.1 milliohms per square to 10 milliohms per square, and in the range of 1 milliohms per square to 7 milliohms per square The range between is preferable. A fine line metal layer made of aluminum (thickness 0.8 microns) formed by sputtering has a sheet resistance of about 35 milliohms per square, while a fine line metal layer made of copper (thickness 0.9 microns) is formed by damascene processing layer, its sheet resistance is about 20 milliohms. The sheet resistance of a fine line metal layer is in the range of 10 milliohms per square to 400 milliohms per square, and in the range of 15 milliohms per square to 100 milliohms per square is the better one.

The resistance per unit length of a metal line is calculated by dividing the sheet resistance by its width. The lateral design standard (width) of the patterned metal layer above the passivation layer is between 1 micron and 200 microns, preferably between 2 microns and 50 microns, and the lateral design standard of the fine line metal layer (Width) is between 20 nanometers and 15 micrometers, preferably between 20 nanometers and 2 micrometers. The resistance per mm of the patterned metal layer over a protective layer is between 2 milliohms per mm length and 5 milliohms per mm length, and between Preferably between 50 milliohms and 2.5 ohms per millimeter long, and a fine line metal layer with resistance per millimeter between 500 milliohms per millimeter long and 3,000 milliohms per millimeter long, and The preferred one is between 500 milliohms per millimeter and 500 ohms per millimeter.

For the wafer designed according to the embodiments of the present invention, the resistance per unit length of the patterned metal layer above a protective layer is less than the resistance per unit length of any thin line metal layer, and the ratio of the unit length resistance of the two (fine line metal The layer ratio (patterned metal layer above the passivation layer) ranges from 3 to 250, and preferably ranges from 10 to 30.

(4) The unit length capacitance of the metal line (capacitance per unit length)

Capacitance per unit length is related to the type and thickness of the dielectric, the width, distance and thickness of the metal lines, and the surrounding metal in the horizontal and vertical directions. Polyimide has a dielectric constant of about 3.3, while phenylcyclobutene has a dielectric constant of about 2.5. Next, please refer to FIG. 20, which discloses that on the same patterned metal layer 802, a patterned metal layer 802x has two adjacent patterned metal layers 802y and 802z, and There is a patterned metal layer 801w under the patterned metal layer 802 , and the patterned metal layer 801w is separated from the patterned metal layer 802 by a polymer layer 98 . Similarly, FIG. 20 also discloses that on the same fine-line metal layer 602, a thin-line metal layer 602x has two adjacent thin-line metal layers 602y and 602z, and under the thin-line metal layer 602 has A fine-line metal layer 601w, and the thin-line metal layer 601w is separated from the thin-line metal layer 602 by a thin-line dielectric layer 30 .

The capacitance per unit length of the patterned metal layer 802x and the fine line metal layer 602x includes three components: (1) plate capacitance (plate capacitance), Cxw (pF/mm), which is the metal line or plane width divided by the dielectric A function of the ratio of the thickness of the material; (2) coupling capacitance (coupling capacitance), Ccx (=Cxy+Cxz), which is the ratio of the metal line or plane thickness divided by the distance between adjacent metal lines or planes (linespacing) and (3) fringing capacitance (fringing capacitance), Cfx (=Cfl+Cfr), which is a function of the thickness of the metal line or plane, the distance between adjacent metal lines or planes, and the thickness of the dielectric . The capacitance per millimeter of a patterned metal layer is between 0.1pF (picoFarads) per millimeter long to 2pF per millimeter long, and preferably between 0.3pF per millimeter long to 1.5pF per millimeter long, and a The capacitance per millimeter of the fine line metal layer is between 0.2 pF per millimeter and 4 pF per millimeter, and preferably between 0.4 pF per millimeter and 2 pF per millimeter.

For the wafer designed according to the embodiments of the present invention, the capacitance per unit length of a patterned metal layer is smaller than the capacitance per unit length of any thin line metal layer, and the ratio of the unit length capacitance of the two (thin line metal layer to pattern metallization layer) ranges from 1.5 to 20, and preferably ranges from 2 to 10.

(5) The resistance and capacitance constant of the metal line (RC constant)

The signal transmission time on a metal line is calculated using RC delay. Based on the contents of (3) and (4) above, the RC delay of a patterned metal layer is between 0.003 to 10 ps (picosecond) per millimeter, and between 0.25 to 2 ps (picosecond) per millimeter. second) is better, and the RC delay of a thin line metal layer is between 10 to 2000 ps (pico second) per millimeter, and between 40 to 500 ps per millimeter. (pico second) range is the better one.

For the wafer designed according to the embodiments of the present invention, the RC propagation time per unit length of a patterned metal layer is less than the RC propagation time per unit length of any thin line metal layer, and the two The ratio of RC propagation delay time per unit length (thin line metal layer to patterned metal layer) ranges from 5 to 500, preferably 10 to 30.

Next, please refer back to FIG. 15C to FIG. 15L , which disclose the manufacturing steps of forming the structure 8 above the protective layer on the completed wafer 10 (as shown in FIG. 15A or FIG. 15B ). Each patterned metal layer 80 is formed using a relief process (as opposed to a damascene copper process under the passivation layer 5). Referring to FIG. 15C , a polymer layer 95 is deposited on the passivation layer 5 and exposes the metal pads 600 exposed by the passivation layer opening 50 through the polymer layer opening 950 . If the polymer is in liquid form, it can be deposited using spin coating or printing, and if the polymer is a dry film, the dry film can be deposited using a lamination way to form. For the photosensitive polymer, the polymer layer 95 is exposed through the light of an alignment machine or a one-time (1X) stepper exposure machine through the photomask, and forms a polymer layer in the polymer layer 95 by developing. Opening 950; when the polymer is not optically sensitive, a photoresist must be used, and the opening 950 in the polymer layer must be patterned by conventional photolithography. The way of patterning the polymer layer can be the following way: before coating the photoresist, a hard mask (hard mask, such as a silicon monoxide layer, not shown in the figure) can be selectively deposited on the polymer layer 95 , and the hard mask has a slow etch rate during etching of the polymer layer opening. In addition, the way of patterning the polymer layer 95 (that is, the polymer layer 95 has the polymer layer opening 950) can also use a screen printing method, by using a metal mesh with a patterned hole (hole) Plate (metal screen) to form, and the method of screen printing does not require exposure and development. In addition, if the polymer layer is a dry film, holes can be formed in a dry film before lamination to the wafer, so exposure and development are not required in this way. In addition, since the polymer layer 95 can be formed on the protective layer 5, the lowermost patterned metal layer 80 on the protective layer 5 can be formed on a relatively flat plane provided by the upper surface of the polymer layer 95, Therefore, it is possible to prevent leakage current between adjacent lines of the patterned metal layer 80, and to prevent coupling between the patterned metal layer 80 and the thin line metal structure under the protective layer, thereby providing better electrical properties. (electrical performance). In some applications, however, polymer layer 95 may be omitted to save cost. The polymer layer opening 950 is aligned with the protective layer opening 50 , and the polymer layer opening 950 may be larger or smaller than the protective layer opening 50 . In addition, the protective layer opening 50 and the polymer layer opening 950 may also be formed by first depositing the polymer layer 95 on the protective layer 5, then forming the polymer layer opening 950, and finally forming the protective layer opening 50. In this way In the polymer layer opening 950, the size of the opening 950 is about the same as the size of the protective layer opening 50.

的一钛钨合金或钛的黏着/阻障层，接着再溅镀形成厚度1,000埃的一金种子层。对于形成厚金属层的材质为铜时，黏着/阻障/种子层8011的形成是先利用溅镀方式形成厚度500埃的一铬金属的黏着/阻障层、形成厚度1,000埃的一钛金属的黏着/阻障层或者是形成厚度3,000埃的一钛钨合金的黏着/阻障层，接着再溅镀形成厚度5,000埃的一铜种子层。图15E是公开出一光阻层71沉积且图案化在黏着/阻障/种子层8011的种子层上。光阻层71是以旋转涂布的方式涂布形成，接着利用一对准机或一倍(1X)步进曝光机进行曝光，并再进行显影后，在光阻层71中形成光阻层开口710。光阻层开口710是用来定义后续加工中与聚合物层开口950与保护层开口50接触的金属线路或平面的形成，而且此接触是在暴露出的金属接垫600上，并连接此暴露出的金属接垫600。图15F中，以电镀的方式形成一厚金属层8012在光阻层开口710所暴露出的种子层上。此厚金属层8012可以是厚度介于1.5微米至50微米之间的一金层，或者是厚度介于2微米至200微米之间的一铜层。一防护/阻障层(cap/barrier layer，图中未示)可利用电镀或无电电镀的方式选择性形成在厚金属层8012上。一组装/接触层(assembly/contact layer，图中未示)也可利用电镀或无电电镀的方式进一步地选择性形成在厚金属层8012以及防护/阻障层上。此组装/接触层可以是厚度介于0.01微米至5微米之间的一金层、一钯层或一钌层。接着，如图15G所示，去除光阻层71。继续，在图15H中，利用自我对准(self-aligned)湿蚀刻或干蚀刻的方式，去除未被厚金属层8012覆盖的黏着/阻障/种子层8011。当利用湿蚀刻方式进行去除时，在图案化金属层801侧壁的底部会形成凹陷部(under cut)8011’，其中此凹陷部8011’是位于厚金属层8012下方，而当使用异向性干蚀刻(anisotropies dry etch)时，则不会有上述的凹陷部8011’的产生。Please also refer to FIG. 15D to FIG. 15H , which disclose an embossing process for forming the patterned metal layer 801 . In FIG. 15D, an adhesion/barrier/seed layer 8011 is deposited on the polymer layer 95, in the polymer layer opening 950 and in the protective layer opening 50, wherein the adhesion/barrier/seed is formed by sputtering. Layer 8011 is preferred. When the material for forming the thick metal layer is gold, the adhesion/barrier/seed layer 8011 is first formed by sputtering to a thickness of 3,000 angstroms.

An adhesion/barrier layer of titanium-tungsten alloy or titanium, followed by sputtering to form a gold seed layer with a thickness of 1,000 angstroms. When the material for forming the thick metal layer is copper, the formation of the adhesion/barrier/seed layer 8011 is to form a chromium metal adhesion/barrier layer with a thickness of 500 angstroms and a titanium metal with a thickness of 1,000 angstroms by sputtering. The adhesion/barrier layer or a titanium-tungsten alloy adhesion/barrier layer with a thickness of 3,000 angstroms is formed, followed by a copper seed layer with a thickness of 5,000 angstroms by sputtering. FIG. 15E discloses that a photoresist layer 71 is deposited and patterned on the seed layer of the adhesion/barrier/seed layer 8011 . The photoresist layer 71 is coated and formed by spin coating, and then exposed by an alignment machine or a double (1X) stepper exposure machine, and then developed to form a photoresist layer in the photoresist layer 71 Opening 710 . The photoresist layer opening 710 is used to define the formation of metal lines or planes in contact with the polymer layer opening 950 and the protective layer opening 50 in subsequent processing, and this contact is on the exposed metal pad 600, and connects the exposed metal pad 600. out of the metal pad 600 . In FIG. 15F , a thick metal layer 8012 is formed on the seed layer exposed by the photoresist layer opening 710 by electroplating. The thick metal layer 8012 can be a gold layer with a thickness between 1.5 microns and 50 microns, or a copper layer with a thickness between 2 microns and 200 microns. A cap/barrier layer (not shown in the figure) can be selectively formed on the thick metal layer 8012 by means of electroplating or electroless plating. An assembly/contact layer (not shown in the figure) can also be selectively formed on the thick metal layer 8012 and the protection/barrier layer by means of electroplating or electroless plating. The assembly/contact layer can be a gold layer, a palladium layer or a ruthenium layer with a thickness between 0.01 microns and 5 microns. Next, as shown in FIG. 15G, the photoresist layer 71 is removed. Continuing, in FIG. 15H , the adhesion/barrier/seed layer 8011 not covered by the thick metal layer 8012 is removed by self-aligned wet etching or dry etching. When wet etching is used for removal, an under cut 8011' will be formed at the bottom of the sidewall of the patterned metal layer 801, wherein the under cut 8011' is located under the thick metal layer 8012, and when anisotropic During dry etching (anisotropies dry etch), the above-mentioned concave portion 8011 ′ will not be generated.

Please refer to FIG. 15I and FIG. 15J at the same time, which disclose the steps of forming a polymer layer 98 and a patterned metal layer 802 through the processing described in FIG. 15C to FIG. 15H . In addition, the processing shown in FIG. 15I and FIG. 15J can be repeatedly used to form the third metal layer, the fourth metal layer or more metal layers. If the structure 8 above the protective layer only includes two metal layers (patterned metal layer 801 and patterned metal layer 802), a cap polymer layer (cap polymer layer) 99 is deposited on the patterned metal layer 802 (now the topmost) and On the polymer layer 98 not covered by the patterned metal layer 802, as shown in FIG. 15K. Polymer layer openings 990 are formed in the top polymer layer 99 and expose contact pads 8000 for connecting external circuits. In some applications, such as when the thick metal layer 8012 is gold, the top polymer layer 99 may be optionally omitted. FIG. 15K discloses a wafer having both fine line structures 6 and overpass structures 8 , which expose contact pads 8000 through polymer layer openings 990 in the top polymer layer 99 .

The wafer is sawed (cut) into a plurality of individual chips, and the contact pad 8000 of this individual chip can be connected to an external circuit in the following manner, which is: (1) a wire bonding wire (gold wire) processed by wire bonding , aluminum wire or copper wire); (2) bumps on other substrates (gold bumps, copper bumps, solder bumps or other metal bumps), which can be silicon chips, silicon substrates, ceramic substrates, organic Substrate, ball grid array (BGA) substrate, flexible substrate, flexible tape (flexible tape) or glass substrate, and the bump height on the substrate is between 1 micron and 30 microns between, and preferably between 5 microns and 20 microns; (3) pillars (gold pillars, copper pillars, solder pillars or other metal pillars) on other substrates, which can be silicon chips, Silicon substrate, ceramic substrate, organic substrate, ball grid array (BGA) substrate, flexible (flexible) substrate, flexible tape (flexible tape) or glass substrate, and the height of the post on this substrate is between 10 microns and 200 microns, preferably between 30 microns and 120 microns; (4) a metal wire of a lead frame or a flexible tape bumps (gold bumps, copper bumps, solder bumps or other metal bumps), the height of the bumps on the substrate is between 1 micron and 30 microns, and the height of the bumps is between 5 microns and 20 microns Micron is preferred.

In some applications, the contact structures 89 formed on the contact pads 8000 can be used to connect external circuits, as shown in FIG. 15L. An under bump metallurgy (UBM) 891 is formed under the contact structure 89 to serve as an adhesion and diffusion barrier. The contact structure 89 can be: (1) solder pads formed by electroplating or screen printing (the thickness is between 0.1 micron and 30 microns, and preferably between 1 micron and 10 microns) , or solder bumps (with a height between 10 microns and 200 microns, preferably between 30 microns and 120 microns). Then, a solder reflow process is used to form a spherical solder ball (ball-shaped solder ball). Solder pads or solder bumps can be: 1. High lead solder, such as tin-lead alloy (PbSn) containing more than 85% lead by weight; 2. Eutectic solder (eutectic) , such as a tin-lead alloy containing about 37% by weight of lead and about 63% by weight of solder; 3. lead-free solder, such as tin-silver alloy (SnAg) or tin-copper-silver alloy ( SnCuAg). In addition, the UBM layer 891 may be the following composite layers (arranged from bottom to top), including: titanium/nickel, titanium/copper/nickel, titanium-tungsten alloy/nickel, titanium-tungsten alloy/copper/nickel , titanium/nickel/gold, titanium/copper/nickel/gold, titanium-tungsten alloy/nickel/gold, titanium-tungsten alloy/copper/nickel/gold, titanium/copper/nickel/palladium, titanium-tungsten alloy/copper/nickel/palladium , chrome/chrome-copper alloy, nickel-vanadium alloy/copper, nickel/copper, nickel-vanadium alloy/gold, nickel/gold or nickel/palladium; microns, preferably between 1 micron and 5 microns), or gold bumps (height between 5 microns and 40 microns, preferably between 10 microns and 20 microns) whichever is better). In addition, the UBM layer 891 can be: titanium, titanium-tungsten alloy, tantalum, tantalum nitride, titanium/copper/nickel composite layer (arranged from bottom to top) or titanium-tungsten alloy/copper/nickel composite layer (Arrangement from bottom to top); (3) Metal balls formed by ball mounting. The metal ball can be a solder ball, a copper ball coated with a nickel layer, a copper ball coated with a nickel layer and a solder layer, or a nickel layer and a gold layer coated on the surface of a copper ball. In addition, the diameter of the metal ball is between 10 microns and 500 microns, preferably between 50 microns and 300 microns. In addition, the metal balls can be directly soldered on the surface of the contact pad 8000 exposed by the polymer layer opening 990 or on the UBM layer 891, and the UBM layer 891 formed to solder the metal balls can be The following composite layers (arranged from bottom to top) include: titanium/nickel, titanium/copper/nickel, titanium-tungsten alloy/nickel, titanium-tungsten alloy/copper/nickel, titanium/nickel/gold, titanium /copper/nickel/gold, titanium-tungsten alloy/nickel/gold, titanium-tungsten alloy/copper/nickel/gold, titanium/copper/nickel/palladium, titanium-tungsten alloy/copper/nickel/palladium, chromium/chrome-copper alloy, nickel Vanadium alloy/copper, nickel/copper, nickel vanadium alloy/gold, nickel/gold or nickel/palladium. In addition, after the metal balls are attached, usually the sleeve needs to undergo a solder reflow process.

After forming the contact structure 89, the chip on the wafer is divided by sawing or dicing to be packaged or assembled to be connected to an external circuit, wherein the method of assembly can be wire bonding (connected to an external organic, ceramic, glass or pads on a silicon substrate, or wires connected to a lead frame or a flexible tape), tape automated bonding (TAB), tape-chip-carrier (TCP) packaging, Chip on glass (COG), chip on chip (COB), flip chip on BGA substrate (flip chip on BGA substrate), chip on film (COF), chip on flex (chip on flex), stacked multi Chip-on-chip stack interconnection, chip-on-Si-substrate stack interconnection, etc.

In the embossing process shown in Figures 15C to 15K, it is disclosed that the steps of forming a patterned metal layer are: forming an adhesion/barrier/seed layer once, followed by forming a photoresist layer and electroplating the patterned metal layer. The metal layer is also only once, and the photoresist layer is removed at the end, and the adhesion/barrier/seed layer not covered by the patterned metal layer is removed. This type of processing is called a single-emboss process, that is, the process includes only one photolithographic process before removing the adhesion/barrier/seed layer not covered by the patterned metal layer And one-time electroplating processing.

A double-embossing process can form a patterned metal layer and a metal plug (via plug) through the same adhesion/barrier/seed layer, while removing the adhesion/resistor not covered by the patterned metal layer In front of the barrier/seed layer, two photolithography processes and electroplating processes are completed. The first photolithography process and electroplating process are used to form a patterned metal layer, while the second photolithography process and electroplating process are used to form a patterned metal layer. It is used to form metal plugs.

Please also refer to FIG. 16A to FIG. 16D , which disclose the double embossing process for forming the structure 8 above the protective layer on the wafer 10 as shown in FIG. 15A or FIG. 15B . The double embossing process has the same manufacturing steps as the single process shown in Figs. 15C to 15G. In FIG. 15G , the photoresist is removed, leaving the adhesion/barrier/seed layer 8011 not under the thick metal layer 8012 . So far the steps of the double embossing process are different from the single embossing process. Please also refer to FIG. 16A to FIG. , and using a single embossing process to form the topmost metal layer 802 forms an example of the patterned metal layer structure above the passivation layer in all embodiments of the present invention. A patterned metal layer 801 is formed by the first photolithography process and electroplating process, as shown in FIGS. 15D to 15G . Next, please refer to FIG. 16A and FIG. 16B at the same time, on the seed layer of the adhesion/barrier/seed layer 8011 and the thick metal layer 8012 formed by electroplating, a photoresist layer 72 is deposited, and the photoresist layer 72 Perform patterning to make the photoresist layer 72: (1) form a photoresist layer opening 720 on the thick metal layer 8012, and use the photoresist layer opening 720 to expose the thick metal layer 8012; and/or (2) in the adhesion/ A photoresist layer opening 720 ′ is formed on the seed layer of the barrier/seed layer 8011 , and the seed layer of the adhesion/barrier/seed layer 8011 is exposed through the photoresist layer opening 720 ′. Continuing, before the photoresist layer 72 is removed, a second electroplating process is performed to form a metal plug 898 in the photoresist layer opening 720 . In addition, a metal layer 898' whose level is lower than the metal plug 898 can also be formed on the seed layer of the adhesion/barrier/seed layer 8011, and the metal layer 898' can be used for packaging purposes. This metal layer 898' can be thinner than the thick metal layer 8012, also can be thicker than the thick metal layer 8012, when the thickness of the metal layer 898' is less than the thickness of the thick metal layer 8012, such as less than 5 microns (in a preferred situation is between 1 micron to 3 microns), the metal layer 898' can be used to make a connection line (interconnection) with a higher winding density than the thick metal layer 8012, but when the thickness of the metal layer 898' is greater than that of the thick metal layer 8012 With a thickness, eg, greater than 5 microns (and preferably between 5 microns and 10 microns), the metal layer 898 ′ can be used to make connection lines with lower resistance than the thick metal layer 8012 . Next, as shown in FIG. 16C, the photoresist layer 72 is removed to expose the thick metal layer 8012, the metal plug 898, the metal layer 898' and the adhesion/barrier/ Seed 8011. Referring to FIG. 16D , the adhesion/barrier/seed layer 8011 not under the thick metal layer 8012 and the metal layer 898' is removed by wet etch and/or dry etch. Thus, patterned metal layer 801, metal plug 898 and metal layer 898' are formed at this stage shown in FIG. 16D. Referring to FIG. 16E , a polymer layer 98 is formed on the metal plug 898 , the metal layer 898 ′, the patterned metal layer 801 and the exposed first polymer layer 95 . Referring to FIG. 16F , the surface of the polymer layer 98 is planarized by grinding, mechanical grinding or chemical mechanical grinding until the metal plug 898 is exposed. Next, please refer to FIG. 16G to FIG. 16K , which disclose the manufacturing steps of forming a patterned metal layer 802 using the same single embossing process as described in FIG. 15C to FIG. 15K . Continuing, as shown in FIG. 16L , finally a top polymer layer 99 is deposited and patterned to complete an overpass structure 8 with two patterned metal layers 801 , 802 . In addition, during assembly and/or packaging, as shown in FIG. 15L , a contact structure 89 may be formed on the contact pad 8000 exposed by the polymer layer opening 990 . 15D to 15G and 16A to 16D for forming the patterned metal layer 801 and the metal plug 898 of the double embossing manufacturing steps can also be used repeatedly to form the second patterned metal layer ( The topmost metal layer) and a second metal plug (not shown in the figure), and the second metal plug can be used as a contact structure connected to an external circuit. Finally, the descriptions and illustrations related to Figures 16A to 16L are applicable to all embodiments of the present invention.

Please refer to FIG. 17A to FIG. 17J , which disclose the processing steps of forming a patterned metal layer 801, a patterned metal layer 802, and a patterned metal layer 803 on a protective layer structure 8, wherein the patterned metal layer 801 and the pattern The metallization layer 802 is formed using a double embossing process, while the patterned metal layer 803 is formed using a single embossing process. First, as described in FIGS. 15D to 15G and FIGS. 16A to 16D , the patterned metal layer 801 and the metal plug 898 are formed by the first double embossing process. Next, in the processing steps shown in FIGS. 16E to 16F , after forming a polymer layer 98 , planarize the polymer layer 98 until the metal plug 898 is exposed. Please continue referring to FIG. 17A , the processing steps before forming the patterned metal layer 802 are the same as the processing steps of forming the patterned metal layer 801 , the metal plug 898 and the polymer layer 98 by double embossing processing in FIG. 16F . However, in order to accommodate an additional metal layer, the design of the patterned metal layer 801 and metal plug 898 of FIG. 17A is slightly different from the design of the patterned metal layer 801 and metal plug 898 of FIG. 16F . Next, please refer to FIG. 17A to FIG. 17G at the same time, repeat the processing steps described in FIG. 15D to FIG. 15G and FIG. 16A to FIG. 16D to form a patterned metal layer 802, a metal plug 897 and a polymer layer 97, And exposed the metal plug 897. In FIG. 17A, it is formed by: (1) depositing an adhesion/barrier/seed layer 8021; (2) depositing and patterning a photoresist layer; (3) plating openings in the photoresist layer a thick metal layer 8022; and (4) removing the photoresist layer to form the structure shown in FIG. 17A. Next, as shown in FIG. 17B, a photoresist layer 74 is deposited and patterned to form a photoresist layer opening 740 on the thick metal layer 8022, or directly form a photoresist layer opening 740' in the adhesion/barrier/seed layer 8021 on the seed layer. Please refer to FIG. 17C, metal plug 897 and metal layer 897' are formed in photoresist layer opening 740 and photoresist layer opening 740' by electroplating, and this metal layer 897' can be used as the same metal layer 898' the use of. Please also refer to FIG. 17D to FIG. 17E , the photoresist layer 74 is removed, and the adhesion/barrier/seed layer 8021 not under the thick metal layer 8022 and the metal layer 897' is removed. Please also refer to FIG. 17F to FIG. 17G , then deposit a polymer layer 97 and planarize the polymer layer 97 until the metal plug 897 is exposed. Next, please refer to FIG. 17H to FIG. 17I at the same time, which disclose the steps of forming a patterned metal layer 803 using a single embossing process, described as follows: (1) deposit adhesion/barrier/seed layer 8031 ; (2) depositing and patterning a photoresist layer; (3) forming a thick metal layer 8032 by electroplating; Adhesion/barrier/seed layer 8031 under thick metal layer 8032. Finally, please refer to FIG. 17J , which discloses a polymer layer opening 990 formed by depositing a top polymer layer 99 and patterning the top polymer layer 99 to expose a connection to an external circuit as an interconnection. A complete structure of the contact pad 8000.

Please refer to FIG. 18A to FIG. 18I , which disclose another processing step for forming a patterned metal layer 801, a patterned metal layer 802, and a patterned metal layer 803 on a structure above a protective layer, wherein the patterned metal layer 801 The patterned metal layer 803 is formed using a single embossing process, while the second metal layer is formed using a double embossing process. First, please refer to FIG. 18A , which uses a single embossing process as described in FIGS. 15D to 15H to form a patterned metal layer 801 . Next, a polymer layer 98 is deposited and patterned by the processing steps described in FIG. 15I , and the polymer layer 98 is patterned to form a polymer layer opening 980 exposing the patterned metal layer 801 . However, in order to accommodate an additional metal layer, the design of the patterned metal layer 801 and polymer layer opening 980 of FIG. 18A is slightly different from the design of the patterned metal layer 801 and polymer layer opening 980 of FIG. 15I. . Next, please refer to FIGS. 18B to 18G, which disclose the processing steps of using a double embossing process to form a patterned metal layer 802 and a metal plug 897, and are described as follows: (1) Please refer to FIG. 18B (2) Referring to FIG. 18C, a photoresist layer 72 is deposited, and the photoresist layer 72 is patterned to form a photoresist layer opening 720, and then Electroplating a thick metal layer 8022 in the photoresist opening 720 of the photoresist layer 72; and (3) removing the photoresist layer 72 to form the structure shown in FIG. 18D . Next, as shown in FIG. 18E, a photoresist layer 73 is formed by deposition, and the photoresist layer 73 is patterned to form a photoresist layer opening 730 on the thick metal layer 8022, and/or form a photoresist layer opening 730' On the seed layer of the adhesion/barrier/seed layer 8021. Continue to use electroplating to form a metal plug 897 and a metal piece 897' in the photoresist layer openings 730, 730', and this metal piece 897' can be used as the metal layer 898 as shown in FIG. 16D ' for the same purpose. Referring to FIG. 18F to FIG. 18G , the photoresist layer 73 is removed, and the adhesion/barrier/seed layer 8021 not under the thick metal layer 8022 and the metal layer 897' is removed. Referring to FIG. 18H , a polymer layer 97 is then deposited, and the polymer layer 97 is planarized until the metal plug 897 is exposed. Finally, please refer to FIG. 18I, which discloses a patterned metal layer 803 formed by the single embossing process described in FIGS. 17H to 17I, and by depositing a top polymer layer 99 and patterning the top polymer Layer 99 forms a polymeric opening 990 exposing a complete structure of a contact pad 8000 as an interconnection to external circuitry.

Please also refer to FIG. 19A to FIG. 19G , which disclose the processing of forming a structure 8 above a protective layer on the wafer 10 as shown in FIG. 15A or FIG. 15B , wherein the patterned metal layer 801 uses a double relief processing, while the patterned metal layer 802 is formed using a single embossing process. First, in FIG. 19A, a patterned metal layer 801, a metal plug 898, a metal layer 898' and a polymer layer 98 are formed using the double embossing process steps described in FIGS. 15D-15G and 16A-16F. Next, please refer to FIG. 19A to FIG. 19G at the same time, which utilizes the same single embossing process step as described in FIG. 15C to FIG. 15K to form a patterned metal layer 802, a polymer layer 97, and a top top The polymer layer 99 and a polymer layer opening 990 expose the contact pads 8000 , which will not be described in detail here.

Finally, as shown in FIG. 19H , the wafer is sawed (cut) into a plurality of individual chips, and connected to external circuits through the contact pads 8000 on the individual chips, for example, using a wire bonding wire 89'( Such as gold wire, aluminum wire or copper wire) to connect external circuits.

The above descriptions are only preferred embodiments of the present invention, and are only illustrative rather than restrictive to the present invention. Those skilled in the art understand that many changes, modifications, and even equivalents can be made within the spirit and scope defined by the claims of the present invention, but all will fall within the protection scope of the present invention.

Claims (14)

1. A line assembly, characterized in that: it comprises: an internal circuit; A chip connected to an external circuit, including an output node; A silicon substrate, carrying the internal circuit and the external circuit connected to the chip; a first metal line, connected to an output node of the internal circuit; A second metal line, connected to an input node of the chip connected to an external circuit, and the thickness of the second metal line is between 0.2 micron and 1 micron; A third metal line, connecting the chip to the output node of the external circuit; a protection layer, located above the silicon substrate, the internal circuit, the chip external circuit, the first metal circuit, the second metal circuit and the third metal circuit, And the protective layer has a first opening, a second opening and a third opening; A first polymer layer is located on the protective layer and contacts the protective layer, and the first polymer layer has a first opening of the first polymer layer, a second opening of the first polymer layer The opening and a third opening of the first polymer layer, the first opening of the first polymer layer is aligned with the first opening, and the second opening of the first polymer layer is aligned with the second opening, the third opening of the first polymer layer is aligned with the third opening, the size of the bottom of the second opening of the first polymer layer is smaller than the size of the second opening, and the the size of the bottom of the third opening of the first polymer layer is smaller than the size of said third opening; A fourth metal circuit, located on the first polymer layer and contacting the first polymer layer, and the fourth metal circuit is connected to the first polymer layer through the first opening of the first polymer layer The first metal line is connected to the second metal line through the second opening of the first polymer layer, and the thickness of the fourth metal line is between 3 microns and 20 microns; a fifth metal circuit, located on the first polymer layer and contacting the first polymer layer, and the thickness of the fifth metal circuit is between 3 microns and 20 microns; a metal line or plane, located on the first polymer layer and contacting the first polymer layer, and the metal line or plane is connected to the first polymer layer through the third opening of the first polymer layer the third metal circuit; A second polymer layer located on the fourth metal circuit, the fifth metal circuit, the metal circuit or plane and the first polymer layer, and the second polymer the layer has a second polymer layer first opening and a second polymer layer second opening; and A sixth metal line, located on the second polymer layer and contacting the second polymer layer, and the sixth metal line is connected to the second polymer layer through the first opening of the second polymer layer The fourth metal line is connected to the fifth metal line through the second opening of the second polymer layer, and the thickness of the sixth metal line is between 3 microns and 20 microns. 2. The circuit assembly according to claim 1, wherein the circuit assembly is a chip. 3. The circuit assembly according to claim 1, characterized in that: the fourth metal circuit is a composite layer composed of an adhesion/barrier/seed layer at the bottom layer and a metal layer at the top layer, and the metal layer The material of the layer is gold, copper, silver, nickel, palladium, rhodium, platinum or ruthenium. 4. The circuit assembly according to claim 1, wherein the sixth metal circuit is a composite layer composed of an adhesion/barrier/seed layer at the bottom layer and a metal layer at the top layer, and the metal layer The material of the layer is gold, copper, silver, nickel, palladium, rhodium, platinum or ruthenium. 5 . The circuit assembly according to claim 1 , wherein the off-chip circuit includes at least one off-chip driver, and the off-chip driver is composed of at least one metal oxide semiconductor device. 5 . 6 . The circuit assembly according to claim 1 , wherein the off-chip circuit includes at least one of an off-chip tri-state buffer and an electrostatic discharge protection circuit or a combination thereof. 7 . 7 . The circuit assembly according to claim 1 , wherein the chip-connected external circuit includes at least one electrostatic discharge protection circuit. 8 . 8. The circuit assembly according to claim 1, wherein the width of the sixth metal circuit is between 1 micron and 200 microns. 9. The circuit assembly according to claim 1, further comprising a metal layer located above the metal circuit or plane, and the metal layer contacts the metal circuit or plane, and the The thickness of the metal layer is between 3 microns and 20 microns. 10 . The circuit assembly according to claim 1 , wherein the protective layer is made of a silicon nitride compound and a silicon oxide compound or a combination thereof. 11 . the 11. The circuit assembly according to claim 1, further comprising a metal layer located above the metal line or plane and a contact structure located on the metal layer, the metal layer contacts The metal line or plane, and the contact structure is a solder bump. 12. The circuit assembly according to claim 1, further comprising a metal layer located above the metal line or plane and a contact structure located on the metal layer, the metal layer contacts The metal line or plane, and the contact structure is a gold pad. 13. The circuit assembly according to claim 1, wherein the second metal circuit is a copper layer. 14. The circuit assembly according to claim 1, wherein the fifth metal circuit is a composite layer composed of a bottom layer of adhesion/barrier/seed layer and a top layer of metal layer. the

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