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CN101208794B - Si:C-OI和SGOI上的硅器件及其制造方法 - Google Patents

Si:C-OI和SGOI上的硅器件及其制造方法 Download PDF

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CN101208794B
CN101208794B CN200480034036.6A CN200480034036A CN101208794B CN 101208794 B CN101208794 B CN 101208794B CN 200480034036 A CN200480034036 A CN 200480034036A CN 101208794 B CN101208794 B CN 101208794B
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杜里赛迪·齐达姆巴劳
奥莫·H.·多库玛斯
奥赖格·G.·格鲁斯臣科夫
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Abstract

提供了一种半导体结构和制造方法。此制造方法包括在衬底中形成浅沟槽隔离(STI)(25)以及在衬底上提供第一材料(30)和第二材料(40)。用热退火工艺，将第一材料(30)和第二材料(40)混合到衬底中，以便分别在nFET区和pFET区处形成第一岛(50)和第二岛(55)。不同的材料层被形成在第一岛(50)和第二岛(55)上。STI弛豫并有利于第一岛(50)和第二岛(55)的弛豫。第一材料(30)可以是淀积的或生长的Ge材料，而第二材料(40)可以是淀积的或生长的Si:C或C。应变Si层被形成在第一岛(50)和第二岛(55)至少之一上。

Description

Si:C-OI和SGOI上的硅器件及其制造方法
技术领域
本发明一般涉及到半导体器件及其制造方法，更确切地说是涉及到半导体器件及其在器件制作过程中将张应力和压应力施加在器件中的制造方法。
背景技术
半导体器件衬底内的机械应力能够调制器件性能。亦即，已知半导体器件内的应力可增强半导体器件的特性。于是，为了改善半导体器件的特性而在n型器件(例如nFET)和/或p型器件(例如pFET)的沟道中产生张应力和/或压应力。但相同的应力分量，张应力或压应力，对n型器件和p型器件的影响是有差别的。
为了尽可能提高集成电路(IC)芯片内的nFET和pFET二者的性能，对于nFET和pFET应该不同地施加应力分量。亦即，因为对nFET性能有利的应力类型通常对于pFET的性能不利。更确切地说，当器件处于伸张时(例如沿平面器件中电流流动的方向)，nFET的性能特性被增强，而pFET的性能特性被削弱。为了选择性地在nFET中产生张应力而在pFET中产生压应力，采用了不同的工艺和不同的材料组合。
例如，已经提出了一种沟槽隔离结构来分别在nFET和pFET中形成适当的应力。当采用此方法时，nFET的隔离区包含第一隔离材料，将第一类型的机械应力沿纵向(例如平行于电流电流的方向)和沿横向(例如垂直于电流流动方向)施加在nFET上。而且，为pFET提供了第一隔离区和第二隔离区，且pFET的各个隔离区将特有的机械应力沿横向和纵向施加在pFET上。
作为变通，已经提出了栅侧壁上的衬里来在FET器件沟道中选择性地诱发适当的应力(见例如Ootsuka et al.，IEDM 2000，p.575)。与由于沟槽隔离填充技术而施加的应力相比，借助于提供衬里，适当的应力被施加得更靠近器件。
而且，已经提出了许多建议分别用张应力和压应力来改善nFET和pFET二者的器件性能，这些建议包括用掩模分别对二种MOSFET调制隔板本征应力和改变STI(浅沟槽隔离)材料。弛豫SiGe上的张应变Si也已经被提出作为施加这种应力的一种方法。不幸的是，弛豫SiGe上的张应变Si仅仅能够将双轴张应力施加在用于叠层形式中的Si帽层上。由于pFET对应力的灵敏度，这就限制了可使用的Ge百分比范围。NFET的性能随双轴伸张而单调地改善；但pFET随双轴伸张而退化，直至大约3GPa才开始改善。
为了同时改善pFET和nFET，Ge百分比必须高，大约要高于25-30％(或等效于应力大约高于3-4GPa)。这种水平的Ge百分比难以在工艺中实现，且不太可能制造，其主要问题包括表面粗糙度、工艺复杂性、缺陷、以及成品率控制等等。已知高的Ge百分比难以用于pFET(由于可能因为伸张程度比较低而不利)，故必须提出其它的方法来改善器件的性能。
此外，已知Si:C外延生长在Si上而固有地伸张。Si:C/Si材料叠层中1％的C含量能够在Si:C中引起约为500Mpa的张应力水平。相比之下，为了引起500Mpa的压力，在SiGe/Si系统中需要大约6％。如论文Ernst et al.，VLSI Symp.，2002，p.92中所示，此1％水平的C能够在外延生长过程中被组合到硅中。在Ernst的论文中，Si/Si:C/Si位于nFET的层状沟道中。但结构的Si:C部分不被弛豫。而是在Ernst的论文中，未被弛豫的Si:C被用作具有非常薄的Si帽层的沟道本身部分。此方法的问题在于，依赖于C含量，迁移率由于散射而不被提高反而被降低。
虽然这些方法确实提供了具有施加到nFET器件的张应力和沿pFET纵向施加的压应力的结构，但可能要求额外的材料和/或更复杂的工艺，从而导致更高的成本。而且，这些情况下所能够施加的应力的水平典型地是中等的(亦即约为一百MPa量级)。于是希望提供成本-效率更好且简化的方法来分别在nFET和pFET沟道中产生大的张应力和压应力。
发明内容
在本发明的第一情况下，制造结构的方法包括在衬底中形成浅沟槽隔离(STI)以及在衬底上提供第一材料和第二材料。用热退火工艺，第一材料和第二材料被混合到衬底中，以便分别在nFET区和pFET区处形成第一岛和第二岛。不同材料层被形成在第一岛和第二岛上。此STI弛豫并便于第一岛和第二岛的弛豫。在一个实施方案中，第一材料是淀积或生长的Ge材料，而第二材料是淀积或生长的Si:C或C。
在另一情况下，制造结构的方法包括用第一材料形成衬底和衬底中的浅沟槽隔离。在pFET区和nFET区上形成第二材料，然后被热退火到衬底中，以便形成混合材料的第一岛和第二岛。Si层被生长在第一区中的第一岛上。此Si层被应变。
在另一情况下，制造方法包括形成衬底和衬底中的由高温稳定的非晶材料优选为氧化物组成的浅沟槽隔离。此方法还包括将至少一种材料热退火到衬底中，以便形成混合材料的第一岛和第二岛，并在至少第一岛上生长Si层。此Si层被应变。在这些实施方案中：
(i)至少一种材料是Ge，且第一岛和第二岛基本上由弛豫SiGe的混合材料组成，
(ii)至少一种材料是C或Si:C，且第一岛和第二岛基本上由弛豫Si:C的混合材料组成，且
(iii)至少一种材料是Ge和Si:C或C，且第一岛基本上由SiGe组成，而第二岛基本上由Si:C组成。
在本发明的另一情况下，半导体结构包括衬底和形成在衬底中的由高温稳定的非晶材料优选为氧化物组成的弛豫的浅沟槽隔离。热退火混合材料的第一岛被形成在pFET区处的衬底中，而热退火混合材料的第二岛被形成在nFET区处的衬底中。应变Si层被形成在至少第一岛和第二岛之一上。
附图说明
图1-6表示形成根据本发明的中间结构的制造工艺；
图7-11表示形成根据本发明另一情况的中间结构的制造工艺；而
图12a和12b是本发明的代表性结构。
具体实施方式
本发明的目的是一种在CMOS器件的nFET沟道和pFET沟道中提供所希望的应力来改善器件性能的半导体器件及其制造方法。在一种方法中，通过将淀积的Ge材料热混合到SOI薄膜中而得到了SiGe岛。同样，通过将淀积的Si:C或C热混合到Si或SOI薄膜中而得到了Si:C岛。利用本发明的方法，所要求的Ge百分比不大，因而不引起缺陷问题。而且，利用本发明能够分别得到pFET和nFET沟道中的SiGe和/或Si:C岛的弛豫，从而与满铺(SiGe或Si:C)衬底相比，提供了改进的性能。这是因为在本发明的执行过程中，提供了例如高温热混合步骤，使浅沟槽隔离(STI)能够弛豫并便于SiGe和Si:C岛的弛豫。
在本发明之前，来实现具有不同的弛豫晶格(不同的原子间尺度)的至少二个晶体岛的安置只能用其中各岛具有比较大的尺寸的晶片键合技术；但在本发明中，此方法产生了具有小的晶体岛的独特衬底，这些小的晶体岛具有弛豫的但不同的晶体结构。在一种执行过程中，这种结构的非凡要点是采用岛之间的高温稳定的非晶材料例如二氧化硅和采用绝缘体上晶体结构。这种具有不同(晶体)岛的独特结构使得能够安置可选地不同的晶体的不同应变的层。在第一情况下，不同应变的层是伸张的和压缩的Si层。在本发明的另一情况下，不同的层是伸张的Si层和SiGe层或压缩的Si层和Si:C层。
本发明对于在绝缘体上制作具有多个晶格常数的各岛的衬底，具有创新的重要的贡献。例如，在本发明中，第一岛(晶体1)的晶格常数为a≥aSi，而第二岛(晶体2)的晶格常数为a≤aSi。在本发明的一种情况下，如下面更详细地讨论的那样，本发明的Si外延层能够分别张应变地和压应变地被选择性生长在SiGe和Si:C上。这一特定应用例如可适合于应变的平面nFET和pFET。
此外，应该理解的是，已知空穴在SiGe中具有优异的迁移率，但在这种材料上难以形成可靠的热基氧化物。然而，在本发明的一种执行过程中，淀积了一种高K材料介质，致使有可能让仅仅用于pFET的弛豫的SiGe(晶体1)与一起用于nFET的晶体1(还是弛豫的SiGe)和张应变Si彼此串列。。本发明还试图将Si:C与具有压应力的Si用于pFET。于是，本发明能够归纳出多晶格常数岛衬底的概念。
现在参照图1，示出了一种硅晶片。这种晶片是用于各种分立半导体器件和集成电路(IC)半导体器件应用的市售初始衬底。在一种执行过程中，可以用SIMOX(用注入的氧来分离)工艺来制作玻璃上硅(SOI)，此工艺采用氧的高剂量离子注入和高温退火，以便在本体晶片中形成BOX层。作为另一例子，可以借助于将器件质量的硅晶片键合到其表面上具有氧化物层的另一硅晶片(衬底层)，来制作晶片。然后，利用在衬底层上的氧化物层(现在已经成为BOX)顶部上留下一个薄的(相对于初始晶片的厚度)器件质量的单晶硅层的工艺，来分离此成对的晶片。也可以用其它的工艺来形成SOI晶片。
仍然参照图1，Si层20被形成且图形化，以便周标准的衬垫氧化；衬垫氮化物淀积；基于光刻的图形化；由氮化物、氧化物、以及硅所组成的叠层向下达及埋置氧化物的反应离子刻蚀；边沿氧化；衬里淀积；填充淀积；以及化学机械抛光技术，来形成浅沟槽隔离(STI)25。此STI形成工艺在本技术领域中是众所周知的。在一种执行过程中，高温稳定的非晶材料例如二氧化硅被用于STI。
参照图2，利用诸如化学气相淀积方法之类的常规技术，外延Ge材料(层)30被淀积在结构的表面上。例如，超高真空化学气相淀积(UHVCVD)可以以常规的方式被用来淀积Ge层30。其它的常规技术包括快速热化学气相淀积(RTCVD)、有限反应加工CVD(LRPCVD)、以及分子束外延(MBE)。在一个实施方案中，依赖于例如可以为30-100nm的下方Si层的厚度，Ge材料的厚度可以是5-50nm或其它的尺度。
nFET硬掩模35被提供在部分Ge层30上(例如要形成nFET器件处)。nFET硬掩模35可以是用诸如甩涂、CVD、等离子体辅助CVD、超高真空化学气相淀积(UHVCVD)、快速热化学气相淀积(RTCVD)、有限反应加工CVD(LRPCVD)、以及其它相似淀积工艺之类的常规淀积工艺所形成的氮化物硬掩模。
在图3中，暴露的Ge层30被腐蚀，并用本技术领域所知的技术剥离nFET掩模35。例如，可以用RIE、湿法腐蚀、或干法腐蚀方法来选择性地腐蚀Ge层30。
如图4所示，Si:C材料40(或可选地为C)被淀积在衬底上，包括淀积在外延淀积的Ge材料35上。例如，可以以常规的方式用超高真空化学气相淀积(UHVCVD)来淀积Si:C(或可选地为C)材料40，其它的常规技术包括快速热化学气相淀积(RTCVD)、有限反应加工CVD(LRPCVD)、以及其它类似的工艺。在一个实施方案中，依赖于例如可以为30-100nm的下方Si层的厚度，此Si:C或C材料的厚度可以是5-50nm或其它的尺度。在另一情况下，当采用C时，厚度可以是1-30nm。
pFET硬掩模45被提供在部分Si:C材料40上要形成pFET器件处。pFET硬掩模45可以是用诸如甩涂、CVD、等离子体辅助CVD、超高真空化学气相淀积(UHVCVD)、快速热化学气相淀积(RTCVD)、有限反应加工CVD(LRPCVD)、以及其它相似淀积工艺之类的常规淀积工艺所形成的氮化物硬掩模。
如图5所示，暴露的Si:C层40然后被腐蚀，并用本技术领域所知的技术剥离pFET掩模45。例如，可以用诸如RIE、湿法腐蚀、或干法腐蚀之类的标准腐蚀技术来腐蚀Si:C和pFET。
然后在图6中，此结构经历热退火工艺。在此工艺过程中，对于nFET，淀积的Ge材料30被混合到下方SOI膜中，以便形成基本上是SiGe材料的岛50。同样，在此工艺过程中，对于pFET，淀积的Si:C或可选的C材料被混合到下方SOI膜中，形成基本上是Si:C材料的岛55。例如在大约1200-1350℃下进行1-10小时的热退火工艺，在一种执行过程中是在1200℃进行大约5小时。
利用本发明的方法，对于nFET，所要求的Ge百分比不大(例如小于25％，而在一种执行过程中为10-20％)，因而不引起缺陷问题。而且，由于高温热混合步骤，故例如STI 25能够弛豫，从而便于SiGe岛50和Si:C岛55的弛豫。这部分地是由于STI包含氧化物材料，此氧化物材料在高温下是一种粘滞材料，例如在高温下成为一种低粘滞性材料。
而且，现在应该理解的是，SiGe岛50和Si:C岛55具有不同的弛豫晶格(不同的原子间距)，这就产生了具有小的晶体岛的独特的衬底。与满铺(SiGe或Si:C)衬底相比，SiGe岛50和Si:C岛55的弛豫提供了改进的性能。在一种执行过程中，根据本发明因而采用了SiGe岛50与Si:C岛55之间例如为SiO2的高温稳定的非晶材料以及绝缘体上晶体结构。
如图6进一步所示，用已知的工艺，Si外延层60被选择性生长在SiGe岛50和Si:C岛55上。在本发明的一种情况下，此选择性生长的Si外延层60将在SiGe岛和Si:C岛上分别张应变和压应变。Si层60的厚度可以是例如5-20nm。正如所有的尺度之类那样，例如依赖于下方衬底的厚度而设想了本发明可以采用的其它尺度和温度等。
现在在执行过程中，SiGe岛50的晶格常数为a≥aSi，而Si:C岛55的晶格常数为a≤aSi。亦即，单独存在时，Si的晶格常数通常小于SiGe的晶格常数，亦即，Si材料的晶格常数与SiGe层的晶格常数不匹配。但在本发明的结构中，Si层的晶格结构将倾向于与SiGe岛的晶格结构匹配。于是，由于Si(通常较小)对SiGe层的晶格匹配，Si层就被置于张应力下。此区域将起nFET的应变沟道的作用。在一个实施方案中，SiGe层的Ge含量对Si含量的比率可以小于25％。
而且，单独存在时，Si的晶格常数通常大于Si:C岛的晶格常数。亦即，Si材料的晶格常数与Si:C的晶格常数不匹配。但在本发明的结构中，Si层的晶格结构将倾向于与Si:C的晶格结构匹配。由于Si(通常较大)对Si:C岛的晶格拟合，Si层就被置于压应力下。亦即，相似于SiGe的情况，Si:C岛的周围区域将试图达到平衡状态，从而导致形成在Si:C岛上的外延Si层的压应力。此区域将起pFET的应变沟道的作用。在一个实施方案中，淀积的C含量对Si含量的比率可以直至大约4％。
图7-11示出了本发明的另一情况。在图7中，示出了诸如SOI的硅晶片。如在先前所述的结构中那样，可以用SIMOX工艺或其它熟知的工艺来制作此SOI。Si层20被图形化，以便用标准的衬垫氧化；衬垫氮化物淀积；基于光刻的图形化；由氮化物、氧化物、以及硅所组成的叠层向下达及埋置氧化物的反应离子刻蚀(RIE)；边沿氧化；衬里淀积；填充淀积；以及化学机械抛光技术，来形成浅沟槽隔离(STI)25。此STI形成工艺在本技术领域中是众所周知的。
参照图8，pFET掩模40被提供在部分结构上要形成pFET器件处。此pFET硬掩模可以用诸如化学气相淀积方法之类的常规技术来淀积。例如，这些技术可以包括甩涂、CVD、等离子体辅助CVD、蒸发、超高真空化学气相淀积(UHVCVD)、快速热化学气相淀积(RTCVD)、有限反应加工CVD(LRPCVD)、以及其它相似淀积工艺。
利用常规技术，外延Ge层30被选择性地生长在要形成nFET的暴露表面上。在一个实施方案中，依赖于例如可以为30-100nm的下方Si层的厚度，Ge材料的厚度可以是5-50nm或其它的尺度。如前面所述，用众所周知的工艺来剥离硬掩模45。
在图9中，nFET掩模35被提供在部分结构上要形成nFET器件处。如通篇所讨论的和一般熟练人员应该知道的那样，此nFET硬掩模可以用诸如化学气相淀积方法之类的常规技术来淀积。
如上面所讨论的那样，用诸如化学气相淀积方法之类的常规技术，Si:C层40被选择性地生长在结构要形成pFET的暴露表面上。在一个实施方案中，依赖于例如可以为30-100nm的下方Si层的厚度，此Si:C材料的厚度可以是5-50nm或其它的尺度。此C甚至可以更薄为1-50nm。
如图10所示，然后用众所周知的工艺来清除nFET硬掩模35。此结构然后经历热退火工艺。在此退火工艺过程中，对于nFET，Ge材料30被混合到SOI膜中，形成基本上是SiGe材料的岛50。同样，对于pFET，Si:C或可选的C材料被混合到SOI膜中，形成基本上是Si:C材料的岛55。此工艺还形成了一个BOX层作为衬底。例如在大约1200-1350℃下进行1-10小时的热退火工艺，在一种执行过程中是在1200℃进行大约5小时。
如上所述，相似于先前各执行过程，利用本发明的方法，所要求的Ge百分比不大(例如小于25％，而在一种执行过程中为10-20％)，因而不引起缺陷问题。而且，由于高温热混合步骤，故例如STI 25能够弛豫，从而便于SiGe岛50和Si:C岛55的弛豫。如先前所述，与满铺(SiGe或Si:C)衬底相比，SiGe和Si:C的弛豫提供了改进的性能。在本发明的一种执行过程中，这种结构的要点是岛之间例如为SiO2的高温稳定的非晶材料以及绝缘体上晶体结构。
如图11进一步所示，Si外延层60被选择性地生长在SiGe岛50和Si:C岛55上。Si层60的厚度可以是例如5-20nm。在本发明的这一情况下，不同的层成为伸张的Si层或压缩的Si层。伸张的Si层将用作nFET的应变沟道，而压缩的Si层将用作pFET的应变沟道。
在本发明的另一情况下，可以在高剂量下将C注入到pFET区中，在热退火时，这能够在Si:C中产生大大高于1-4％的浓度。此剂量可以约为每平方厘米1×1016或以上，例如每平方厘米5×1016。
在图12a的所示例子中，在一种执行过程中，排除了Si:C或C，SiGe可以被用于nFET和pFET二者。在此执行过程中，应变Si将位于nFET区上而不在pFET区上。在制作时，nFET则将处于张应力中。但为了开始器件的制作工艺，高K介质100被选择性地生长在结构上；亦即，高K介质100可以被生长在应变Si层和暴露的SiGe层上。此高K介质100可以是例如氧化锆或氧化铝。
作为变通，排除了SiGe，Si:C可以被用于nFET和pFET二者。在此执行过程中，应变Si将位于pFET区上而不在nFET区上。在制作时，pFET则将处于压应力中。但为了开始器件的制作，高K介质100被选择性地生长在结构上；亦即，高K介质100可以被生长在应变Si层和暴露的Si:C层上。此高K介质100可以是例如氧化锆或氧化铝。图12b也表示了这一点。如上所述，采用Si:C和SiGe的工艺仍然相同。
如图6、图11、图12a和12b所示，所形成的结构是一些根据本发明的原理适应诸如pFET和nFET的半导体器件的制作的中间结构。如本技术众所周知的那样，为了形成最终的器件，可以执行标准的CMOS工艺，以便在结构上形成诸如场效应晶体管之类的器件。例如，这些器件可以包括被应变Si(或Si和SiGe以及Si和Si:C)的半导电沟道分隔开的源区和漏区的离子注入。亦即，nFET将被形成在张应变的Si沟道上，而pFET将被形成在压应变的Si沟道上。栅氧化物被提供在应变Si沟道的顶部，而栅导体被提供在栅氧化物的顶部上。还提供了隔板。这些组成部分在典型的场效应晶体管中都有，为了容易理解FET器件的制作工艺，对于本技术领域的一般熟练人员无须进一步解释。
虽然就实施方案而言已经描述了本发明，但本技术领域的熟练人员可以理解的是，可以在所附权利要求的构思与范围内加以修正来实施本发明。例如，本发明能够被容易地应用于体衬底。
工业应用可能性
本发明可用于半导体器件领域，更确切地说，可应用于在制作过程中将张应力和压应力施加到半导体器件中的半导体器件及其制造方法。

Claims (21)

1.一种制造半导体结构的方法，包括下列步骤：
在衬底中形成浅沟槽隔离(25)；
在衬底上提供第一材料(30)；
在衬底上提供第二材料(40)；
通过热退火工艺，将第一材料(30)和第二材料(40)混合到衬底中，以便分别在nFET区和pFET区处形成第一岛(50)和第二岛(55)；以及
在第一岛(50)和第二岛(55)上形成晶格常数不同于第一岛(50)和第二岛(55)的材料层，
其中，浅沟槽隔离(25)弛豫并有利于第一岛(50)和第二岛(55)的弛豫。
2.根据权利要求1的方法，其中，所述第一材料(30)是淀积的Ge材料，而所述第二材料(40)是淀积的Si:C或C。
3.根据权利要求1的方法，其中，所述热退火工艺在1200-1350℃下进行。
4.根据权利要求1的方法，其中，所述形成材料层的步骤是在第一岛(50)和第二岛(55)上生长Si材料层。
5.根据权利要求4的方法，其中，所述第一岛(50)包含SiGe，第二岛(55)包含Si:C，且Si材料层是应变层。
6.根据权利要求1的方法，其中，所述浅沟槽隔离(25)由粘滞性随温度上升而下降的材料组成。
7.根据权利要求4的方法，其中，所述Si材料层在第一岛(50)上被置于张应力中，而在第二岛(55)上被置于压应力中。
8.根据权利要求1的方法，其中，所述第一岛(50)和所述第二岛(55)具有不同的弛豫晶格。
9.根据权利要求1的方法，其中，所述浅沟槽隔离(25)是高温稳定的非晶材料。
10.根据权利要求1的方法，其中，在所述混合步骤之前，第一材料(30)和第二材料(40)被淀积在衬底上。
11.根据权利要求1的方法，其中，在所述混合步骤之前，第一材料(30)和第二材料(40)被生长在衬底上。
12.根据权利要求1的方法，其中，所述第二材料(40)是按照在热退火工艺时产生大于1％但不大于2％的Si:C的浓度的剂量注入的C。
13.根据权利要求1的方法，其中，所述第二材料(40)是按照在热退火工艺时产生大于2％的Si:C的浓度的剂量注入的C。
14.根据权利要求1的方法，其中，所述材料层包括在第一岛(50)和第二岛(55)上选择性生长的Si外延层，此Si外延层具有不同于第一岛(50)和第二岛(55)的晶格常数，使得此选择性生长的Si外延层将分别在第一岛(50)和第二岛(55)上张应变和压应变。
15.根据权利要求1的方法，其中，所述第一岛(50)的晶格常数为a≥aSi，而所述第二岛(55)的晶格常数为a≤aSi。
16.根据权利要求15的方法，其中，所述第一岛(50)由SiGe组成，而所述第二岛(55)由Si:C组成，，SiGe岛和Si:C岛上有选择性生长的Si外延层，Si外延层由于分别与SiGe和Si:C的晶格匹配，而分别处于张应力和压应力下。
17.根据权利要求1的方法，其中，第二岛(55)由Si:C组成，并在热退火工艺时，C的范围为1-4％。
18.一种制造半导体结构的方法，包括下列步骤：
形成衬底；
在衬底中形成高温稳定的非晶材料的浅沟槽隔离；
将至少一种材料热退火到衬底中，以便形成混合材料的第一岛(50)和第二岛(55)；以及
至少在第一岛(50)上生长Si层，
使Si层按照压应力和张应力之一应变。
19.根据权利要求18的方法，其中，存在下列情况之一：
所述至少一种材料是Ge，且第一岛(50)和第二岛(55)由弛豫SiGe的混合材料组成，
所述至少一种材料是C或Si:C，且第一岛(50)和第二岛(55)由弛豫Si:C的混合材料组成，以及
所述至少一种材料是Ge和Si:C，或者是Ge和C，且第一岛(50)由SiGe组成，第二岛(55)由Si:C组成。
20.根据权利要求19的方法，其中，所述Si层的晶格常数不同于所述SiGe材料和所述Si:C材料的晶格常数，且衬底也由高温稳定的非晶材料组成。
21.一种通过权利要求18的方法形成的半导体结构。
CN200480034036.6A 2003-11-19 2004-06-30 Si:C-OI和SGOI上的硅器件及其制造方法 Expired - Lifetime CN101208794B (zh)

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