CN101154670B - Pixel structure and manufacturing method thereof - Google Patents
Pixel structure and manufacturing method thereof Download PDFInfo
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- CN101154670B CN101154670B CN2007101820629A CN200710182062A CN101154670B CN 101154670 B CN101154670 B CN 101154670B CN 2007101820629 A CN2007101820629 A CN 2007101820629A CN 200710182062 A CN200710182062 A CN 200710182062A CN 101154670 B CN101154670 B CN 101154670B
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Abstract
一种像素结构及其制造方法，该像素结构适于配置在一透明基板上，其包括一扫描配线、一栅绝缘层、一数据配线、一遮光层、一介电层、一薄膜晶体管、一保护层、一接触窗以及一像素电极；其中，遮光层配置在透明基板的表面上且对应配置于数据配线的两侧，介电层配置在该数据配线与遮光层上方的栅绝缘层之间；其可以降低寄生电容量，并可避免因数据配线与其两侧的遮光层所产生的寄生电容不一致，而导致显示不均匀的情形。
A pixel structure and its manufacturing method, the pixel structure is suitable for disposing on a transparent substrate, which includes a scanning wiring, a gate insulating layer, a data wiring, a light-shielding layer, a dielectric layer, and a thin film transistor , a protective layer, a contact window, and a pixel electrode; wherein, the light-shielding layer is arranged on the surface of the transparent substrate and is correspondingly arranged on both sides of the data wiring, and the dielectric layer is arranged on the grid above the data wiring and the light-shielding layer. Between the insulating layers; it can reduce the parasitic capacitance, and can avoid the unevenness of the display due to the inconsistency of the parasitic capacitance generated by the data wiring and the light-shielding layers on both sides.
Description
The application is for be that " dot structure and manufacture method thereof ", application number are dividing an application of 02153826.3 Chinese invention patent application proposition according to denomination of invention.
Technical field
The invention relates to a kind of structure and manufacture method thereof of semiconductor subassembly, and particularly relevant for a kind of Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, dot structure TFT-LCD) and manufacture method thereof.
Background technology
Thin Film Transistor-LCD mainly is made of plurality of groups of substrates of thin-film transistor, colorized optical filtering multiple substrate and liquid crystal layer, wherein plurality of groups of substrates of thin-film transistor is the thin-film transistor of being arranged with array by a plurality of, and a pixel electrode (Pixel Electrode) of corresponding configuration with each thin-film transistor is formed.And above-mentioned thin-film transistor comprises grid, channel layer, source electrode and drain electrode, and the film crystal piping is used as the switch module of liquid crystal display.
The operating principle of thin-film transistor component and traditional semiconductor MOS assembly are similar, all are the assemblies with three terminals (grid, source electrode and drain electrode).Usually thin-film transistor component can be divided into two types of amorphous silicon and polysilicon materials.Wherein, amorphous silicon film transistor is to belong to comparatively mature technique.With regard to the amorphous silicon film transistor LCD, its manufacturing process roughly is included in and forms grid, channel layer, source/drain, pixel electrode and protective layer on the substrate.
Shown in Figure 1, it illustrates to looking schematic diagram on existing a kind of dot structure; Shown in Figure 2, it illustrates the generalized section by I-I ' into Fig. 1.
Please be simultaneously with reference to Fig. 1 and Fig. 2, existing one pixel structure process method at first provides a transparency carrier 100.Then, the one scan distribution 130 that on transparency carrier 100, forms a grid 102 and be connected with grid 102, and on transparency carrier 100, form a shading metal level 132a, 132b simultaneously, and shading metal level 132a, 132b are formed on predetermined both sides that form the data wiring place.Afterwards, on transparency carrier 100, form a gate insulation layer 104, cover grid 102, scan wiring 130 and shading metal level 132a, 132b.
Then, on the gate insulation layer above the grid 102 104, form a channel layer 106.Then, on channel layer 106, form source 108a/108b, and on gate insulation layer 104, form a data wiring 140 that is connected with source electrode 108a simultaneously, wherein data wiring 140 direction of being extended is vertical with the direction that scan wiring 130 is extended, and is formed with shading metal level 132a, 132b under the gate insulation layer 104 of data wiring 140 both sides.And grid 102, channel layer 106 and source/drain 108a/108b constitute a thin-film transistor 120.
Afterwards, above transparency carrier 100, form a protective layer 110, cover thin-film transistor 120 and data wiring 140.Continue it, in protective layer 110, form an opening 112, expose the drain electrode 108b of thin-film transistor.Then, on protective layer 110, form a pixel electrode 114, wherein be electrically connected to each other by opening 112 between the drain electrode 108b of pixel electrode 114 and thin-film transistor 120.At this, the pixel electrode 114 that is defined may cover shading metal level 132a, 132b simultaneously.
Owing to can produce between shading metal level 132a, 132b and the data wiring 140 and between shading metal level 132a, 132b and the pixel electrode 114 parasitic capacitance is arranged, be floating state owing to shading metal level 132a, 132b again, so the parasitic capacitance that it produced will be difficult to calculate and control.Particularly, if a little deviation is arranged when definition of data distribution 140, will cause the distance between data wiring 140 and shading metal level 132a, the 132b inconsistent, as shown in Figure 1, the distance of shading metal level 132a and data wiring 140 is little than the distance of shading metal level 132b and data wiring 140.Thus, the parasitic capacitance that shading metal level 132a, the 132b of data wiring 140 and its both sides produced can be inequality, in other words, CHARGE DISTRIBUTION between shading metal level 132a, the 132b of data wiring 140 and its both sides can be inhomogeneous, the color and the gray scale that so will cause two zones to show can be inhomogeneous, and it is called Shot Mura.
Summary of the invention
Therefore, purpose of the present invention is providing a kind of dot structure and manufacture method thereof exactly, and reducing parasitic capacitance, and then it is inconsistent and cause showing uneven situation according to parasitic capacitance between the shading metal level of distribution and its both sides to reduce factor.
The present invention proposes a kind of dot structure; it is suitable for framework on a transparency carrier, and this dot structure comprises one scan distribution, a gate insulation layer, a data wiring, a light shield layer, a dielectric layer, a thin-film transistor, a protective layer, a contact hole and a pixel electrode.Wherein scan wiring is configured on the transparency carrier, and gate insulation layer is disposed on the transparency carrier, and covers scan wiring.Data wiring is disposed on the gate insulation layer, and the direction that data wiring extended is perpendicular to direction that scan wiring extended.In addition, light shield layer is configured on the transparency carrier, and the corresponding both sides that are configured in data wiring.And dielectric layer is configured between the gate insulation layer and data wiring of light shield layer top.At this, the light shield layer of data wiring both sides optionally is electrically connected to each other.Generally speaking, between light shield layer and data wiring, dispose gate insulation layer and dielectric layer.In addition, thin-film transistor is disposed on the transparency carrier, and thin-film transistor comprises a grid, a channel layer and source, wherein source electrode and data wiring electric connection, grid and scan wiring electrically connect, and channel layer is configured on the gate insulation layer of grid top.In addition, protective layer is disposed at the top of transparency carrier, covers thin-film transistor and data wiring.Contact hole is configured in the protective layer.And pixel electrode is disposed on the protective layer, and wherein pixel electrode electrically connects with drain electrode by contact hole.
The present invention proposes a kind of one pixel structure process method, the method at first forms the one scan distribution that a grid is connected with grid on a transparency carrier, and on transparency carrier, form a light shield layer simultaneously, wherein, light shield layer is formed on predetermined both sides that form the data wiring place, and is formed on the predetermined light shield layer that forms both sides, data wiring place and can optionally be electrically connected to each other.Afterwards, on transparency carrier, form a gate insulation layer, cover grid, scan wiring and light shield layer.Then, on the gate insulation layer of grid, form a channel layer, on the gate insulation layer on the light shield layer, form a dielectric layer.On channel layer, form source then, and on gate insulation layer, form a data wiring that is connected with source electrode simultaneously, wherein grid, channel layer and source/drain constitute a thin-film transistor, and are formed with gate insulation layer and dielectric layer between light shield layer and the data wiring.Continue it, above transparency carrier, form a protective layer, cover thin-film transistor and data wiring.Then in protective layer, form an opening, expose drain electrode.Form a pixel electrode afterwards on protective layer, wherein pixel electrode electrically connects with drain electrode by opening.
Dot structure of the present invention and manufacture method thereof, since between data wiring and the light shield layer except a gate insulation layer is arranged, also include a dielectric layer, the relation that is inversely proportional to based on the thickness of electric capacity and capacitance dielectric layer, therefore this kind structure and method can reduce parasitic capacitance, and then reduce factor and differ and cause according to the parasitic capacitance of distribution both sides and show uneven situation.
Dot structure of the present invention and manufacture method thereof, because being configured in the light shield layer of data wiring both sides is electrically connected to each other, therefore the electric capacity that light shield layer produced of data wiring and its both sides balance mutually, and avoid factor to differ according to the parasitic capacitance of distribution both sides and cause the uneven situation of demonstration.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Fig. 1 is for looking schematic diagram on existing a kind of dot structure;
Fig. 2 is the generalized section of Fig. 1 by I-I ';
Fig. 3 is according to looking schematic diagram on a kind of dot structure of a preferred embodiment of the present invention;
Fig. 4 is the generalized section of Fig. 3 by II-II ';
Fig. 5 is according to looking schematic diagram on a kind of dot structure of a preferred embodiment of the present invention;
Fig. 6 is the generalized section of Fig. 5 by III-III ';
Fig. 7 is the generalized section according to a kind of dot structure of a preferred embodiment of the present invention.
Indicate explanation:
100: transparency carrier 102: grid
104: gate insulation layer 106: channel layer
108a/108b: source/drain 110: protective layer
112: opening (contact hole) 114: pixel electrode
120: thin-film transistor 130: scan wiring
132a, 132b: light shielding part 132c: connecting portion
134,160: light shield layer
140: data wiring 150: dielectric layer
Embodiment
First embodiment
Shown in Figure 3, it illustrates and is the above-mentioned schematic diagram according to the dot structure of a preferred embodiment of the present invention; Shown in Figure 4, its illustrate among Fig. 3 by the generalized section of II-II '.
Please refer to Fig. 3 and Fig. 4, a transparency carrier 100 at first is provided, wherein transparency carrier 100 for example is a glass substrate or a plastic base.Then, the one scan distribution 130 that on transparency carrier 100, forms a grid 102 and be connected with grid 102, and on transparency carrier 100, become a light shield layer 134 simultaneously.Wherein, light shield layer 134 is made of a light shielding part 132a, 132b and a junction 132c, and light shielding part 132a, 132b be configured in predetermined both sides that form the data wiring place, and connecting portion 132c couples together light shielding part 132a, 132b.
In the present embodiment, the material of grid 102, scan wiring 130 and light shield layer 134 for example is conductors such as tantalum, titanium or aluminum metal.Afterwards, comprehensive formation one gate insulation layer 104 on transparency carrier 100, cover grid 102, scan wiring 130 and light shield layer 134.Wherein, gate insulation layer 104 for example is a silicon nitride layer or one silica layer.
Then, on the gate insulation layer above the grid 102 104, form a channel layer 106.And on the surface of channel layer 106, also comprise and be formed with an ohmic contact layer (not illustrating).At this, the material of channel layer 106 for example is amorphous silicon (a-Si), and the material of ohmic contact layer for example is through doped amorphous silicon (n+-Si).
Then, on channel layer 106, form source 108a/108b, and on gate insulation layer 104, form a data wiring 140 that is connected with source electrode 108a simultaneously, wherein data wiring 140 direction of being extended is vertical with the direction that scan wiring 130 is extended, and is formed with light shield layer 134 under the gate insulation layer 104 of data wiring 140 both sides.And grid 102, channel layer 106 and source/drain 108a/108b constitute a thin-film transistor 120.
Afterwards, above transparency carrier 100, form a protective layer 110, cover thin-film transistor 120 and data wiring 140.Continue it, in protective layer 110, form an opening 112, expose the drain electrode 108b of thin-film transistor.Then; on protective layer 110, form a pixel electrode 114; wherein pixel electrode 114 is electrically connected to each other by opening 112 with the gap of the drain electrode 108b of thin-film transistor 120, and the pixel electrode 114 that is defined may cover part light shield layer 134 simultaneously.
The dot structure of this enforcement is owing to be electrically connected to each other by connecting portion 132c between light shielding part 132a, the 132b of its shielding layer 134, therefore the parasitic capacitance that produced of light shielding part 132a, the 132b of data wiring 140 and its both sides balance mutually then, so can avoid factor to differ according to the electric capacity of distribution 140 both sides and cause showing uneven situation.
The present embodiment another kind can prevent to show uneven one pixel structure process method as shown in Figure 5, and Fig. 5 is for according to looking schematic diagram on the dot structure of another preferred embodiment of the present invention, and Fig. 6 is by the generalized section of III-III ' among Fig. 5.
Please refer to Fig. 5 and Fig. 6, as described previously, on transparency carrier 100, form in grid 102 and the scan wiring 130, also on transparency carrier 100, form a light shield layer 160.At this, formed light shield layer 160 crosses a predetermined block shading metal level 160 that forms the data wiring place.
Afterwards, above transparency carrier 100, form a gate insulation layer 104, cover grid 102, scan wiring 130 and light shield layer 160.
Then, as discussed previously, a data wiring 140 that forms a channel layer 106, source 108a/108b in regular turn and be connected with source electrode 108a is to constitute a thin-film transistor 120.Afterwards, form a protective layer 110, a contact hole 112 and a pixel electrode 114 according to previous described method again, to finish the making of a dot structure.
At this, because the light shield layer 160 of data wiring 140 belows is for crossing a block shading metal level of data wiring 140, make the current potential of light shield layer 160 of data wiring 140 both sides equate, therefore can avoid factor to differ and cause showing uneven situation according to the electric capacity of distribution 140 both sides.
Dot structure of the present invention is suitable for framework on a transparency carrier 100, and this dot structure comprises one scan distribution 130, a gate insulation layer 104, a data wiring 140, a light shield layer 134 (or light shield layer 160), a thin-film transistor 120, a protective layer 110, a contact hole 112 and a pixel electrode 114.
Wherein, scan wiring 130 is configured on the transparency carrier 100, and gate insulation layer 104 is disposed on the transparency carrier 100, and covers scan wiring 130.Data wiring 140 is disposed on the gate insulation layer 104, and data wiring 140 direction of the being extended direction of being extended perpendicular to scan wiring 130.
In addition, light shield layer 134 is configured on the surface of transparency carrier 100, and the corresponding both sides that are disposed at data wiring 140, and wherein the light shield layer 134 of data wiring 140 both sides is electrically connected to each other.In the present embodiment, light shield layer 134 is made of a light shielding part 132a, 132b and a junction 132c, wherein light shielding part 132a, 132b correspondence are configured in the both sides of data wiring 140, couple together and connecting portion 132c will be configured in light shielding part 132a, the 132b of data wiring 140 both sides.In addition, light shield layer 160 of the present invention can also be a block shading metal level 160 that crosses the data wiring both sides.
In addition, thin-film transistor 120 is disposed on the transparency carrier 100, and thin-film transistor 120 comprises a grid 102, a channel layer 104 and source 108a/108b, wherein source electrode 108a and data wiring 140 electrically connect, grid 102 electrically connects with scan wiring 130, and channel layer 106 is configured on the gate insulation layer 104 of grid 102 tops.In addition, protective layer 110 is disposed at the top of transparency carrier 100, covers thin-film transistor 120 and data wiring 140.Contact hole 112 is configured in the protective layer 110.And pixel electrode 114 is disposed on the protective layer 110, and wherein pixel electrode 114 electrically connects with drain electrode 108b by contact hole 112.
Second embodiment
Another kind of the present invention can prevent to show uneven one pixel structure process method as shown in Figure 5 that Fig. 5 is the face schematic diagram according to the dot structure of another preferred embodiment of the present invention.
Please refer to Fig. 5, describe, on transparency carrier 100, form in grid 102 and the scan wiring 130, also on transparency carrier 100, form light shield layer 132a, 132b as previous prior art.Afterwards, above transparency carrier 100, form a gate insulation layer 104, cover grid 102, scan wiring 130 and light shield layer 132a, 132b.Then, additionally form a dielectric layer 150 again on the gate insulation layer on light shield layer 132a, the 132b 104, wherein the material of dielectric layer 150 for example is a silicon nitride.
Continue, a data wiring 140 that forms a channel layer 106, source 108a/108b in regular turn and be connected with source electrode 108a is to constitute a thin-film transistor 120.Wherein, except being formed with gate insulation layer 104, also be formed with a dielectric layer 150 between formed data wiring 140 and light shield layer 132a, the 132b.Afterwards, previous in regular turn more described method forms a protective layer 110 1 contact holes 112 and a pixel electrode 114, to finish the making of a dot structure.
What deserves to be mentioned is that the formation one dielectric layer 150 in extra between data wiring 140 and light shield layer 132a, the 132b of present embodiment can reduce the parasitic capacitance that is produced between data wiring 140 and light shield layer 132a, the 132b.In addition, in this embodiment, can optionally be electrically connected to each other between light shield layer 132a, the 132b.For example shown in Figure 1, do not electrically connect between light shield layer 132a, the 132b, or as shown in Figure 3, electrically connect by connecting portion 132c between light shield layer 132a, the 132b, or as shown in Figure 5, light shield layer 160 crosses the both sides of data wiring 140.
The dot structure of present embodiment; it is suitable for framework on a transparency carrier 100, and this dot structure comprises one scan distribution 130, a gate insulation layer 104, a data wiring 140, a light shield layer 132a, 132b (or light shield layer 134,160), a dielectric layer 150, a thin-film transistor 120, a protective layer 110, a contact hole 112 and a pixel electrode 114.
Wherein, scan wiring 130 is configured on the transparency carrier 100, and gate insulation layer 104 is disposed on the transparency carrier 100, and covers scan wiring 130.Data wiring 140 is disposed on the gate insulation layer 104, and data wiring 140 direction of the being extended direction of being extended perpendicular to scan wiring 130.
In addition, light shield layer 132a, 132b are configured on the transparency carrier 100, and the corresponding both sides that are configured in data wiring 140.And dielectric layer 150 is configured between the gate insulation layer 104 and data wiring 140 of light shield layer 132a, 132b top.At this, light shield layer 132a, the 132b of data wiring 140 both sides optionally are electrically connected to each other. Light shield layer 132a, 132b for example shown in Figure 1 ( light shield layer 132a, 132b do not electrically connect), or as Fig. 3 and light shield layer 134,150 (light shield layer of data wiring both sides has the relation of electric connection) shown in Figure 5.Generally speaking, dispose gate insulation layer 104 and dielectric layer 150 between light shield layer 132a, the 132b of present embodiment (or light shield layer 134,160) and the data wiring 140.
In addition, thin-film transistor 120 is disposed on the transparency carrier 100, and thin-film transistor 120 comprises a grid 102, a channel layer 106 and source 108a/108b, wherein source electrode 108a and data wiring 140 electrically connect, grid 102 electrically connects with scan wiring 130, and channel layer 106 is configured on the gate insulation layer 104 of grid 102 tops.In addition, protective layer 110 is disposed on the gate insulation layer 104, covers thin-film transistor 120 and data wiring 140.Contact hole 112 is configured in the protective layer 110.And pixel electrode 114 is disposed on the protective layer 110, and wherein pixel electrode 114 electrically connects with drain electrode 108b by contact hole 112.
At this, since between data wiring 140 and light shield layer 132a, the 132b (or light shield layer 134,160) except being formed with gate insulation layer 104, also be formed with a dielectric layer 150, the relation that is inversely proportional to based on the thickness of electric capacity and capacitance dielectric layer, therefore the structure of present embodiment and method can reduce the parasitic capacitance between data wiring 140 and light shield layer 132a, the 132b (or light shield layer 134,160), cause showing uneven phenomenon because of parasitic capacitance is inconsistent to reduce data wiring 140 both sides whereby.
Dot structure of the present invention and manufacture method thereof, because being configured in the light shield layer of data wiring both sides is electrically connected to each other, therefore the electric capacity that light shield layer produced of data wiring and its both sides balance mutually, and the parasitic capacitance about avoiding factor according to distribution differs and cause the uneven situation of demonstration.
Dot structure of the present invention and manufacture method thereof, since between data wiring and the light shield layer except a gate insulation layer is arranged, also include a dielectric layer, the relation that is inverse ratio based on the thickness of electric capacity and capacitance dielectric layer, therefore this kind structure and method can reduce parasitic capacitance, and then reduce the parasitic capacitance of factor about according to distribution and differ and cause and show uneven situation.
Though the present invention with preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claims.
Claims (10)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021538263A CN1504816A (en) | 2002-11-28 | 2002-11-28 | Pixel structure and manufacturing method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021538263A Division CN1504816A (en) | 2002-11-28 | 2002-11-28 | Pixel structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101154670A CN101154670A (en) | 2008-04-02 |
| CN101154670B true CN101154670B (en) | 2010-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101820633A Expired - Fee Related CN100514658C (en) | 2002-11-28 | 2002-11-28 | Pixel structure and its manufacturing method |
| CNA021538263A Pending CN1504816A (en) | 2002-11-28 | 2002-11-28 | Pixel structure and manufacturing method thereof |
| CN2007101820629A Expired - Fee Related CN101154670B (en) | 2002-11-28 | 2002-11-28 | Pixel structure and manufacturing method thereof |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2007101820633A Expired - Fee Related CN100514658C (en) | 2002-11-28 | 2002-11-28 | Pixel structure and its manufacturing method |
| CNA021538263A Pending CN1504816A (en) | 2002-11-28 | 2002-11-28 | Pixel structure and manufacturing method thereof |
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1317596C (en) * | 2004-11-15 | 2007-05-23 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| KR101119186B1 (en) | 2005-04-06 | 2012-03-20 | 삼성전자주식회사 | Display panel, display apparatus having the same and method of fabricating the same |
| CN100533236C (en) * | 2005-11-29 | 2009-08-26 | 中华映管股份有限公司 | pixel structure |
| CN100451795C (en) * | 2006-11-13 | 2009-01-14 | 友达光电股份有限公司 | Pixel structure |
| CN100499085C (en) * | 2006-11-17 | 2009-06-10 | 友达光电股份有限公司 | Manufacturing method of pixel structure |
| CN100429765C (en) * | 2006-12-04 | 2008-10-29 | 友达光电股份有限公司 | Thin film transistor array substrate and method of manufacturing the same |
| TWI379140B (en) | 2008-04-22 | 2012-12-11 | Au Optronics Corp | Pixel structure and active device array substrate |
| CN101847652B (en) * | 2010-04-21 | 2011-08-17 | 友达光电股份有限公司 | Electroluminescent display panel |
| CN102269900B (en) * | 2010-06-03 | 2013-04-24 | 北京京东方光电科技有限公司 | Thin film transistor (TFT) array substrate and making method thereof |
| CN103730475B (en) | 2013-12-26 | 2016-08-31 | 京东方科技集团股份有限公司 | A kind of array base palte and manufacture method, display device |
| CN106298840B (en) * | 2015-06-09 | 2019-08-02 | 群创光电股份有限公司 | Display device |
| CN114155812A (en) * | 2016-08-30 | 2022-03-08 | 索尼半导体解决方案公司 | Display device and electronic apparatus |
| CN106298956A (en) | 2016-09-08 | 2017-01-04 | 武汉华星光电技术有限公司 | The preparation method of oxide thin film transistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369731A (en) * | 2001-01-29 | 2002-09-18 | 株式会社日立制作所 | Liquid crystal display |
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2002
- 2002-11-28 CN CNB2007101820633A patent/CN100514658C/en not_active Expired - Fee Related
- 2002-11-28 CN CNA021538263A patent/CN1504816A/en active Pending
- 2002-11-28 CN CN2007101820629A patent/CN101154670B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369731A (en) * | 2001-01-29 | 2002-09-18 | 株式会社日立制作所 | Liquid crystal display |
Non-Patent Citations (2)
| Title |
|---|
| JP特开2001-209041A 2001.08.03 |
| JP特开平9-329804A 1997.12.22 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100514658C (en) | 2009-07-15 |
| CN101154671A (en) | 2008-04-02 |
| CN101154670A (en) | 2008-04-02 |
| CN1504816A (en) | 2004-06-16 |
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