JPS6139579A - Thin film transistor matrix array and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] The present invention relates to a thin film transistor (hereinafter referred to as rTFTJ).
The present invention relates to a device and its manufacturing method. In more detail,
If so, the present invention can reduce short-circuits between bus lines and bus line disconnections connecting individual TFTs arranged in a matrix array, and can achieve high-yield application of TFTs to active matrix display panels.
The present invention relates to an FT matrix array and its manufacturing method.

Conventional technology Figure 2 shows a cross section of a TFT using an amorphous SL, where 1 is a glass substrate, 2 is a gate electrode made of a metal such as NLCr, and 3 is a silicon dioxide (such as St(h)). A gate insulating film, 4 is a semiconductor (for example, amorphous silicon), 5 and 6 are source and drain electrodes.A voltage is applied to the gate electrode 2 to create a channel in the amorphous silicon layer 4 directly under the gate electrode, and the source, A conductive state is established between the drains 5 and 6. To fabricate this TFT, a gate electrode material is deposited on a glass substrate 1, patterned to form a gate electrode 2, and Si is deposited on top of it by CVD.
A gate insulating film 3 is formed by growing O□ and patterning, and an amorphous silicon layer 4 is grown thereon by the CVD method and patterned to form a semiconductor layer. An electrode material is deposited on it and patterned. Then, source and drain electrodes 5.6 are made. A TFT device in which such TFTs are arranged in a matrix array is attracting attention as a driving element for a large liquid crystal display partitioned into a matrix.

FIG. 3 shows an example, where GS is a glass plate, S is a source electrode, and G is a gate. These constitute the vertical and horizontal lines of the matrix. D is a drain electrode, which is rectangular and has a large area, and forms a pair of electrodes of a liquid crystal panel together with a counter electrode ITO, as shown in FIG. 4, and liquid crystal is sealed between these electrodes. The spacing between the electrodes is about 10 μm.

When a biasing voltage is applied to select the source electrode S and the gate electrode G, the source voltage is applied to the drain D that constitutes the TFT together with the selected source and gate electrode, and the arrangement of the liquid crystal between the drain and the counter electrode 170 is changed. The area changes and becomes transparent so you can see it.

FIG. 5 is a diagram schematically showing an enlarged view of one element of the TFT matrix array in FIG.
The line and the Vl-Vl line correspond to FIGS. 2 and 6, respectively. A conventional method for manufacturing a TFT matrix array will be described with reference to FIGS. 5 and 6.

Conventionally, bus lines for TFT matrix arrays have been manufactured in the same process as electrodes for individual TFTs. That is, according to the conventional method, at the intersection 10 where the gate bus line G conducting to the gate electrode 2 (FIG. 6) and the drain bus line D passing four times to the drain electrode 6 intersect, the gate bus line G and the drain path 9470 are connected to each other. A TFT gate insulating film 3 is used as a film for interlayer insulation.

In the above case, the areas W and XW are larger than the overlapping area of the gate electrode (2) and drain electrode 6 of the TFT.

At the intersection 10 where the width is large, the amount of defects such as pinholes in the film increases in proportion to the intersection area, so there is a problem that a short circuit occurs between the gate bus line G and the drain path 9470 at the intersection 10. .

In particular, in recent years, amorphous TFTs have been manufactured in which the junction capacitance between the source electrode 5 and the drain electrode 6 is reduced by aligning the source electrode 5 and the drain electrode 6 with the gate electrode 2. Since the overlap width of 6 is extremely small, just over 1 micron, short circuits in this area can be reduced, but if the conventional crossover partial interlayer insulation method is used for such amorphous TFTs, short circuits in the crossover area will still be reduced. No, the above amorphous TFT is disclosed in Japanese Patent Application Laid-Open No. 58-170067 (Japanese Patent Application No. 57-53239).
This was proposed by the applicant in .

Furthermore, in the conventional cross-over partial interlayer insulation method, the bus line (D, G) material deposition process is limited to before and after the formation of the gate insulating film 3 in the individual TFT fabrication process, resulting in a high probability of disconnection.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to reduce the occurrence of short circuits between bus lines at intersections and the occurrence of bus line disconnections in a TFT matrix array. Furthermore, it is an object of the present invention to make it possible to introduce an interlayer insulating film between bus lines other than a gate insulating film by performing the fabrication of source/drain electrodes of individual TFTs of a TFT matrix array and the fabrication of drain bus lines in separate steps. The purpose is to provide a method.

Means for Solving the Problems The TFT matrix array according to the present invention is a thin film transistor (T P A TFT matrix array in which a large number of TFTs are arranged in a matrix, and the gate electrode of each TFT is connected to a gate bus line, and the drain electrode of each TFT is connected to a drain bus line that intersects with the gate bus line, A feature of the present invention is that an interlayer insulating film having a lower dielectric constant and being thicker than the gate insulating film is formed to cover the intersection of each bus line.

The method for manufacturing a TFT matrix array according to the present invention includes:
Individual TFTs connected to each other only by gate bus lines
After completion of the process, a drain bus line connecting the drain electrodes of each individual TFT is fabricated.

In general, the gate insulation film of a TFT is a thin film made of a material with a high dielectric constant, such as S with a film thickness of several thousand angstroms.
Composed of iO□ film. Vapor deposition, spatter, CVD, and plasma CV that can be adopted as gate insulating film formation methods
It is fully possible to use such an insulating film made by D or the like and having a thickness of several thousand layers as the gate insulating film of the entire individual TFT without any defects. However, with the conventional method of using a film of the same type and thickness as the gate insulating film for interlayer insulation at the intersections of the TFT matrix array, it is difficult to eliminate pinholes over the entire display panel area of several hundred cIll. .

On the other hand, the film required for interlayer insulation at bus line intersections in a TFT matrix array does not need to have the effect of applying a potential to the semiconductor like the gate insulating film of a TFT, and instead operates as a reliable insulator. It is essential to do so. Therefore, according to the present invention, if a film having a lower dielectric constant and thicker than the gate insulating film of the TFT is used for interlayer insulation at the bus line intersection portion, short circuits and the like can be prevented in the entire bus line intersection portion of the TFT matrix array. Furthermore, in the present invention, by performing the fabrication of the source/drain electrodes of individual TFTs and the fabrication of drain bus lines in separate processes, it is possible to use low dielectric constant and A pinhole-free membrane is introduced, reducing shorts between bus lines. In addition,
There are technical documents that describe a matrix array in which source bus lines and gate bus lines form a matrix array, and it goes without saying that the interlayer insulation of the present invention can be applied to the intersections thereof.

chiasm spots Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the sixth part of the TFT matrix array according to the present invention.
FIG. 3 is a sectional view corresponding to the figure. 21 is a transparent insulator substrate such as a glass substrate, 22 is a gate electrode, 23 is a gate insulating film such as SiO□, 24 is a semiconductor film such as an amorphous semiconductor, 25 is a source electrode, and 26 is a drain electrode. A large number of TFTs composed of elements 22 to 26 are arranged in a matrix on a transparent insulating substrate 21. In addition to the above-mentioned elements 22 to 26, the present applicant's earlier application/Japanese Patent Application No. 57-53239 (Japanese Unexamined Patent Publication No. 58-1989)oo
Other elements can be added, such as an amorphous semiconductor to fill the gap between the source electrode 25 and the drain electrode as shown in No. 67).

The interlayer insulating film 24 between the drain bus line D and the gate bus line G of the TFT matrix array is made of an organic material such as polyimide (dielectric constant=2 to 3) or an inorganic material.

8A to 8F show TFTs for liquid crystal display using the present invention.
The fabrication process of a matrix array is shown. FIG. 7 shows the planar pattern of the TFT matrix array manufactured by the processes shown in FIGS. 8A to 8F, and will be explained in order of the zero-order process.

First step: A gate electrode e and an ITO display electrode f with a bus line are formed on a glass substrate l (FIG. 8A).

2nd step: SiN:H gate insulation MK and a (amorphous) -5i:H semiconductor film j by plasma CVD method
is continuously formed into a film (Fig. 8B).

Third step: SiN:H gate insulating film a-5i:
The H semiconductor film j is patterned by etching (FIG. 8C).

Fourth step: Forming the source electrode and drain electrode i (
Figure 8D). In this fourth step, the individual TFTs are completed, and these individual TFTs are connected to the gate bus line e (7th
(Figure) are interconnected only. In the next step,
An interlayer insulating film is formed. Although there are no particular limitations on this forming method, a coating method capable of forming a thick film, particularly a spin-coating method, is preferred.

Fifth step: A polyimide interlayer insulating film is formed so that part of the drain electrode i, part of the source bridge, and the entire display electrode f are exposed (Fig. 8E).
g is a drain electrode/drain bus line contact hole.

In the sixth step, a metal film C, which will become a pad for connecting the drain bus lines a1 and light shielding film b1, is simultaneously formed and patterned (FIG. 8F).

Through this step, the TFT matrix array is completed.

In FIG. 7, a polyimide film (d) is formed at the intersection 10 of the drain bus line a and the gate bus line e. The polyimide film (d) may optionally be formed only on this intersection 10, but as shown in the figure, the polyimide interlayer insulating film is left over the TFT and the TFT protective film (d) is formed.
However, it is desirable to share the same information. Furthermore, this protective film t
TF in the same process as drain bus line (a) fabrication on dl.
It is desirable to also form a T light shielding film (b).

Results (1) The interlayer insulation according to the present invention can reduce short circuits between bus lines and disconnections of drain bus lines in a TFT matrix array, thereby improving yield in manufacturing flat active matrix display devices. This is effective in reducing costs and improving display quality.

+21 T P T Matrix Array Individual TFTs
First, an array interconnected only with gate bus lines is fabricated, and the interlayer insulating layer and drain bus line are fabricated in the subsequent steps, which increases the degree of freedom in fabricating bus lines and reduces disconnections. .

(3) A protective film necessary for an amorphous TFT can be formed in the same process as an interlayer insulating layer, and a light shielding film can be formed in the drain bus line.

[Brief explanation of the drawing]

FIG. 1 is a partial sectional view of a TFT matrix array according to the present invention, FIG. 2 is a sectional view of a TFT, FIG. 3 is a plan view of a TFT matrix array, FIG. 4 is a sectional view of FIG. 3, and FIG. is a conceptual plan view showing a unit pattern of a TFT matrix array; FIG. 6 is a corresponding view of FIG. 1 according to the conventional method; FIG. 7 is a plan view showing an embodiment of a TFT matrix array according to the present invention; Figures 8F to 8F are diagrams illustrating the manufacturing process of the array shown in Figure 7. 1...Glass substrate 1, 2...Gate electrode, 3
...Gate insulating film, 4...Semiconductor, 5...
Source electrode, 6... Drain electrode, a...
Drain bus line, b...light shielding film, C...metal for connecting source electrode/display electrode, d...polyimide interlayer insulating film/TFT protective film, e...gate no<sline (gate electrode), f...Display electrode, g...Drain electrode/drain bus line contact hole, h...
Source electrode, i... drain electrode.

Claims (1)

[Claims] 1. On a transparent insulating substrate, a gate electrode, a gate insulating film,
A large number of thin film transistors (TFTs), each consisting of a semiconductor film, source/drain electrodes, and other layers and patterned in sequence, are arranged in a matrix, and the gate electrode of each TFT intersects with the gate bus line, and the drain electrode intersects with the gate bus line. A TFT matrix array each connected to a drain bus line, characterized in that an interlayer insulating film having a lower dielectric constant and thicker than a gate insulating film is formed so as to cover the intersection of each bus line. TFT matrix array. 2. The TFT matrix array according to claim 1, wherein the semiconductor film is an amorphous silicon semiconductor film. 3. The TFT matrix array according to claim 1 or 2, wherein the interlayer insulating film is also used for surface protection of individual TFT matrices. 4. On the transparent insulating substrate, a gate electrode, a gate insulating film,
A large number of thin film transistors (TFTs), each consisting of a semiconductor film, source/drain electrodes, and other layers and patterned in sequence, are arranged in a matrix, and the gate electrode of each TFT intersects with the gate bus line, and the drain electrode intersects with the gate bus line. In a method of manufacturing a TFT matrix array each connected to a drain bus line,
Individual TFTs connected to each other only by gate bus lines
After this is completed, an interlayer insulating film with a lower dielectric constant and thickness than the gate insulating film is formed to cover the intersections of each bus line, and a drain bus line is created to connect the drain electrodes of each individual TFT. A method for manufacturing a TFT matrix array, characterized in that: 5. The method according to claim 4, wherein the interlayer insulating film is left on top of the TFT and is also used as a protective film for the TFT. 6. The method according to claim 5, characterized in that a light-shielding film for the TFT is also formed on the protective film in the same process as drain bus line fabrication.