CN101109972A - New CMOS Voltage Reference Source Without BJT Structure - Google Patents

Abstract

The utility model pertains to the field of the analog integration reference source circuit, more particularly, a BJT-free CMOS voltage reference source which comprises a start circuit, a biasing circuit and a reference source circuit. Only MOS tube is used for the voltage reference source to realize the reference voltage, while the three-electrode tube is not needed. Therefore, the utility model has the advantages of simple structure, low power consumption and space-saving, so that the utility model can meet the moderate required precision as demanded by the power tube driver circuit and the voltage sensing circuit, etc.

Description

The Novel CMOS voltage reference source of no BJT structure

Technical field

The invention belongs to the integrated reference source circuit technical field of simulation, be specifically related to a kind of cmos voltage reference source of the BJT of nothing structure.

Technical background

Traditional band-gap reference is because its output voltage absolute value accurately, low-temperature coefficient and Power Supply Rejection Ratio be used widely in various Analogous Integrated Electronic Circuits and mixed signal circuit [1] preferably.Along with CMOS technology more and more becomes the IC manufacturing process of main flow, people also expect total system, comprise simulation reference source, can use the CMOS technology to realize.Though can utilize parasitic triode to realize band-gap reference in the CMOS technology, also exist excessively such as area, power consumption is than problems such as height.Therefore, utilize pure CMOS technology to realize that the research of voltage or current reference is carried out and make certain gains [2,3,4].

The voltage reference of no BJT structure is broadly divided into two kinds at present: one is based on the reference voltage source [2] of metal-oxide-semiconductor subthreshold value indicial response; Two are based on the threshold voltage of metal-oxide-semiconductor, such as document [3] propose based on enhancement mode and depletion type NMOS pipe threshold voltage difference; The former requires some metal-oxide-semiconductor to be operated in sub-threshold region, and than higher, structure is also complicated to the requirement of circuit design; And the latter be owing to need realize strengthening on same silicon chip and depletion type MOS tube, to the technological requirement height, thereby the cost height, simultaneously, the absolute value of voltage that these two kinds of structures obtain is all bigger with the simulation value deviation, so all is not widely used.The benchmark architecture that document [4] proposes based on metal-oxide-semiconductor weight gate source voltage difference, circuit is simple, technology there is not specific (special) requirements, and relative accuracy height, on power supply and temperature characterisitic, can compare with traditional band gap reference, represented the latest developments of pure MOS benchmark architecture, but the absolute value of its output voltage is still bigger in different process corner lower deviations.

As seen, with respect to traditional band-gap reference, the defective of the benchmark maximum of pure MOS structure is that its technological parameter fluctuation that relies on is bigger, therefore the output voltage absolute value is difficult to control accurately.

Summary of the invention

The objective of the invention is to propose a kind of parasitic triode that need not to utilize, just can export the pure MOS structure voltage reference source of accurate voltage, its performance index can satisfy the application that medium accuracy requires.

Its integrated circuit of voltage-reference that the present invention proposes as shown in Figure 1, it is by start-up circuit 1, biasing circuit 2 and reference circuit 3 constitute, wherein start-up circuit 1 is made of metal-oxide-semiconductor MS1～MS3; Biasing circuit 2 is made of metal-oxide-semiconductor MB1-MB9 and resistance R b; Reference circuit 3 is made of PMOS pipe MP and NMOS pipe MN, wherein the grid of PMOS pipe MP links to each other and ground connection with drain electrode, the drain electrode of source electrode and NMOS pipe MN links to each other and the PMOS that is connected to biasing circuit 2 together manages the drain electrode of MB8, the grid of NMOS pipe MN links to each other with drain electrode and is connected to the source electrode that PMOS manages MP together, source electrode is received the drain electrode of the NMOS pipe MB9 of biasing circuit 2, the i.e. output node of circuit.

NMOS in the start-up circuit 1 pipe MS2 and MS3 respectively with biasing circuit 2 in NMOS pipe MB1 link to each other with PMOS pipe MB3, can normally start when being used for making circuit to power on; NMOS pipe MB8 in the biasing circuit 2 links to each other with NMOS pipe MN with the PMOS pipe MP of reference circuit 3 respectively with MB9, is used to provide required bias current.Start-up circuit 1 and biasing circuit 2 are the conventional simulation element circuit.

We can be so that flow through the electric current approximately equal of PMOS pipe MP and NMOS pipe MN by current mirror technique, and establishing this electric current is I _b, V _RefBe the output voltage of circuit, i.e. reference voltage, its value can be provided by following formula:

$V_{\mathrm{ref}}=V_{\mathrm{gsp}}-V_{\mathrm{gsn}}$

$=V_{\mathrm{thp}}+\sqrt{\frac{{2I}_b}{u_p{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_p}}-[V_{\mathrm{thn}}+\sqrt{\frac{2I_b}{u_n{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_n}}]$

$=V_{\mathrm{thp}}-V_{\mathrm{thn}}+\sqrt{\frac{{2I}_b}{C_{\mathrm{ox}}}}(\frac{1}{u_p{\left(\frac{W}{L}\right)}_p}-\frac{1}{u_n{\left(\frac{W}{L}\right)}_n})---\left(1\right)$

V in the following formula _GspAnd V _GsnThe gate source voltage of representing PMOS pipe MP and NMOS pipe MN respectively, V _ThpAnd V _ThnRepresent the threshold voltage of PMOS pipe MP and NMOS pipe MN respectively, L and W represent the long and grid width of the grid of metal-oxide-semiconductor respectively, (W/L) _p(W/L) _nBe the breadth length ratio of PMOS pipe and NMOS pipe, u _pAnd u _nThe mobility of representing hole and electronics respectively, C _OxBe the grid oxygen electric capacity of unit area.

In a typical C MOS technology, the threshold voltage of PMOS pipe MP and NMOS pipe MN normally changes in the same direction, and therefore, (1) formula can well be offset the threshold voltage variation that causes owing to process deviation, thereby has guaranteed output voltage V _RefConstant relatively.

Next investigate the temperature characterisitic of this structure, at first, bias current I _bCan not be desirable fully, it also is acted upon by temperature changes, and biasing circuit is shown in Fig. 1 left part, for the gate source voltage V of NMOS pipe MB1 and MB2 _Gs1And V _Gs2, following relation is arranged:

V _gs1＝V _gs2+I _bR _b

Therefore:

$I_b=\frac{2}{u_n{C}_{\mathrm{ox}}{R^2}_b}{(\frac{1}{{\left(\frac{W}{L}\right)}_1}-\frac{1}{{\left(\frac{W}{L}\right)}_2})}^2---\left(2\right)$

R wherein _bThe resistance of expression biasing resistor Rb, (W/L) ₁(W/L) ₂The breadth length ratio of representing NMOS pipe MB1 and MB2 respectively.Identical in the implication of other parameters and (1) formula.As seen, bias current I _bWith electron mobility u is arranged _nClose, and rate u _nBe the function of temperature, so I _bWith temperature correlation.Look in BSIM3V3 (the Berkeley short channel field effect transistor model) handbook with the formula of temperature correlation as can be known:

$u=u_0{\left(\frac{T}{T_0}\right)}^{\mathrm{ute}}---\left(3\right)$

$V_{\mathrm{th}}=V_{\mathrm{th}0}+(K_{\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="A20071004519600091.png"\; state="\{\{state\}\}">t</figure-callout>}1}+K_{t1l}/L_{\mathrm{eff}}+K_{t2}{V}_{\mathrm{bseff}})(\frac{T}{T_0}-1)---\left(4\right)$

More than in two formulas, u represents carrier mobility, u ₀Expression is as temperature T=T ₀(T ₀=u value 273K) time; Ute is the humidity index coefficient of mobility; V _ThExpression metal-oxide-semiconductor threshold voltage, V _Th0Expression is as temperature T=T ₀The time V _ThValue; K _T1Temperature coefficient for threshold voltage; K _TIlRepresent channel length to K _T1Related coefficient; K _T2Represent the body-effect coefficient of threshold voltage to temperature.

With (3) formula substitution (2) formula, again (2), (4) two formulas are all brought (1) formula into, then to the T differentiate, obtain through arrangement and abbreviation:

$\frac{{\&PartialD;V}_{\mathrm{ref}}}{\&PartialD;T}=\frac{(K_{t1p}+{\mathrm{<figure-callout\; id="1"\; label="K\; t"\; filenames="A20071004519600091.png"\; state="\{\{state\}\}">K</figure-callout>}}_t/L_{\mathrm{effp}}+K_{t2p}{V}_{\mathrm{bsefpf}})}{T_0}-\frac{(K_{t1n}+{\mathrm{<figure-callout\; id="1"\; label="K\; t"\; filenames="A20071004519600091.png"\; state="\{\{state\}\}">K</figure-callout>}}_t/L_{\mathrm{effn}}+K_{t2n}{V}_{\mathrm{bsefnf}})}{T_0}$

$+\sqrt{\frac{I_b}{{2C}_{\mathrm{ox}}}}(\sqrt{\frac{1}{u_p{\left(\frac{W}{L}\right)}_p}}({-\mathrm{ute}}_n-{\mathrm{ute}}_p)+\sqrt{\frac{1}{u_n{\left(\frac{W}{L}\right)}_n}}*{2\mathrm{ute}}_n)---\left(5\right)$

As previously mentioned, K _T1, K _TIl, K _T2, u _p, u _nBe technological parameter, can look into technical papers and obtain.By adjusting design parameter (W/L) _p(W/L) _n, finally can make $\frac{{\&PartialD;V}_{\mathrm{ref}}}{\&PartialD;T}=0,$ Thereby obtain the voltage-reference of a zero-temperature coefficient.

Major advantage of the present invention is: circuit is simple, realizes easily, need not to utilize the parasitic triode in the CMOS technology, also need not the high-gain amplifier of band gap reference requirement, and therefore low in energy consumption, it is little to take silicon area.

It is less demanding to adopt the controller of this structure to be applied to temperature coefficient, but needs the occasion of output voltage absolute value accurately, such as the power tube driver of synchronous rectification structure, and battery voltage detection circuit and other mixed signal circuit.

Description of drawings

The integrated circuit figure of Fig. 1, voltage-reference.

The temperature coefficient test result of Fig. 2, voltage-reference.

The line regulation test result of Fig. 3, voltage-reference.

Number in the figure: 1 is start-up circuit, and 2 is biasing circuit, and 3 is reference circuit.

Embodiment

Further describe the present invention below by embodiment.In this example, need to produce the reference voltage about a 1V, the threshold ratio that is used for the adaptive power driver and judge requires the absolute error≤50mV of output voltage.

At first according to the manual estimation biasing of bias current pipe sizing:

Electric current changes the influence that brings in (1) formula in order to reduce, and simultaneously also in order to reduce power consumption, can make I _bBe biased in lower level, get I _b=5uA.

The electric current of biasing circuit can be obtained littler, such as 5/3mA, offers main circuit by the amplification of current mirror mirror image then, and the breadth length ratio that can be obtained NMOS pipe MB1 and MB2 by formula (2) is respectively:

(W/L) ₁＝2 (W/L) ₂＝8

After having determined the size of main biasing circuit, PMOS pipe MB3 in the common-source common-gate current mirror, MB4, MB5, the breadth length ratio of MB6 also can be decided:

(W/L) ₃＝(W/L) ₄＝(W/L) ₅＝(W/L) ₆＝2

In the selection of L, the long L1 of grid, the L2 of NMOS pipe MB1 and MB2 get 2um, the long L3 of grid, the L4 of PMOS pipe MB3～MB6, and L5, L6 can get 4um in order to suppress the power supply influence.

Start-up circuit is not strict to the dimensional requirement of pipe, can guarantee that circuit normally starts, and makes simultaneously that power consumption is less to get final product, through emulation, the breadth length ratio of we selected PMOS pipe MS1 is 1um/30um, and the breadth length ratio of NMOS pipe MS2 is 10um/3um, and the breadth length ratio of NMOS pipe MS3 is 15um/1um.

The size Selection of NMOS pipe and PMOS pipe is the comparison key in the reference generating circuit, and equation (5) is an indeterminate equation, corresponding to each (W/L) _pValue, all corresponding one (W/L) _nValue, and under each different value, the performance of circuit all is different, so necessarily have one or some optimal values, and because the unpredictability of technique change makes that in fact optimal value also can't accurately provide, but we can pass through parameter scanning, find best in theory point, prerequisite is to make each pipe operate as normal in the saturation region.

We get (W/L) _p=1.8 (W/L) _n=1.5, for reduce the relative error that photoetching brings as far as possible, the grid length and the grid width of these two pipes to get medium size, such as the long Lp=5um of grid of PMOS pipe MP, the long Ln=3um of grid of NMOS pipe MN, its grid width W can determine thereupon.

Use emulation tool to carry out circuit stages emulation then, further adjust and parameters optimization, finally obtain the optimal size of each pipe.

This circuit is flow under Chartered (special permission semiconductor) 0.35um standard technology, and print has been carried out the test of temperature characterisitic and power supply characteristic, Fig. 2 be in temperature when 0 ℃ changes to 100 ℃, the relation curve of output voltage and temperature; Fig. 3 is a supply voltage when 1.8V changes to 4V, the relation curve of output voltage and supply voltage.Table 1 has been summed up the various performance index of this voltage reference, as seen the voltage reference relative error of this kind method design in ± 4.5mV (room temperature), with the absolute error of simulation value be 8mV, and because circuit is simple, its area is also very little, and 0.022mm is only arranged ²Even consider the influence of temperature variation and supply voltage, the error of this benchmark under worst case is also less than 10mV, and its error still can satisfy system requirements after amplifying output.

Table 1

Technology	Chartered 0.35um
		Supply voltage/electric current	3.3V/9uA
Reference voltage (simulation value)	322mV
		Reference voltage (test value)	314+4.5mV

Temperature coefficient	180ppm/℃
		Line regulation	±1.1％
Chip area	0.022mm 2

Attached:

The technological parameter that this circuit relates to is as follows:

u _nC _ox＝185.6 u _pC _ox＝110 V _thn＝0.6053 V _thp＝-0.845

ute _n＝-1.724 ute _p＝-1.724 kt1 _n＝-0.278 Kt2 _n＝-0.02

kt1l _n＝-20219e-8 Kt1 _p＝-0.56 Kt2 _p＝-0.046 Kt1l _p＝0

List of references:

[1].Y.P.Tsividis and R.W.Ulmer，“A CMOS Voltage Reference，”IEEE Journal ofSolid-State Circuits，vol.13，pp.774-778，Dec.1978.

[2].E.Vittoz and J.Fellrath，“CMOS analog integrated circuits based on weakinversion operation，”IEEE Journal of Solid-State Circuits，vol.SC-12，no.3，pp.224-231，Jun.1977

[3].H.-J.Song and C.-K.Kim，“A temperature-stabilized SOI voltage referencebased on threshold voltage difference between enhancement and depletionNMOSFETs，”IEEE Journal of Solid-State Circuits，vol.28，no.6，pp.671-677，Jun.1993.

[4].K.N.Leung and P.K.T.Mok，“A CMOS Voltage Reference Based onWeightedΔVGS for CMOS Low-Dropout Linear Regulators，”IEEE Journal ofSolid-State Circuits，VOL.38，NO.1，JANUARY 2003。

Claims (1)

1. A novel CMOS voltage reference source without a BJT structure, characterized in that it is made of a start-up circuit (1), a bias circuit (2) and a reference circuit (3); wherein the start-up circuit (1) consists of MOS transistors MS1～MS3 Composition; bias circuit (2) is composed of MOS transistors MB1 ~ MB9 and resistor Rb; reference circuit (3) is composed of PMOS transistor MP and NMOS transistor MN, wherein the gate and drain of PMOS transistor MP are connected and grounded, and the source It is connected to the drain of the NMOS transistor MN and is connected to the drain of the PMOS transistor MB8 of the bias circuit (2), the gate and the drain of the NMOS transistor MN are connected to the source of the PMOS transistor MP together, and the source is connected to To the drain of the NMOS transistor MB9 of the bias circuit (2), that is, the output node of the circuit; the NMOS transistors MS2 and MS3 in the start-up circuit (1) are respectively connected with the NMOS transistor MB1 and the PMOS transistor MB3 in the bias circuit (2) The NMOS transistors MB8 and MB9 in the bias circuit (2) are respectively connected to the PMOS transistor MP and the NMOS transistor MN of the reference circuit (3).

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