CN100383691C - Reference Current Source with Low Temperature Coefficient and Low Supply Voltage Coefficient - Google Patents

Abstract

The invention relates to a reference current source with low temperature coefficient and low power supply voltage coefficient, belonging to the technical field of power supply. The starting circuit in this power supply generates a low voltage to make the constant current generating circuit work. The starting circuit includes: a PMOS transistor for generating mirror current, two NMOS transistors for forming a current mirror, an NMOS transistor for starting a constant current generating circuit, and a resistance for controlling the turn-on and turn-off of the NMOS transistor. The constant current generating circuit includes: two PMOS transistors used to form a current mirror, capacitors used to prevent parasitic oscillations in the circuit, used to generate two emitter junction voltage PNP bipolar transistors, and used to perform differential amplification operations on voltage drops amplifier. This reference current source realizes the temperature stability of the output current by compensating the temperature coefficient of the on-chip resistance, and obtains a very low temperature coefficient; no external components and external signals are required, the structure is simple, the occupied area is small, and the power consumption is low. .

Description

Reference Current Source with Low Temperature Coefficient and Low Supply Voltage Coefficient

technical field

The invention relates to a reference current source with low temperature coefficient and low power supply voltage coefficient, belonging to the technical field of power supply.

Background technique

Current reference circuits are important components in analog integrated circuits. Because, for current, there are no losses on long metal wires, but for voltage, there are losses, so current reference sources are preferred in complex analog circuits with long metal wires. In addition, the operating frequency of the analog circuit designed by the current mode method is higher than that of the voltage mode circuit. Therefore, in modern electronic circuits and systems, reference current sources have a wide range of uses. Due to the wide range of applications of modern electronic systems and the harsher environment, it is required that the reference current source can work reliably in a wide temperature range (-25 ° C ~ 125 ° C) and a wide power supply voltage range. In the prior art, a bandgap circuit is generally used to realize a constant voltage source (reference voltage source), such as: K.N.Leung, P.K.T.Mok.A sub-1-V15-ppm/℃ CMOS bandgap voltage reference without requiring low threshold voltagedevice.IEEE Journal of Solid-State Circuits. 2002, 37(4): 526-530.

Contents of the invention

The purpose of the present invention is to propose a reference current source with low temperature coefficient and low power supply voltage coefficient, which uses an energy gap circuit to realize the constant current source.

The reference current source with low temperature coefficient and low power supply voltage coefficient proposed by the present invention includes a starting circuit and a constant current generating circuit, wherein the starting circuit generates a low voltage to make the constant current generating circuit work; wherein the starting circuit includes:

(1) A PMOS transistor (M ₃ ) is used to generate mirror current, its source is connected to an external power supply, and its gate is connected to the drain of the NMOS transistor (M _s ) and the output terminal of the constant current generating circuit at the same time. The pole is connected to the drain and gate of the NMOS transistor (M ₅ );

(2) Two NMOS transistors (M ₄ and M ₅ ), used to form a current mirror to generate two currents, the sources of the two NMOS transistors (M ₄ and M ₅ ) are grounded, and their gates are connected to each other, and Connected to the drain of the NMOS transistor (M ₅ ), the drain of the NMOS transistor (M ₄ ) is connected to one end of the resistor Rs;

(3) An NMOS transistor (M _s ), which is used to start the constant current generating circuit, its gate is simultaneously connected to one end of the resistor Rs and the drain of the NMOS transistor (M ₄ ), and its source is grounded;

(4) Resistor Rs, used to control the turn-on and turn-off of the NMOS tube (M _s ), one end of which is connected to an external power supply;

The constant current generating circuit includes:

(5) Two PMOS transistors (M ₁ and M ₂ ) are used to form a current mirror to generate two currents (I ₁ , I ₂ ); the sources of the two PMOS transistors are connected to an external power supply, and their gates are interconnected , and connected to the output of the operational amplifier (O ₁ );

(6) Capacitor (C ₀ ), used to prevent parasitic oscillation in the circuit, one end of the capacitor is connected to the drain of the PMOS transistor (M ₁ ), and the other end is connected to the grid of the two PMOS transistors and the operational amplifier (O _{1 )} ) output end connection;

(7) PNP bipolar transistors (Q ₁ and Q ₂ ), used to generate two emitter junction voltages (V _BE1 , V _BE2 ), where the collector and base of PNP bipolar transistor Q ₁ are short-circuited, and the emitter and The drain of the above-mentioned PMOS transistor (M ₁ ) is connected to the opposite end of the operational amplifier (O ₁ ), and the emitter of the PNP bipolar transistor Q ₂ is connected to the PMOS (M ₂ ) through the resistor (R ₀ ). The drains are connected, and at the same time connected to the same direction end of the operational amplifier (O ₁ );

(8) Operational amplifier (O ₁ ), used for differential amplification of V1 and V2, where V1 is the emitter junction voltage drop of the PNP bipolar transistor (Q ₁ ), and V2 is the emitter junction voltage of the PNP bipolar transistor (Q ₂ ). The sum of the drop and the voltage drop across the resistor (R ₀ );

(9) Resistors (R ₁ , R ₂ ), used for resistance compensation of the circuit, one end of the resistor (R ₁ ) is grounded, the other end is connected to the reverse end of the operational amplifier (O ₁ ), and one end of the resistor (R ₂ ) Ground, and the other end is connected to the non-inverting end of the operational amplifier (O ₁ ).

The operational amplifier (O ₁ ) in the reference current source above consists of:

(1) Two PMOS transistors (M ₆ and M ₇ ) are used to generate constant current. The gates of the two PMOS transistors (M ₆ and M ₇ ) are interconnected and connected to the output terminal of the constant current generating circuit, and their sources At the same time, it is connected to an external power supply, the drain of the PMOS transistor (M ₆ ) is connected to the sources of two PMOS transistors (M ₈ and M ₉ ), the drain of the PMOS transistor (M ₇ ) is connected to the drain of the NMOS transistor (M ₁₂ ) Pole connected;

(2) Two PMOS transistors (M ₈ and M ₉ ) form a differential pair for inputting differential signals. The gates of the two PMOS transistors (M ₈ and M ₉ ) are respectively connected to the differential signal input terminals, and the PMOS transistors ( The drain of M ₈ ) is connected to the drain of the NMOS transistor (M ₁₀ ) and the gates of two NMOS transistors (M ₁₀ and M ₁₁ ), and the drain of the PMOS transistor (M ₉ ) is connected to the gate of the NMOS transistor (M ₁₁ ). connected to the drain;

(3) Two NMOS transistors (M ₁₀ and M ₁₁ ), which are used to form a current mirror, become the active load of the above differential pair, and are connected with PMOS transistors (M ₆ and M ₇ ) and PMOS transistors (M ₈ and M ₉ ) together perform first-stage differential amplification on the differential signal, the sources of the two NMOS transistors (M ₁₀ and M ₁₁ ) are grounded, and the drain of the NMOS transistor (M ₁₁ ) is connected to the drain of the PMOS transistor (M ₉ );

(4) NMOS transistor (M ₁₂ ), used for second-stage amplification of the above-mentioned amplified signal together with the PMOS transistor (M ₇ ), and the gate of the NMOS transistor (M ₁₂ ) is connected to the drain of the NMOS transistor (M ₁₁ ) at the same time and one end of the resistor R;

(5) Resistor (R) and capacitor (C), used for frequency compensation of the amplifier, one end of the capacitor (C) is connected to the resistor (R), and the other end is connected to the drain of the NMOS transistor (M ₁₂ ).

The reference current source with low temperature coefficient and low supply voltage coefficient proposed by the present invention has the following advantages:

1. The core circuit of the constant current source is based on the traditional energy gap circuit. Usually, the conventional bandgap circuit is used to realize the constant voltage source, but in the present invention it is used to realize the constant current source.

2. The temperature stability of the output current is obtained by compensating the temperature coefficient of the on-chip resistance, and a very low temperature coefficient is obtained. Propose a different optimization procedure.

3. The bipolar transistor in the present invention is base-collector short-circuited, so that the circuit can be implemented with a standard CMOS process, and can be easily applied to other complex systems. The circuit does not require external components and external signals, has a simple structure, occupies a small area, and consumes low power consumption.

4. The constant current source circuit integrates an operational amplifier, which has obtained good power supply voltage stability, so that the output current can remain basically unchanged at a power supply voltage higher than 1V, and can operate under low voltage and wide power supply voltage range. In normal operation, the temperature coefficient of the reference current source output is 50ppm/°C (temperature range: 0°C ~ 110°C), and the relative deviation in the power supply voltage range (1V ~ 2.3V) is 0.5%.

5. The start-up circuit ensures that the circuit works properly after power-up.

6. The use of capacitor C ₀ and the design of the operational amplifier ensure the stability of the circuit.

7. The constant current source has good process stability, can work normally under the condition of process fluctuation, and helps to obtain a higher processing yield.

Description of drawings

Fig. 1 is a structural block diagram of a reference current source designed in the present invention.

Fig. 2 is a schematic circuit diagram of the reference current source designed in the present invention.

Figure 3 is a circuit schematic diagram of the operational amplifier in the reference current source.

Fig. 4 is the temperature characteristic curve of the reference current source output power supply designed by the present invention.

Fig. 5 is a relationship curve between the output power and the power supply voltage of the reference current source designed in the present invention.

Detailed ways

The reference current source with low temperature coefficient and low power supply voltage coefficient proposed by the present invention has a structural block diagram as shown in Figure 1, including a starting circuit and a constant current generating circuit, wherein the starting circuit generates a low voltage to make the constant current generating circuit Work. Its circuit diagram is shown in Figure 2, including:

(1) A PMOS transistor (M ₃ ) is used to generate mirror current, its source is connected to an external power supply, and its gate is connected to the drain of the NMOS transistor (M _s ) and the output terminal of the constant current generating circuit at the same time. The pole is connected to the drain and gate of the NMOS transistor (M ₅ );

(2) Two NMOS transistors (M ₄ and M ₅ ), used to form a current mirror to generate two currents, the sources of the two NMOS transistors (M ₄ and M ₅ ) are grounded, and their gates are connected to each other, and Connected to the drain of the NMOS transistor (M ₅ ), the drain of the NMOS transistor (M ₄ ) is connected to one end of the resistor Rs;

(3) An NMOS transistor (M _s ), which is used to start the constant current generating circuit, its gate is simultaneously connected to one end of the resistor Rs and the drain of the NMOS transistor (M ₄ ), and its source is grounded;

(4) Resistor Rs, used to control the turn-on and turn-off of the NMOS tube (M _s ), one end of which is connected to an external power supply;

The constant current generating circuit includes:

(5) Two PMOS transistors (M ₁ and M ₂ ) are used to form a current mirror to generate two currents (I ₁ , I ₂ ); the sources of the two PMOS transistors are connected to an external power supply, and their gates are interconnected , and connected to the output of the operational amplifier (O ₁ );

(6) Capacitor (C ₀ ), used to prevent parasitic oscillation in the circuit, one end of the capacitor is connected to the drain of the PMOS transistor (M ₁ ), and the other end is connected to the grid of the two PMOS transistors and the operational amplifier (O _{1 )} ) output end connection;

(7) PNP bipolar transistors (Q ₁ and Q ₂ ), used to generate two emitter junction voltages (V _BE1 , V _BE2 ), where the collector and base of PNP bipolar transistor Q ₁ are short-circuited, and the emitter and The drain of the above-mentioned PMOS transistor (M ₁ ) is connected to the opposite end of the operational amplifier (O ₁ ), and the emitter of the PNP bipolar transistor Q ₂ is connected to the PMOS (M ₂ ) through the resistor (R ₀ ). The drains are connected, and at the same time connected to the same direction end of the operational amplifier (O ₁ );

(8) Operational amplifier (O ₁ ), used for differential amplification of V1 and V2, where V1 is the emitter junction voltage drop of the PNP bipolar transistor (Q ₁ ), and V2 is the emitter junction voltage of the PNP bipolar transistor (Q ₂ ). The sum of the drop and the voltage drop across the resistor (R ₀ );

(9) Resistors (R ₁ , R ₂ ), used for resistance compensation of the circuit, one end of the resistor (R ₁ ) is grounded, the other end is connected to the reverse end of the operational amplifier (O ₁ ), and one end of the resistor (R ₂ ) Ground, and the other end is connected to the non-inverting end of the operational amplifier (O ₁ ).

The operational amplifier (O ₁ ) in the reference current source above consists of:

(1) Two PMOS transistors (M ₆ and M ₇ ) are used to generate constant current. The gates of the two PMOS transistors (M ₆ and M ₇ ) are interconnected and connected to the output terminal of the constant current generating circuit, and their sources At the same time, it is connected to an external power supply, the drain of the PMOS transistor (M ₆ ) is connected to the sources of two PMOS transistors (M ₈ and M ₉ ), the drain of the PMOS transistor (M ₇ ) is connected to the drain of the NMOS transistor (M ₁₂ ) Pole connected;

(2) Two PMOS transistors (M ₈ and M ₉ ) form a differential pair for inputting differential signals. The gates of the two PMOS transistors (M ₈ and M ₉ ) are respectively connected to the differential signal input terminals, and the PMOS transistors ( The drain of M ₈ ) is connected to the drain of the NMOS transistor (M ₁₀ ) and the gates of two NMOS transistors (M ₁₀ and M ₁₁ ), and the drain of the PMOS transistor (M ₉ ) is connected to the gate of the NMOS transistor (M ₁₁ ). connected to the drain;

(3) Two NMOS transistors (M ₁₀ and M ₁₁ ), which are used to form a current mirror, become the active load of the above differential pair, and are connected with PMOS transistors (M ₆ and M ₇ ) and PMOS transistors (M ₈ and M ₉ ) together perform first-stage differential amplification on the differential signal, the sources of the two NMOS transistors (M ₁₀ and M ₁₁ ) are grounded, and the drain of the NMOS transistor (M ₁₁ ) is connected to the drain of the PMOS transistor (M ₉ );

(4) NMOS transistor (M ₁₂ ), used for second-stage amplification of the above-mentioned amplified signal together with the PMOS transistor (M ₇ ), and the gate of the NMOS transistor (M ₁₂ ) is connected to the drain of the NMOS transistor (M ₁₁ ) at the same time and one end of the resistor R;

(5) Resistor (R) and capacitor (C), used for frequency compensation of the amplifier, one end of the capacitor (C) is connected to the resistor (R), and the other end is connected to the drain of the NMOS transistor (M ₁₂ ).

The above start-up circuit is used to ensure that the circuit can be stabilized at a desired value when it is powered on, and the P-channel metal-oxide-semiconductor (hereinafter referred to as PMOS) transistors of other circuits are connected to the gate of the PMOS transistor in the core circuit. A current mirror is formed to mirror the constant current generated in the core circuit to other circuits in the chip. The PMOS transistors _M1 and _M2 are identical, as are the resistors _R1 and _R2 . All components are implemented on-chip. Three parameters ensure the temperature stability of the constant current source. One is the base-emitter voltage V BE1 and V _BE2 of the PNP bipolar transistors Q ₁ and Q ₂ with the two bases and collectors short-circuited, which has a negative temperature _{coefficient; the second is the V BE of} the transistors Q ₁ and Q ₂ The difference between ΔV _BE , which has a positive temperature coefficient. ; The third is the temperature coefficient of the sheet resistance.

For _Q1 and _Q2 in Figure 2, if the ratio of their emitter areas is N and the currents through the emitters are equal, the difference ΔVBE between their VBEs is determined by:

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

in $V_T=\frac{\mathrm{kT}}{q},$ T is the absolute temperature, and k is the Boltzmann constant. It can be seen that ΔVBE is proportional to the absolute temperature. Since the gain of the operational amplifier in the figure is very high (more than 10,000 times at DC), if there is a small voltage difference between the nodes V1 and V2, the voltage difference will appear on the output after being amplified by the operational amplifier, which will make The output of the op amp is saturated. Due to the feedback effect of _M1 and _M2 , the voltages of nodes V1 and V2 are equalized.

The inside of the operational amplifier and its two input terminals are connected to the gate of the MOS transistor, and its input impedance tends to be infinite, so no current will flow in or out. At the same time, the resistance values of the resistors R ₁ and R ₂ are also equal, so the currents flowing through them are also equal, and they are both proportional to the voltage V _BE1 , so by investigating the relationship between the currents at the node V2, we can get

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="N\; R"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">N</figure-callout></span><figure-callout\; id="0"\; label="N\; R"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">\; </figure-callout>}}{{\mathrm{<span\; class="notranslate">\; </span>}}_{}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

是流过电阻R₀的电流，而

则等于流过电阻R₁的电流。In the above formula

is the current flowing through resistor _R0 , and

Then it is equal to the current flowing through the resistor _R1 .

In order to simplify the analysis, all parameters have only one-order temperature characteristics, which means that all parameters are assumed to have a linear relationship with temperature. Then V _T can be expressed as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; k</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="T"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">T</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; k</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&alpha;</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

where T ₀ is the center point of the temperature range of interest, for example, if the temperature range we are analyzing is (-25°C, 125°C), then T ₀ is 50°C and ΔT=TT ₀ .

Around temperature T ₀ , the first-order approximation of V _BE1 to temperature can be expressed as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{<span\; class="notranslate">\; \&PartialD;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; T</span>}}{<span\; class="notranslate">\; |</span>}_{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="T"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">T</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&beta;</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

All on-chip resistances are also temperature dependent, so _R0 can be expressed as:

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="R"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="R"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{<span\; class="notranslate">\; \&PartialD;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="R"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; T</span>}}{<span\; class="notranslate">\; |</span>}_{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="T"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">T</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="R"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; ,</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&gamma;</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

R ₁ and R ₀ use the same type of resistors, and their ratio does not change with temperature. If m=R ₁ /R ₀ , when:

$\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; q</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="k\; T"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">k</figure-callout></span><figure-callout\; id="0"\; label="k\; T"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">\; </figure-callout>}{\mathrm{<span\; class="notranslate">\; </span>}}_{}{\mathrm{<span\; class="notranslate">T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&beta;</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&gamma;</span>}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&alpha;</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&gamma;</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

Then the expression of the temperature-independent current at this time is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="R"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; k</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V\; BE"\; filenames="C20031010047500102.png,C20031010047500112.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="1"\; label="V\; BE"\; filenames="C20031010047500102.png,C20031010047500112.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}}{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

Connect point A to the gates of other PMOS transistors, and the temperature-stabilized currents in _M1 and _M2 are mirrored into these transistors.

If the saturation current of _Q1 is I _S1 , then:

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V\; BE"\; filenames="C20031010047500102.png,C20031010047500112.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="1"\; label="V\; BE"\; filenames="C20031010047500102.png,C20031010047500112.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; k</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

Substituting formula (8) into formula (7), we get:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="R"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="T"\; filenames="C20031010047500111.png,C20031010047500112.png"\; state="\{\{state\}\}">T</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; \&CenterDot;</span>\frac{\mathrm{<span\; class="notranslate">\; k</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; m</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

All parameters in this expression have nothing to do with the power supply voltage, so it can also obtain relatively good power supply voltage stability. Also, since the op amp forces the voltages V1 and V2 to be equal, the four terminal voltages of _M1 (i.e. source, gate, drain, and substrate voltages) are equal to the corresponding terminal voltages of _M2 , ensuring their drain The pole currents are exactly equal, reducing errors caused by power supply voltage variations and achieving low power supply voltage coefficients.

Capacitor C ₀ is used to prevent possible parasitic oscillations.

Without the help of the startup circuit, the output current of this constant current source will always be zero. Therefore, the circuit needs a start-up circuit to ensure that it stabilizes to the correct state during power-up. The approach we take is to bring current through _M1 and _M2 in Figure 2 to bring the circuit out of the dead zone. The startup circuit we designed is shown in Figure 2. The current in the resistor R _s is mirrored by the current folding of M ₁ or M ₂ in Figure 2. If the current is zero, there is no voltage drop across R _s , and the N-channel metal-oxide-semiconductor (NMOS) tube The gate level of M _S is equal to the supply voltage. When the power supply voltage V _DD is higher than the threshold voltage V _th of _MS , _MS is turned on, thereby pulling the level of node A down to the ground level, so the two PMOS transistors in Figure 2 start to conduct, and there is current From the power supply flows into _Q1 and _Q2 tubes below through two PMOS transistors. When the current increases to a certain level, the gate level of _MS is close to the ground level, and _MS is cut off, which isolates the startup circuit from the core circuit, the startup process ends, and the circuit enters a normal working state.

The circuit of the operational amplifier used in the circuit shown in Figure 2 is shown in Figure 3. Because the common-mode voltage of its input terminal is that the BE junction voltage drop of Q ₁ in Figure 2 is relatively low, so the input stage uses a PMOS differential pair instead of the usual NMOS differential pair. In order to make it work under the power supply voltage of 1V, the substrates of the two PMOS transistors of the differential pair are connected to their sources to eliminate the substrate bias effect.

In order to minimize the error between the two input ports, the op amp must have very high gain. For this reason, the present invention adopts a two-stage amplification structure, and uses a current mirror as a load. Resistor R and capacitor C are used for frequency compensation to ensure the stability of the op amp. In addition, long trench devices are used to reduce mismatch and offset between devices. Its bias current is mirrored by a constant current generated in the core circuit to improve the power supply rejection ratio.

The relationship between the output current and the temperature of the constant current source circuit is shown in FIG. 4 . In the temperature range of 0°C to 110°C, the temperature coefficient of the current is 50ppm/°C. The relationship between the output current of the constant current source circuit and the power supply voltage is shown in FIG. 5 . It can be seen that when the current exceeds 1V, the current is completely stable. For the nominal output current of 527μA, the relative variation within the supply voltage range of 1V to 2.3V does not exceed 0.5%. Has very good supply voltage stability.

Claims (2)

1. A reference current source with low temperature coefficient and low supply voltage coefficient, characterized in that the reference current source includes a starting circuit and a constant current generating circuit, wherein the starting circuit generates a low voltage to make the constant current generating circuit work, The startup circuit includes: (1) A PMOS transistor _M3 is used to generate mirror current, its source is connected to an external power supply, its gate is connected to the drain of NMOS transistor M _S and the output terminal of the constant current generating circuit, and its drain is connected to the NMOS transistor The drain of _M5 is connected to the gate; (2) Two NMOS transistors M ₄ and M ₅ are used to form a current mirror to generate two currents. The sources of the two NMOS transistors M ₄ and M ₅ are grounded, and their gates are connected to each other and connected to the NMOS transistor The drain of _M5 , the drain of the NMOS transistor _M4 is connected to one end of the resistor Rs; (3) An NMOS transistor M _S is used to start the constant current generating circuit, its gate is connected with one end of the resistor Rs and the drain of the NMOS transistor _M4 at the same time, and its source is grounded; (4) The resistance Rs is used to control the opening and closing of the NMOS transistor _Ms , and one end thereof is connected to an external power supply; The constant current generating circuit includes: (5) Two PMOS transistors M ₁ and M ₂ are used to form a current mirror to generate two currents I ₁ and I ₂ ; the sources of the two PMOS transistors are connected to an external power supply, and their gates are interconnected and connected to the output of the operational amplifier _O1 ; (6) Capacitor C ₀ is used to prevent parasitic oscillation in the circuit. One end of the capacitor is connected to the drain of the PMOS transistor M ₁ , and the other end is connected to the gates of the two PMOS transistors and the output terminal of the operational amplifier O ₁ simultaneously; (7) PNP bipolar transistors Q ₁ and Q ₂ are used to generate two emitter junction voltages V _BE1 and V _BE , where the collector and base of the PNP bipolar transistor Q ₁ are short-circuited, and its emitter is connected to the above-mentioned PMOS transistor M The drain of ₁ is connected, and at the same time connected with the reverse terminal of the operational amplifier O ₁ , the emitter of the PNP bipolar transistor Q ₂ is connected with the drain of the PMOS transistor M ₂ through the resistor R ₀ , and is connected with the operational amplifier O ₁ at the same time The same end is connected; (8) Operational amplifier O ₁ , used to differentially amplify V1 and V2, where V1 is the emitter junction voltage drop of PNP bipolar transistor Q ₁ , and V2 is the difference between the emitter junction voltage drop of PNP bipolar transistor Q ₂ and resistor R ₀ The sum of the voltage drop; (9) Resistors R ₁ and R ₂ are used for resistance compensation of the circuit. One end of resistor R ₁ is grounded, the other end is connected to the reverse end of operational amplifier O ₁ , one end of resistor R ₂ is grounded, and the other end is connected to operational amplifier O ₁ in the same direction. 2. The reference current source as claimed in claim 1, wherein said operational amplifier O ₁ comprises: (1) Two PMOS transistors M ₆ and M ₇ are used to generate constant current. The gates of the two PMOS transistors M ₆ and M ₇ are interconnected and connected to the output terminal of the constant current generating circuit, and their sources are simultaneously connected to the external The power supply is connected, the drain of the PMOS transistor _M6 is connected to the sources of the two PMOS transistors _M8 and _M9 , and the drain of the PMOS transistor _M7 is connected to the drain of the NMOS transistor _M12 ; (2) Two PMOS transistors M ₈ and M ₉ form a differential pair for inputting differential signals. The gates of the two PMOS transistors M ₈ and M ₉ are respectively connected to the differential signal input terminals, and the drain of the PMOS transistor M ₈ At the same time, it is connected to the drain of the NMOS transistor _M10 and the gates of the two NMOS transistors _M10 and _M11 , and the drain of the PMOS transistor _M9 is connected to the drain of the NMOS transistor _M11 ; (3) Two NMOS transistors M ₁₀ and M ₁₁ are used to form a current mirror and become the active load of the above-mentioned differential pair, and together with PMOS transistors M ₆ and M ₇ and PMOS transistors M ₈ and M ₉ perform differential signal In the first stage of differential amplification, the sources of the two NMOS transistors _M10 and _M11 are grounded, and the drain of the NMOS transistor _M11 is connected to the drain of the PMOS transistor _M9 ; (4) NMOS transistor M ₁₂ , which is used to perform second-stage amplification on the above-mentioned amplified signal after the first-stage differential amplification together with PMOS transistor M ₇ , and the gate of NMOS transistor M ₁₂ is connected to the drain of NMOS transistor M ₁₁ at the same time pole and one end of resistor R; (5) The resistor R and the capacitor C are used for frequency compensation of the amplifier. One end of the capacitor C is connected to the resistor R, and the other end is connected to the drain of the NMOS transistor _M12 .

Images