CN101106118A - Chip packaging structure - Google Patents

Abstract

The invention discloses a chip packaging structure, which comprises a loader, a chip, a plurality of first bonding wires, a plurality of second bonding wires and a packaging colloid, wherein the loader is provided with a plurality of first connecting points and at least one second connecting point, and the chip is provided with at least one first bonding pad and at least one second bonding pad. In addition, the first bonding wires are electrically connected with the first bonding pads and the first contacts, and the second bonding wires are electrically connected with the second bonding pads and the second contacts, wherein the first bonding pads are electrically connected with at least two first contacts through at least two first bonding wires, and the second bonding pads are electrically connected with one second contact through one second bonding wire. In addition, the packaging colloid is arranged on the loader to coat the chip, the first bonding wires and the second bonding wires.

Description

Chip package structure

technical field

The present invention relates to a chip package structure (Chip package structure), in particular to a wire bonding (Wire bonding) chip package structure.

Background technique

In recent years, with the rapid development of electronic technology and the rise of the semiconductor industry, electronic products that are more humane and better in function are constantly being introduced, and are designed towards the trend of light, thin, short and small. In the semiconductor industry, the production of integrated circuits (Integrated Circuits, IC) is mainly divided into three stages: integrated circuit design, integrated circuit production and integrated circuit packaging (package). In the packaging of integrated circuits, the bare chip is first completed through the steps of wafer fabrication, circuit design, photomask fabrication, and wafer cutting, and each bare chip formed by wafer cutting is passed through the bare chip The bonding pad on it is electrically connected to the packaging substrate, and then the bare chip is covered with encapsulant. The purpose is to prevent the bare chip from being affected by external humidity and dust pollution, and to provide The medium for the electrical connection between the bare chip and the external circuit to form a chip package (Chip Package) structure.

Please refer to FIG. 1A and FIG. 1B at the same time. FIG. 1A is a schematic diagram of a conventional chip packaging structure, and FIG. 1B is a top view of the chip packaging structure in FIG. 1A . The chip packaging structure 100a includes a carrier 110, a chip 120, a plurality of bonding wires 130, and an encapsulant 140, wherein the chip 120 is disposed on a surface of the carrier 110, and the plurality of bonding pads 122 on the chip 120 respectively pass through The bonding wires 130 are electrically connected to the plurality of contacts 112 on the carrier 110 by wire bonding. In addition, the encapsulant 140 is also disposed on the surface of the carrier 110, and the encapsulant 140 covers the plurality of contacts 112 of the carrier 110, the chip 120, and the plurality of bonding wires 130 connecting the contacts 112 and the pads 122 to prevent the chip from 120 is subject to external influences (such as moisture, dust, etc.), and can protect the bonding wire 130 from being damaged by external forces. In addition, the carrier 110 has a plurality of wires 102 , wherein the wires 102 are electrically connected between the contact point 112 a and the contact point 112 b. However, when the wire 102 is broken or an error occurs in the circuit layout, the electrical connection between the contact 112a and the contact 112b will disappear, that is, the contact 112b can no longer obtain the signal output by the chip 120 from the contact 112a. Therefore, the carrying seat 110 will lose its original function.

Please refer to FIG. 2 , which is a top view of another conventional chip packaging structure. It can be seen from FIG. 1B and FIG. 2 that the chip packaging structure 100b is similar to the above-mentioned chip packaging structure 100a, and the main difference is that the arrangement positions of the plurality of contacts 112 on the carrier 110 and the plurality of pads 122 on the chip 120 are different. (For example, the contact 112b in the chip package structure 100a is not provided but the contact 112c at another position is provided). In the chip package structure 100b, due to the requirements of the circuit layout, a wire 104 must be used to electrically connect the contact 112a and the contact 112c. However, the contacts 112 a and 112 c are respectively disposed on the carrier 110 and correspond to two sides of the chip 120 , that is, the wire 104 has a more difficult layout circuit than the wire 102 . In other words, the wires 104 are more likely to be broken or errors occur in the circuit layout, which makes the supporting seat 110 unusable. Therefore, how to maintain the electrical connection between the contacts when the wire is broken or the wiring layout of the wire is wrong is an important issue.

Contents of the invention

The technical problem to be solved by the present invention is to provide a chip packaging structure, which can still maintain the original function when the wires inside the carrier are broken or the wiring layout of the wires is wrong.

In order to solve the above technical problems, the present invention proposes a chip packaging structure, which includes a carrier, a chip, a plurality of first bonding wires, a plurality of second bonding wires and an encapsulant, wherein the carrier has a plurality of first contacts and at least one second contact, and the chip has at least one first pad and at least one second pad. In addition, the first welding wire is electrically connected to the first welding pad and the first contact, and the second welding wire is electrically connected to the second welding pad and the second contact, wherein the first welding pad is connected to at least two first welding pads through at least two first welding wires. The two first contacts are electrically connected, and the second welding pad is electrically connected to a second contact through a second welding wire. In addition, the encapsulation compound is disposed on the carrier to cover the chip, a plurality of first bonding wires and a plurality of second bonding wires.

According to an embodiment of the present invention, the carrier is, for example, a circuit substrate, and the first contacts and the second contacts are, for example, a plurality of connection pads.

According to an embodiment of the present invention, the carrier is, for example, a lead frame, and the first contacts and the second contacts are, for example, a plurality of pins.

According to an embodiment of the present invention, the first bonding wires include, for example, a pushpin-shaped bump and a bonding wire body, wherein the bonding wire body is connected to the pushpin-shaped bump, for example. In addition, the pushpin-shaped bumps in the first bonding wire are, for example, stacked on the first bonding pad, and the material of the bonding wire body and the pushpin-shaped bump is, for example, gold.

The present invention also proposes a chip packaging structure, which includes a plurality of bonding wires and the above-mentioned carrier, chip and packaging compound. The bonding wires electrically connect the contacts of the carrier and the bonding pads of the chip, wherein at least one bonding pad is electrically connected to at least two contacts through at least two bonding wires.

To sum up, in the chip packaging structure of the present invention, at least one pad and at least two contacts are electrically connected by at least two bonding wires, so that when the wire in the carrier is broken or the wiring layout of the wire is wrong , the bonding pad can still be electrically connected to the plurality of contacts through the bonding wire, so the chip packaging structure still has the original function.

After adopting the structure and manufacturing process of the present invention, in the chip packaging structure of the present invention, a plurality of bonding wires can be electrically connected to different contacts on the carrier on a bonding pad of the chip, wherein each bonding wire is connected with its thumbtack shaped bumps to connect to the pads. Compared with the prior art, the present invention has the following advantages:

1. When the wire connecting the two contacts in the carrier is broken or the circuit layout of the wire is wrong, the bonding wire connection method in the chip packaging structure of the present invention can make the two contacts still have an electrical connection.

2. When the wiring between the two contacts on the carrier has a difficult circuit layout in the carrier, the electrical connection between the two contacts can be simplified through the bonding wire connection method in the chip packaging structure of the present invention.

3. In the chip packaging structure of the present invention, the thumbtack-like bumps of each bonding wire are stacked on a bonding pad so that the wire bonding machine can smoothly avoid the chip or the bonding wire that has been bonded.

Description of drawings

FIG. 1A is a schematic diagram of a conventional chip packaging structure.

FIG. 1B is a top view of the chip package structure in FIG. 1A .

FIG. 2 is a top view of another conventional chip packaging structure.

FIG. 3A is a schematic diagram of a chip packaging structure according to a first embodiment of the present invention.

FIG. 3B is a top view of the chip package structure in FIG. 3A .

FIG. 4 is a top view of a chip packaging structure according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram of a chip packaging structure according to a third embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100a, 100b, 300a, 300b, 500: chip package structure

102, 104, 302, 304: wire

110, 310, 510: carrier

112, 112a, 112b, 112c, 512: contacts

120, 320, 520: chip

122, 522: welding pad

130, 530: welding wire

140, 350: encapsulation colloid

312, 312a, 312b, 312c: first contacts

314: second contact

322: First welding pad

324: Second welding pad

330, 330a, 330b, 330c, 330d: first welding wire

332: Welding wire body

334: Pushpin bump

340: Second welding wire

Detailed ways

Please refer to FIG. 3A and FIG. 3B at the same time. FIG. 3A is a schematic diagram of the chip packaging structure of the first embodiment of the present invention, and FIG. 3B is a top view of the chip packaging structure of FIG. 3A . It can be seen from the figure that the chip packaging structure 300a includes a carrier 310, a chip 320, a plurality of first bonding wires 330 (for example, 330a and 330b), a plurality of second bonding wires 340, and an encapsulant 350, wherein the chip 320 is, for example, It is arranged on the carrier 310, and the encapsulant 350 is also arranged on the carrier 310. The encapsulant 350 is used to cover the chip 320, a plurality of first bonding wires 330 and a plurality of second bonding wires 340, so as to prevent the chip 320 from The encapsulation compound 350 can protect the first bonding wire 330 and the second bonding wire 340 from being damaged by external force at the same time.

In addition, the carrier 310 of this embodiment has a plurality of first joints 312 (such as a first joint 312a and a first joint 312b) and one or more second joints 314, and the chip 320 has one or more first solder joints. pad 322 and one or more second pads 324 . In addition, the first welding wire 330 is used for electrically connecting the first welding pad 322 and the first contact 312 , and the second welding wire 340 is used for electrically connecting the second welding pad 324 and the second contact 314 . In this embodiment, the carrier 210 has a plurality of wires 302, wherein the wires 302 are electrically connected to the first contact 312a and the first contact 312b, and the first welding pad 322 has first welding wires 330a and 330b respectively. It is electrically connected to the first contact 312a and the first contact 312b, that is, the first welding pad 322 is electrically connected to two or more first contact 312 through two or more first welding wires 330 respectively. The second bonding pad 324 is electrically connected to a second contact 314 through a second bonding wire 340 .

Therefore, it can be seen from the above that when the wire 302 electrically connected between the first contact 312a and the first contact 312b is broken or the wiring layout of the wire 302 is wrong, the first welding wire 330a and 330b can still be connected to the second wire respectively. The electrical connection between the first contact 312a and the first contact 312b is such that the electrical connection between the first contact 312a and the first contact 312b is maintained continuously. In addition, the carrier 310 of the present invention can also be a circuit substrate, and the plurality of first contacts 312 and the plurality of second contacts 314 on the carrier 310 can be a plurality of connection pads.

To sum up, in order to understand the connection relationship between the above-mentioned first bonding wire 330 and the first bonding pad 322 , it will be described in detail below. Please refer to FIG. 3A , the wire bonding method of the present invention, for example, first forms a pushpin-shaped bump 334 on the first pad 322, and then uses a wire bonding machine to bond a wire body 332 to the first contact 312, and then The wire bonder stretches upwards for a certain distance, and then turns to pull the wire to the thumbtack-shaped bump 334 preformed on the first pad 322 , wherein the bonding wire body 332 and the thumbtack-shaped bump 334 are made of gold, for example. In this way, when the wire bonder intends to repeatedly bond the first bonding wire 330 between the first bonding pad 322 and the first contact 312 , the pushpin-shaped bumps 334 of each first bonding wire 330 will be stacked on top of each other. on a pad 322 . The above wire bonding method will enable the wire bonding machine to smoothly avoid other bonding wires or chips 320 that have been bonded.

Please refer to FIG. 4 , which is a top view of a chip package structure according to a second embodiment of the present invention. Please refer to FIG. 3B and FIG. 4 at the same time. The chip packaging structure 300b of this embodiment is similar to the above-mentioned chip packaging structure 300a. The main difference lies in the arrangement positions of the multiple contacts on the carrier 310 and the multiple pads on the chip 320. different (for example, the chip package structure 300b is not provided with the first contact 312b of the chip package structure 300a but is provided with the first contact 312c at another position). In the chip package structure 300b, for example, a wire 304 is used to electrically connect the first contact 312a and the first contact 312c to meet the requirements of the circuit layout. The first contact 312a and the first contact 312c are respectively arranged on the carrier 310 and correspond to two sides of the chip 320 , that is, the wire 304 has a more difficult circuit layout than the wire 302 in the chip package structure 300a. In this embodiment, the first pad 322 can be electrically connected to the first contacts 312c and 312a respectively through the first bonding wire 330c and the first bonding wire 330d. In other words, if the wire 304 between the first contact 312c and the first contact 312a is broken or the wiring layout of the wire 304 is wrong, the first contact 312c can still be connected through the first bonding wire 330c and the first bonding wire 330d. The electrical connection with the first contact 312a is maintained continuously.

The aforementioned chip packaging structures 300 a and 300 b are electrically connected to the first contact 312 and the first bonding pad 322 through the first bonding wire 330 , and are electrically connected to the second contact 314 and the second bonding pad 324 through the second bonding wire 340 . It should be noted that in other types of chip packaging structures, a bonding wire can be used to electrically connect the contacts on the carrier and the pads on the chip. FIG. 5 is a schematic diagram of a chip packaging structure according to a third embodiment of the present invention. Please refer to FIG. 3 and FIG. 5 at the same time. The chip packaging structure 500 is similar to the chip packaging structure 300a of the first embodiment, but the main difference is that the chip packaging structure 500 of this embodiment only uses a bonding wire 530 to electrically connect the carrier. Contact 512 on chip 510 and bonding pad 522 on chip 520 . Therefore, the chip packaging structure 500 has a simpler chip packaging process.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the implementation scope of the present invention; that is, all equivalent changes and modifications made according to the claims of the present invention are covered by the patent scope of the present invention.

Claims (10)

1. a chip-packaging structure is characterized in that, this chip-packaging structure comprises:

One carrier has a plurality of first contacts and at least one second contact;

One chip has at least one first weld pad and at least one second weld pad;

Many first bonding wires, it electrically connects this first weld pad and this first contact, and wherein this first weld pad electrically connects by at least two first bonding wires and two first contacts at least;

Many second bonding wires, it electrically connects this second weld pad and this second contact, and wherein this second weld pad electrically connects by one second bonding wire and one second contact; And

One packing colloid, it is arranged on this carrier, to coat this chip, described first bonding wire and described second bonding wire.

2. chip-packaging structure as claimed in claim 1 is characterized in that, this carrier is a circuit base plate, and described first contact and described second contact are a plurality of connection gaskets (connecting pad).

3. chip-packaging structure as claimed in claim 1 is characterized in that, this carrier is a lead frame, and described first contact and described second contact are a plurality of pins (lead).

4. chip-packaging structure as claimed in claim 1 is characterized in that, described each first bonding wire comprises:

One figure spike projection; And

One bonding wire body is connected on this figure spike projection.

5. chip-packaging structure as claimed in claim 4 is characterized in that, the described figure spike projection in described first bonding wire is stacked on this first weld pad each other.

6. chip-packaging structure as claimed in claim 4 is characterized in that, the material of this figure spike projection comprises gold.

7. chip-packaging structure as claimed in claim 4 is characterized in that the material of this bonding wire body comprises gold.

8. a chip-packaging structure is characterized in that, this chip-packaging structure comprises:

One carrier has a plurality of contacts;

One chip has a plurality of weld pads;

Many bonding wires, it electrically connects described weld pad and described contact, and wherein at least one weld pad electrically connects with at least two contacts by at least two bonding wires; And

One packing colloid, it is arranged on this carrier, to coat this chip and described bonding wire.

9. chip-packaging structure as claimed in claim 8 is characterized in that, this carrier is a circuit base plate, and described contact is a plurality of connection gaskets (connecting pad).

10. chip-packaging structure as claimed in claim 8 is characterized in that, this carrier is a lead frame, and described contact is a plurality of pins (lead).

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