CN101079376B - Making method for semiconductor part - Google Patents
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- CN101079376B CN101079376B CN200610026761A CN200610026761A CN101079376B CN 101079376 B CN101079376 B CN 101079376B CN 200610026761 A CN200610026761 A CN 200610026761A CN 200610026761 A CN200610026761 A CN 200610026761A CN 101079376 B CN101079376 B CN 101079376B
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Abstract
The invention discloses a making method of semiconductor element, which is characterized by the following: forming silica layer, polysilicon layer, metal silicate layer and silicon nitride layer on the semiconductor substrate; transmitting the grid pattern on the film layer to form grid through etching; proceeding high temperature annealing for the grid.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of grating of semiconductor element.
Background technology
Along with the progress of semiconductor technology and design, the storage density of dynamic random access memory is increasing and device size is more and more littler.Size reduces to bring intraconnections resistance to increase and its access speed is descended.For each memory cell, resistance is the key factor of decision storage and reading speed.Patent No. application number is the manufacture method that 93118158 Chinese patent discloses a kind of grid structure, promptly forms gate oxide, polysilicon layer and metal silicide layer on substrate.General metal-oxide semiconductor (MOS) adopts the substitution material of polysilicon (Polysilicon) as its gate metal layer more, yet has also introduced other problem, and promptly polysilicon has very high resistivity.Solution is to cover the layer of metal silicide on described polysilicon layer again, and tungsten silicide (WSix) titanium silicide (TiSix) for example is to reduce resistivity.
The manufacturing process of grid structure as shown in Figure 1 in the prior art: generate one deck thin oxide layer (S110a) on a doping such as N type (N-type) Semiconductor substrate.On described oxide layer, cover one deck polysilicon (S120a).Cover the layer of metal silicide on polysilicon, for example, tungsten silicide (WSix) (S130a).Deposition one deck silicon nitride (S140a) on described metal silicide.After finishing deposition, uniform temperature for example 900～1100 the degree under to its anneal (S150a).Spin coating photoresist and form gate patterns forms grid (S160a) with dry etching (Dry etch) then.In the prior art, the purpose of annealing is to eliminate the defective and the internal stress of film inside, reduces resistivity.Its principle is that the atom in the film can be reset under heat effect and makes defective disappear.But annealing temperature also can make the rearrangement of crystal grain in the film even in conjunction with forming bigger crystal grain, be difficult to control the profile variation after its profile makes etching when causing the rete etching.Fig. 2 is the profile that film is carried out the grid defective that etching causes after annealing.As shown in Figure 2, doped layer 105 is arranged on the substrate 100, narrow channel isolation (STI) 106 and the grid structure of being made up of oxide layer 110, polysilicon 120, metal silicide 130 and silicon nitride 140 that forms, metal silicide residual 131 is attached to the side formation defective of grid.Side wall 135 is used for protecting grid, and defective 131 has reached outside the side wall 135, and because stopping of defective 131 makes that the polysilicon 120 and the oxide layer 110 of defective below can not be by plasma institute etchings.Being used for being connected drain electrode 107 in the defective that forms and the connecting hole 150 is connected with the plain conductor of bit line.Defective 131 makes the metal in the contact hole 150 directly link to each other with grid.
Those skilled in the art will know that, dynamic random access memory is made up of the memory cell of array distribution, general have a MOS transistor and the capacitor of memory cell constitutes, word line (word line) leads to by grid Controlling Source leakage conductance or forbids, the drain electrode 107 of metal-oxide-semiconductor is connected to bit line (Bit line) by the metal in the bit line connecting hole 150, and source electrode 108 is connected to a pole plate of memory cell capacitor by the metal in the electric capacity contact hole.By word line control grid cut-in voltage is added to and makes the source form passage between leaking on the grid, the passage between data to be stored are then leaked by bit line and source is deposited into capacitor.In grid manufacturing process, can cause the profile of metal silicide 130 in the grid bad in the prior art, thereby can cause grid and be connected to the drain bit line short circuit.When in capacitor memory units, writing Z-operation, the high voltage that is added on the word line need be low-voltage on the bit line greater than the metal-oxide-semiconductor cut-in voltage, because word line and bit line are in gate lateral wall short circuit and form path and can not zero write capacitor, cause and write zero and fail.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of semiconductor device, to solve the problem of gate profile distortion in the prior art.
For achieving the above object, the manufacture method of a kind of semiconductor device provided by the invention, this method comprises:
A Semiconductor substrate is provided;
On described substrate, form oxide layer;
On described oxide layer, form polysilicon layer;
On described polysilicon layer, form metal silicide layer;
On described metal silicide layer, form silicon nitride layer;
The described silicon nitride of photoetching and etching, metal silicide, polysilicon and silica;
Annealing.
Described annealing temperature is 900～1100 degrees centigrade.
Described annealing time is 20～30 seconds.
Described metal silicide comprises tungsten silicide (WSix), titanium silicide (TiSix).
The thickness of described metal silicide is 500～1000 dusts.
This method further comprises: hydrofluoric acid (HF) and SC1, SC2 with dilution before forming oxide layer clean.
This method further comprises: clean with HF before the plated metal silicide.
Described etching is a dry etching.
The thickness of described polysilicon is 500～800 dusts.
The manufacture method of described polysilicon is chemical vapour deposition (CVD).
The thickness of described silicon oxide layer is 50 dusts～150 dusts.
Compared with prior art, the present invention has the following advantages: among the present invention, form gate oxide on Semiconductor substrate, polysilicon layer behind the metal silicide layer, carries out the etching processing procedure earlier, carries out annealing in process then.Avoid grain growth in the film that causes of annealing earlier in the prior art to increase the problem of profile distortion when the etching grid, further avoided the grid that therefore causes and the problem of bitline short circuits.Annealing is exactly to utilize thermal effect that the defective that produces owing to stress in the thin-film material of deposition is eliminated.Defective in the object is owing to the rearrangement of atom under the thermal effect effect disappears.The temperature of annealing can cause when raising that the interior crystal grain of thin-film material is reset even combination forms bigger crystal grain.Annealing in process under the high temperature of 900～1100 degree, the grain growth in the metal silicide becomes bigger particle.Dry etching is the chemical reaction process under ion bombardment, and ion bombardment has strengthened etching reaction speed and anisotropy by the mode of deface chemical bond and chemical reaction product.And the method for high annealing, in the lattice defect when repairing silicide in deposition, grain growth (Grain size growth) becomes bigger particle, has weakened the effect of ion bombardment, makes the etching profile be difficult to control.Easily after forming device, make grid and the short circuit of drain electrode line.If carry out etching earlier after finishing thin film deposition, the crystal grain particle of film inside is less, is easy to control when etching.Profile to the grid that forms after etching is finished is annealed, and under the high temperature of 900～1100 degree, the defective in the metal silicide is repaired behind atomic rearrangement, and its resistivity also descends to some extent.The present invention does not increase processing procedure, just exchanges the sequencing of etching and annealing in the process of making grid, thereby has avoided gate profile to be out of shape the short circuit problem that causes, has reduced the defective of the grid that forms in process of production, has improved the yield of product.
Description of drawings
Fig. 1 makes the flow chart of grid structure for prior art;
Fig. 2 is the profile of grid structure defective in the prior art;
Fig. 3 is for making the flow chart of grid structure among the present invention;
Fig. 4～Fig. 7 is the profile of explanation the inventive method.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The flow process of the inventive method as shown in Figure 3.A Semiconductor substrate at first is provided, and this substrate can be that the P type also can be a N type substrate (S100).And put described substrate and in the high-temperature oxydation stove, form a thin oxide layer (S110) thereon; On described oxide layer, deposit one deck polysilicon (S120) then; Then form a metal silicide layer (S130) on described polysilicon, this metal silicide materials can be tungsten silicide (Wsix), titanium silicide (TiSix).On described metal silicide, form a silicon nitride layer (S140); Follow again, form grid structure (S150) by chemical wet etching.The substrate that has grid structure that will form at last carries out annealing in process under 900～1100 degree high temperature, the time of annealing is 20～30 seconds (S160).
The following describes the detailed step of the inventive method.At first as shown in Figure 4, provide the Semiconductor substrate 200 of a p type or n type, ion injects and forms n trap or p trap layer 210.And form groove and fill spacer medium 215 by shallow trench isolation processing procedure (STI) and isolate active area.Successively to substrate 200 prerinse, remove staining and oxide layer of substrate 200 surfaces with the hydrofluoric acid (HF) of dilution and SC1, SC2 solution.Then substrate 200 is sent into oxidation furnace the high-temperature oxydation processing procedure is carried out on its surface, as shown in Figure 5, generate a thin oxide layer 220 as grid oxygen on its surface.The thickness of the grid oxygen that forms can be 50 dusts～150 dusts.There is the substrate 200 of oxide layer 220 to send into vapor deposition apparatus described growth, is approximately the polysilicon layer 230 of 500～800 dusts at its surface deposition one layer thickness, and described polysilicon layer 230 is mixed to reduce its resistivity by chemical vapour deposition (CVD).Clean the surface of described polysilicon layer 230 with hydrogen fluoride (HF) solution, remove surface oxide layer, for next step plated metal silicide layer 240 carries out surface preparation.Follow the resistivity of the metal silicide layer 240 of about hundreds of to one thousand dusts of deposit one layer thickness on described polysilicon layer 230 with further reduction grid.Described metal silicide comprises tungsten silicide (WSix), titanium silicide (TiSix).Though polysilicon layer 230 can reduce its resistivity through overdoping, its resistivity is still higher relatively, thereby can cause bigger signal delay when the grid structure size reduces.On polysilicon layer 230, cover metal silicide layer 240 and can reduce resistance with the polysilicon polyphone, and reduce contact resistance with polysilicon.Then on metal silicide layer 240, deposit one deck silicon nitride (SiN) layer 250.Then as shown in Figure 6, spin coating photoresist on described silicon nitride layer 250, exposure is developed the figure transfer of grid on the mask plate and is formed gate patterns 260 to photoresist and by developing apparatus.(Dry etch) transfers to described gate patterns on the substrate with the plasma dry etching. because the film that is used to form grid on the substrate 200 has multilayer and is to be made of different materials, different etch rates is arranged. thereby when etching, need select for use different materials to carry out etching step by step. for example, at first the silicon nitride layer 250 to the superiors carries out etching, it can be used as hard mask and further the metal silicide 240 and the polysilicon layer 230 of lower floor is carried out etching then, form grid structure as shown in Figure 7. promptly, be coated with oxide layer 220a successively in position, substrate 200 top, polysilicon layer 230a, metal silicide layer 240a, silicon nitride layer 250. is last, the substrate that will be formed with grid structure is sent into Equipment for Heating Processing under the high temperature of 900～1100 degree and carry out annealing in process in nitrogen environment, time is about 20～30 seconds. unlike the prior art be, among the present invention annealing steps being put into etching forms after the grid structure, rather than after the film that has deposited grid structure, carry out before the etching. to have avoided like this owing to carry out the influence of etching after the annealing high-temperature step gate profile. annealing is exactly to utilize thermal effect that the defective that produces owing to stress in the thin-film material that deposits is eliminated. and the defective in the object is owing to the rearrangement of atom under the thermal effect effect disappears. can cause the crystal grain that crystal grain is reset even combination formation is bigger in the thin-film material when temperature raises during annealing. in the present embodiment, the described oxide layer 210 of deposition on substrate 200, after polysilicon layer 220 and the metal silicide 230, if earlier it is carried out annealing in process, under the high temperature of 900～1100 degree, grain growth in the metal silicide 230 (Grain size growth) becomes bigger particle, thereby can cause that side profile is difficult to control when etching.Cause the gate profile distortion easily after forming device, to make grid and the short circuit of drain electrode line.If carry out etching earlier after finishing thin film deposition, the crystal grain particle of film inside is less, is easy to control when etching.Profile to the grid that forms after etching is finished is annealed, and under the high temperature of 900～1100 degree, the defective in the metal silicide is repaired behind atomic rearrangement, and its resistivity also descends to some extent.After finishing the making of grid; form the side wall of protection in gate side; respectively the substrate on grid both sides is mixed and form source electrode and drain electrode and above source electrode, form memory cell capacitor; a pole plate of described electric capacity links to each other with source electrode by contact hole; above drain electrode, form contact hole, and insert metal and link to each other with bit line.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the manufacture method of a semiconductor device is characterized in that, this method comprises:
A Semiconductor substrate is provided;
On described substrate, form silicon oxide layer;
On described silicon oxide layer, form polysilicon layer;
On described polysilicon layer, form metal silicide layer;
On described metal silicide layer, form silicon nitride layer;
The described silicon nitride layer of photoetching and etching, metal silicide layer, polysilicon layer and silicon oxide layer form grid structure;
Etching is finished after described silicon nitride layer, metal silicide layer, polysilicon layer and the silicon oxide layer, and the metal silicide layer to described grid structure under nitrogen environment is carried out annealing process;
Wherein, described annealing temperature is 900～1100 degrees centigrade, and annealing time is 20～30 seconds.
2. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that: described metal silicide layer comprises tungsten silicide (WSix), titanium silicide (TiSix).
3. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that: the thickness of described metal silicide layer is 500～1000 dusts.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, this method further comprises: hydrofluoric acid (HF) and SC1, SC2 with dilution before forming silicon oxide layer clean.
5. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, this method further comprises: clean with hydrofluoric acid (HF) before the plated metal silicide layer.
6. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that: described etching is a dry etching.
7. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that: the thickness of described polysilicon layer is 500～800 dusts.
8. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that: the manufacture method of described polysilicon layer is chemical vapour deposition (CVD).
9. the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that: the thickness of described silicon oxide layer is 50～150 dusts.
10. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that: after described annealing process, further comprise, form side wall at described grid structure sidewall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN200610026761A CN101079376B (en) | 2006-05-22 | 2006-05-22 | Making method for semiconductor part |
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| CN200610026761A CN101079376B (en) | 2006-05-22 | 2006-05-22 | Making method for semiconductor part |
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| CN101079376A CN101079376A (en) | 2007-11-28 |
| CN101079376B true CN101079376B (en) | 2010-05-12 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024691B (en) * | 2009-09-23 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Grid structure forming method |
| CN102446734A (en) * | 2010-10-14 | 2012-05-09 | 上海华虹Nec电子有限公司 | Gate structure and method |
| CN102169828A (en) * | 2011-03-10 | 2011-08-31 | 上海宏力半导体制造有限公司 | Method for forming grid electrode structure |
| CN102810458A (en) * | 2011-05-31 | 2012-12-05 | 无锡华润上华半导体有限公司 | Solution of WSI (tungsten silicide) linear granules |
| CN102820215A (en) * | 2011-06-08 | 2012-12-12 | 上海华虹Nec电子有限公司 | Method for manufacturing grid electrode |
| CN102437037B (en) * | 2011-09-08 | 2014-06-04 | 上海华力微电子有限公司 | Method for effectively reducing water mark defects |
| CN103137449B (en) * | 2011-12-01 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of grid, the manufacture method of transistor |
| CN102693906B (en) * | 2012-06-11 | 2017-03-01 | 上海华虹宏力半导体制造有限公司 | Weaken method, lithographic method and the method, semi-conductor device manufacturing method of sidewall redeposition |
| CN104241103A (en) * | 2013-06-14 | 2014-12-24 | 无锡华润上华科技有限公司 | Method for manufacturing WSI composite gate |
| CN113013323A (en) * | 2019-12-19 | 2021-06-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method thereof and semiconductor device |
| CN112542379B (en) * | 2020-12-09 | 2022-11-08 | 济南晶正电子科技有限公司 | Film patterning process method, composite film and electronic component |
| CN115828842B (en) * | 2023-01-09 | 2023-04-18 | 广州粤芯半导体技术有限公司 | Optimization method of semiconductor device manufacturing process |
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| US6277719B1 (en) * | 1999-11-15 | 2001-08-21 | Vanguard International Semiconductor Corporation | Method for fabricating a low resistance Poly-Si/metal gate |
| CN1540722A (en) * | 2003-10-30 | 2004-10-27 | �Ϻ����ɵ�·�з���������˾ | An improved method for forming a flash memory control gate stacked structure |
| CN1604308A (en) * | 2003-09-30 | 2005-04-06 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing DRAM crystal cell structure by utilizing oxidizing wire clearance walls and back etching |
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| US6221746B1 (en) * | 1998-12-30 | 2001-04-24 | United Microelectronics Corp. | Method for forming a poly gate structure |
| US6277719B1 (en) * | 1999-11-15 | 2001-08-21 | Vanguard International Semiconductor Corporation | Method for fabricating a low resistance Poly-Si/metal gate |
| CN1604308A (en) * | 2003-09-30 | 2005-04-06 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing DRAM crystal cell structure by utilizing oxidizing wire clearance walls and back etching |
| CN1540722A (en) * | 2003-10-30 | 2004-10-27 | �Ϻ����ɵ�·�з���������˾ | An improved method for forming a flash memory control gate stacked structure |
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Non-Patent Citations (1)
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| CN101079376A (en) | 2007-11-28 |
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