CN102820215A - Method for manufacturing grid electrode - Google Patents
Method for manufacturing grid electrode Download PDFInfo
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- CN102820215A CN102820215A CN2011101527615A CN201110152761A CN102820215A CN 102820215 A CN102820215 A CN 102820215A CN 2011101527615 A CN2011101527615 A CN 2011101527615A CN 201110152761 A CN201110152761 A CN 201110152761A CN 102820215 A CN102820215 A CN 102820215A
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- layer
- grid
- silicon
- tungsten
- silicon layer
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 238000000137 annealing Methods 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 3
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000007792 gaseous phase Substances 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- 238000005289 physical deposition Methods 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 82
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 238000000151 deposition Methods 0.000 abstract description 5
- 239000011241 protective layer Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- PBZHKWVYRQRZQC-UHFFFAOYSA-N [Si+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O Chemical compound [Si+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O PBZHKWVYRQRZQC-UHFFFAOYSA-N 0.000 abstract 3
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 11
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a method for manufacturing a grid electrode. The method includes sequentially depositing a grid insulating layer, a polycrystalline silicon layer and a tungsten-silicon layer on a silicon wafer used as a substrate; annealing in a nitrogen environment; depositing a silicon nitrate layer on the tungsten-silicon layer after annealing; performing photoetching and etching to obtain a grid electrode body; and oxidizing side walls of the grid electrode body. By the method, the grid electrode with multiple film layers consists of the polycrystalline silicon layer and the tungsten-silicon layer, and the silicon nitrate layer is formed on the tungsten-silicon layer to be used as a protective layer of the grid electrode, so that the grid electrode is low in resistivity and can be effectively protected. Besides, the tungsten-silicon layer is subjected to heat treatment after being formed, so that partial stress of the tungsten-silicon layer can be released, stress between the tungsten-silicon layer and the silicon nitrate layer can be eliminated, and the problem that films bulge or crack in a follow-up heat treatment process due to stress can be avoided.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of grid making method.
Background technology
In the deep submicron integrated circuit CMOS technology, polysilicon is still as irreplaceable important grid conducting material.Polysilicon need be used as the local interlinkage line as grid simultaneously in circuit.Polysilicon as the local interlinkage line requires to have lower resistance, realizes than low circuit loss and short circuit delay.In integrated circuit technology, in order to obtain the grid interconnection line of low resistivity, generally on polysilicon, make the layer of metal silicide, existing most of process using self-aligned silicide technologies form metal silicide on polysilicon gate.In more existing special process are used, thereby polysilicon gate need be protected by silicon nitride layer and can't adopt self-registered technology to form metal silicide at polysilicon gate; In the middle of existing these special process, form metal silicide in order on polysilicon gate, to make, deposit layer of metal silicide after the polysilicon layer deposit usually, and on metal silicide, form silicon nitride layer, thus form the grid material of low-resistivity.But in the prior art deposit silicon nitride on the metal silicide can since between the double-layer films stress problem can in subsequent heat treatment technology, cause film to heave or split, thereby make product produce defective.
Summary of the invention
Technical problem to be solved by this invention provides a kind of grid making method; Can form the grid of the multilayer film of forming by polysilicon layer and tungsten silicon layer; And on the silicon tungsten layer, be formed with the protective layer of silicon nitride layer as grid, can reduce grid resistivity, and can make grid obtain excellent protection; Can eliminate stress between tungsten silicon layer and the silicon nitride layer, and the film that in subsequent heat treatment technology, causes that can avoid causing by stress heave or split, thereby reduce the defective of grid.
For solving the problems of the technologies described above, grid making method provided by the invention comprises step:
Deposit gate insulation layer, polysilicon layer and tungsten silicon layer successively on step 1, the silicon substrate.
Step 2, said tungsten silicon layer deposit are carried out annealing in process after accomplishing under nitrogen environment.
After step 3, annealing are accomplished on said tungsten silicon layer the deposit silicon nitride layer.
Step 4, said silicon chip is carried out lithographic definition go out area of grid; Etch away area of grid outer said silicon nitride layer, said tungsten silicon layer and said polysilicon layer successively; Form grid at said area of grid, said grid is made up of said tungsten silicon layer and said polysilicon layer and is protected by said silicon nitride layer.
Step 5, the sidewall of said grid is carried out oxidation processes.
Further be improved to, the material of said gate insulation layer is one or more combinations in silicon dioxide, silicon oxynitride, tantalum oxide and the aluminium oxide; The thickness of said gate insulation layer is
Further be improved to; Said polysilicon layer thickness is that said polysilicon layer thickness is
for
optimal selection
Further be improved to; Said tungsten silicon layer adopts sputter mode deposit or adopts the deposit of chemical gaseous phase physical deposition mode; Said tungsten silicon layer thickness is that said tungsten silicon layer is thick to be
for
optimal selection
Further be improved to, the said boiler tube that is annealed in the step 2 is annealed or short annealing.
Further be improved to, the temperature of the said annealing in the step 2 is that 700 ℃～1000 ℃, time are 5 seconds～120 minutes.
Further be improved to, the said oxidation processes in the step 5 adopts furnace oxidation or adopts the short annealing oxidation.
Further be improved to, the temperature of the said oxidation processes in the step 5 is that 700 ℃～1050 ℃, time are 5 seconds～120 minutes.
The inventive method can form the grid of the multilayer film of being made up of polysilicon layer and tungsten silicon layer, and on the silicon tungsten layer, is formed with the protective layer of silicon nitride layer as grid, thereby can form the grid that has lower resistivity, also can obtain excellent protection.The inventive method is through after forming tungsten silicon layer, heat-treat tungsten silicon layer; Tungsten silicon layer release portion stress can be made, thereby stress between tungsten silicon layer and the silicon nitride layer can be eliminated, and can avoid the problem that in subsequent heat treatment technology, causes film to heave or split that causes by stress.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the flow chart of embodiment of the invention method;
Fig. 2-Fig. 7 is the silicon chip generalized section in the manufacturing process of embodiment of the invention method;
Fig. 8 is the defect analysis sketch map of the grid of prior art formation;
Fig. 9 is the defect analysis sketch map of the grid of embodiment of the invention method formation.
Embodiment
As shown in Figure 1 is the flow chart of embodiment of the invention method.To shown in Figure 7, is the silicon chip generalized section in the manufacturing process of embodiment of the invention method like Fig. 2.Embodiment of the invention grid making method comprises step:
Step 1, as shown in Figure 2; Deposit or growth gate insulation layer on the silicon substrate 10; The gate oxide 11 that adopts thermal oxide growth in the embodiment of the invention is as said gate insulation layer, and the thickness of said gate oxide 11 is
As shown in Figure 3; The polysilicon layer 12 of deposit on said gate oxide 11
mixes to said polysilicon layer 12 with injecting through photoetching.
As shown in Figure 4, the tungsten silicon layer 13 through sputter or chemical vapor deposition mode deposit
on said polysilicon layer 12.
The deposit of step 2, said tungsten silicon layer 13 is annealed in 700 ℃～1000 ℃ nitrogen atmosphere after accomplishing, and the short annealing mode is adopted in the said annealing of the embodiment of the invention, and the time of short annealing is 10 seconds～100 seconds, and the best is 10～30 seconds; Perhaps, boiler tube annealing is adopted in the said annealing of the embodiment of the invention, and the time of said boiler tube annealing is 5 minutes～120 minutes, and the best is 10 minutes～30 minutes.
Step 3, as shown in Figure 5; The thick silicon nitride layer 14 of deposit one deck on said tungsten silicon layer 13
; The optimum value of the thickness of said silicon nitride layer 14 is
, and said silicon nitride layer 14 adopts the deposits of PECVD mode, and deposition temperature is that 350 ℃～450 ℃, deposition pressure are 1 holder～5 holders.Perhaps, said silicon nitride layer 14 adopts the deposit of LPCVD mode, and deposition temperature is 600 ℃～850 ℃, and pressure is 0.1 holder～2 holders.
Step 4, as shown in Figure 6; Said silicon chip 10 is carried out lithographic definition go out area of grid; Etch away area of grid outer said silicon nitride layer 14, said tungsten silicon layer 13 and said polysilicon layer 12 successively; Form grid at said area of grid, the said tungsten silicon layer 152 of said grid after by etching formed with said polysilicon layer 151 and protected by said silicon nitride layer 153.
Step 5, as shown in Figure 7; Said grid is carried out sidewall oxidation; And formation sidewall oxide 154; The thickness of said sidewall oxide 154 is
, and said sidewall oxide 154 adopts the short annealing oxidation to form; Temperature is 950 ℃～1050 ℃, and the time is 5 seconds～30.Perhaps, said sidewall oxide 154 adopts furnace oxidation, and temperature is 800 ℃～950 ℃, and the time is 1 minute～100 minutes.
Form manufacturing approach in the prior art by the grid of forming by polysilicon layer and tungsten silicon layer of silicon nitride layer protection; The inventive method is through after forming tungsten silicon layer, heat-treat tungsten silicon layer; Tungsten silicon layer release portion stress can be made, thereby stress between tungsten silicon layer and the silicon nitride layer can be eliminated, and can avoid the problem that in subsequent heat treatment technology, causes film to heave or split that causes by stress.As shown in Figure 8, be the defect analysis sketch map of the grid of prior art formation; Can find out because the stress problem between tungsten silicon layer and the silicon nitride layer has caused more defective.As shown in Figure 9, be the defect analysis sketch map of the grid of embodiment of the invention method formation; The defective of the grid that the inventive method forms significantly reduces.
More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Claims (10)
1. a grid making method is characterized in that, comprises step:
Deposit gate insulation layer, polysilicon layer and tungsten silicon layer successively on step 1, the silicon substrate;
Step 2, said tungsten silicon layer deposit are carried out annealing in process after accomplishing under nitrogen environment;
After step 3, annealing are accomplished on said tungsten silicon layer the deposit silicon nitride layer;
Step 4, said silicon chip is carried out lithographic definition go out area of grid; Etch away said area of grid outer said silicon nitride layer, said tungsten silicon layer and said polysilicon layer successively; Form grid at said area of grid, said grid is made up of said tungsten silicon layer and said polysilicon layer and is protected by said silicon nitride layer;
Step 5, the sidewall of said grid is carried out oxidation processes.
2. grid making method according to claim 1, it is characterized in that: the material of said gate insulation layer is one or more combinations in silicon dioxide, silicon oxynitride, tantalum oxide and the aluminium oxide; The thickness of said gate insulation layer is
3. grid making method according to claim 1, it is characterized in that: said polysilicon layer thickness is
4. like the said grid making method of claim 3, it is characterized in that: said polysilicon layer thickness is
5. grid making method according to claim 1; It is characterized in that: said tungsten silicon layer adopts sputter mode deposit or adopts the deposit of chemical gaseous phase physical deposition mode, and said tungsten silicon layer thickness is
6. like the said grid making method of claim 5, it is characterized in that: said tungsten silicon layer is thick to be
7. grid making method according to claim 1 is characterized in that: said in the step 2 is annealed into boiler tube annealing or short annealing.
8. grid making method according to claim 1 is characterized in that: the temperature of the said annealing in the step 2 is that 700 ℃～1000 ℃, time are 5 seconds～120 minutes.
9. grid making method according to claim 1, it is characterized in that: the said oxidation processes in the step 5 adopts furnace oxidation or adopts the short annealing oxidation.
10. grid making method according to claim 1 is characterized in that: the temperature of the said oxidation processes in the step 5 is that 700 ℃～1050 ℃, time are 5 seconds～120 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101527615A CN102820215A (en) | 2011-06-08 | 2011-06-08 | Method for manufacturing grid electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101527615A CN102820215A (en) | 2011-06-08 | 2011-06-08 | Method for manufacturing grid electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102820215A true CN102820215A (en) | 2012-12-12 |
Family
ID=47304260
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101527615A Pending CN102820215A (en) | 2011-06-08 | 2011-06-08 | Method for manufacturing grid electrode |
Country Status (1)
| Country | Link |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333251B1 (en) * | 1999-08-17 | 2001-12-25 | Samsung Electronics Co., Ltd. | Method of fabricating gate structure of semiconductor device for repairing damage to gate oxide layer |
| CN101079376A (en) * | 2006-05-22 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Making method for semiconductor part |
| CN101165859A (en) * | 2006-10-20 | 2008-04-23 | 茂德科技股份有限公司 | Method for reducing stress between conductive layer and mask layer and method for manufacturing grid |
-
2011
- 2011-06-08 CN CN2011101527615A patent/CN102820215A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333251B1 (en) * | 1999-08-17 | 2001-12-25 | Samsung Electronics Co., Ltd. | Method of fabricating gate structure of semiconductor device for repairing damage to gate oxide layer |
| CN101079376A (en) * | 2006-05-22 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Making method for semiconductor part |
| CN101165859A (en) * | 2006-10-20 | 2008-04-23 | 茂德科技股份有限公司 | Method for reducing stress between conductive layer and mask layer and method for manufacturing grid |
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| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140103 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20140103 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20121212 |