CN101009478A - Differential signal receiver - Google Patents
Differential signal receiver Download PDFInfo
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- CN101009478A CN101009478A CNA200710008349XA CN200710008349A CN101009478A CN 101009478 A CN101009478 A CN 101009478A CN A200710008349X A CNA200710008349X A CN A200710008349XA CN 200710008349 A CN200710008349 A CN 200710008349A CN 101009478 A CN101009478 A CN 101009478A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45612—Indexing scheme relating to differential amplifiers the IC comprising one or more input source followers as input stages in the IC
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45652—Indexing scheme relating to differential amplifiers the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45696—Indexing scheme relating to differential amplifiers the LC comprising more than two resistors
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Abstract
A differential signal receiver according to the present invention includes a waveform shaping circuit selectively outputting an upper limit value having a first potential difference from a first power supply potential, and a lower limit value having a second potential difference from the upper limit value, from a first and a second output terminals according to a differential signal input, and an amplifier comparing voltages of the first and the second output terminals and outputting one of a voltage almost the same as the first power supply potential or a voltage almost the same as a second power supply potential.
Description
Technical field
The present invention relates to a kind of differential signal receiver, and especially relate to and be used to receive the differential signal receiver of differential clock signal and differential data signals by a small margin.
Background technology
Slim and flat-panel monitor low-power consumption is the main flow of PC (personal computer) and televimonitor.Panel of LCD as the flat-panel monitor principal mode is developed fast, and wishes to improve the number of display device and valid pixel.The liquid display panel converts aanalogvoltage to so that it is applied on the liquid crystal apparatus by the digital signal data that will be imported, comes display frame.Along with the number of pixel and valid pixel has increased, must the digital signal data of input be transmitted quickly.Therefore, by using data transport standard, come actual figure reportedly to send such as the such differential signal by a small margin of RSDS (reducing swing difference signal) and miniLVDS (low-voltage differential signal).Therefore, at the display driver that is used for carrying out data processing, need receiver to convert the amplitude of the primary differential signal sub-signal data of input to internal logic voltage.
Fig. 5 has provided the block diagram of general liquid crystal panel.Panel of LCD comprises display control unit 101, power circuit 102, source electrode driver 103, gate drivers 104 and TFT-LCD (thin-film transistor-LCD) 105.Display controller device 101 offers source electrode driver 103 and gate drivers 104 with the video data and the control signal of input.Power circuit 102 is incorporated in the display controller device 101, to provide reference voltage to source electrode driver 103 and gate drivers.
Fig. 6 has provided the interior block diagram of the source electrode driver 103 that is used to receive video data.For example, video data is the data that are used to represent colour information.Come described video data is transmitted by differential signal by a small margin.Source drive 103 utilizes receiver 110 to receive video data, and converts differential signal to single-ended signal.This single-ended signal and control signal are converted to analog signal from digital signal in internal logic circuit 111.
In addition, owing to the manufacturing tolerance limit in the transmission fluctuates, reflects and noise, and make the voltage and the amplitude fluctuation of video data.This makes the signal of receiver output that fluctuation time of delay take place, and is used in the duty ratio reduction of expression waveform high-low level ratio.In the open No.2003-198265 (first conventional art) of Japanese Unexamined Patent Application, disclosed the receiver that is used to improve this fluctuation.
Fig. 7 has provided the block diagram according to the receiver of first conventional art.In the receiver of first conventional art, the DC level of the differential signal that will receive by input A and B in DC level transducer 121 is carried out level and is moved, by first order amplifier 122 (gain G 1), second level amplifier 123 (gain G 2) and third level amplifier 124 (gain G 3) it is amplified again, in third level amplifier, convert differential signal to single-ended signal then, and after this export this single-ended signal from output circuit.Fig. 8 has provided the detailed circuit diagram of this receiver.
As shown in Figure 8, DC level transducer 121 comprises respectively nmos pass transistor QN1 and the QN2 that links to each other with B with input A.The drain electrode of nmos pass transistor QN1 and QN2 links to each other with electrical source voltage VDD, and current source I1 and I2 are connected between source electrode and the earth potential GND.The source electrode of nmos pass transistor QN1 and QN2 exported with respectively from differential signal INa and the corresponding internal output enable signal int_OUTa of INb and the int_OUTb of input A and B input.The DC level of internal output enable signal int_OUTa and int_OUTb is the value that the DC level Vcm of differential signal INa and INb deducts threshold voltage Vgs.Fig. 9 A has provided the signal waveform of input signal, and Fig. 9 B has provided the signal waveform of the output signal of DC level transducer 121.Shown in Fig. 9 A and 9B, differential signal INa and INb are that the center is that DC level Vcm, high level voltage are that VH, low level voltage are the signal of VL, and wherein amplitude VIN represents the voltage difference between VH and the VL.In addition, the internal output enable signal int_OUTa and the int_OUTb of 121 outputs of DC level transducer have the amplitude that the center is the VIN of current level Vcm-Vgs.
Signal is amplified by casacade multi-amplifier according to the receiver of first conventional art and can reduce the time of delay of signal in receiver, even the amplitude fluctuation of differential signal.
Yet in the receiver of first conventional art, if the DC level Vcm of input signal moves to the side of supply voltage VDD or the amplitude VIN of input signal has increased, the magnitude of current that flows to nmos pass transistor QN3 or QN4 has so increased, thereby can improve the threshold voltage Vgs of nmos pass transistor QH5 and QN6 and the time of delay that can reduce receiver.
On the other hand, if the DC level Vcm of input signal moves to the side of earth potential GND or the amplitude VIN of input signal has reduced, the magnitude of current that flows to nmos pass transistor QN3 or QN4 has so reduced, thereby the threshold voltage Vgs of nmos pass transistor QN5 and QN6 has been reduced and increased the time of delay of receiver.
In addition, owing to represent the lower limit of input range of the DC level Vcm of input signal,, must be Vlimit1＞Vgs＜Vgs (QN1)+Vgs (QN3)-(VIN/2) therefore for receiver is operated by Vlimit.Under the situation of Vgs=1V and VIN=2QOrriV, Vlimit＞(1+1-(0.2/2))=1.9V.Therefore receiver can not be operated with the DC level Vcm that input signal is less than or equal to 1.9V.
Therefore in the receiver according to first conventional art, whether also whether the amplitude of now having found input signal or DC level fluctuate and fluctuation time of delay of signal.In addition, have another problem, if promptly the DC level of input signal is lower than the lower limit of input range of the DC level of input signal, receiver is not operated so.
Summary of the invention
According to the present invention, a kind of like this differential signal receiver is provided, this differential signal receiver comprises: wave forming circuit is used for according to differential signal input and exports selectively with first electrical source voltage from first and second outputs and to differ the higher limit of first electrical potential difference and to differ the lower limit of second electrical potential difference with higher limit; And amplifier, be used for voltage to first and second outputs and compare and export almost identical voltage or almost identical voltage one with the second source electromotive force with first electrical source voltage.
According to differential signal receiver of the present invention, the higher limit of the differential signal of wave forming circuit output becomes first electrical source voltage (for example electrical source voltage VDD), and the amplitude of first electrical potential difference equates with second electrical potential difference (for example earth potential GND).Therefore the DC level and the amplitude of the differential signal of wave forming circuit output do not depend on DC level and the amplitude that is input on it.In addition, the differential signal of wave forming circuit output becomes very stable, and this does not depend on the fluctuation of input differential signal.In addition, because having the output signal of the wave forming circuit of stable DC level and amplitude, the amplifier basis operates, therefore exportable stable single-ended signal.
Description of drawings
Can more conspicuously learn above-mentioned and other purposes, advantage and feature of the present invention from following description in conjunction with the accompanying drawings, wherein:
Fig. 1 has provided the circuit diagram according to the differential signal amplifier of the first embodiment of the present invention;
Fig. 2 A has provided the view according to the waveform of the input signal of first embodiment of the invention;
Fig. 2 B has provided the view according to the waveform of the internal output enable signal of first embodiment of the invention;
Fig. 3 has provided the circuit diagram according to the differential signal amplifier of second embodiment;
Fig. 4 has provided the circuit diagram according to the differential signal amplifier of third embodiment of the invention;
Fig. 5 has provided the block diagram of general liquid crystal panel;
Fig. 6 has provided the block diagram of general source electrode driver;
Fig. 7 has provided the block diagram according to the differential signal amplifier of first conventional art;
Fig. 8 has provided the circuit diagram according to the differential signal amplifier of first conventional art;
Fig. 9 A has provided the view according to the waveform of the input signal of first conventional art; And
Fig. 9 B has provided the view according to the waveform of the internal output terminal of first conventional art.
Embodiment
Here present invention is described with reference to an illustrative embodiment now.The instruction of the present invention that is to use that those of ordinary skills can understand can realize that many alternative embodiments and the present invention have been not limited to the illustrated embodiment of explanatory purpose.
First embodiment
With reference to the accompanying drawings embodiments of the invention are described hereinafter.Differential signal receiver 1 is imported differential signal by a small margin and is exported significantly single-ended signal.The amplitude of input differential signal approximately is 0.2V (low level: 0.8V and a high level: 1.0V) or 0.6V (low level: 0.2V and high level: 0.8V).In addition, the single-ended signal of output has the amplitude of the electrical potential difference between first power supply (for example electrical source voltage VDD) and the second source electromotive force (for example earth potential GND).Fig. 1 has provided the circuit diagram according to the differential signal receiver 1 of first embodiment.
As shown in Figure 1, differential signal receiver 1 comprises wave forming circuit 10, amplifier 11 and output control circuit 12.From the first output output signal, this signal has the lower limit that the upper limit that electrical source voltage VDD deducts first electrical potential difference and the upper limit deduct second differential potential to wave forming circuit 10 according to input differential signal.Wave forming circuit 10 is also from the second output output signal, and this signal has the signal upper and lower bound much at one with the output of first output.The voltage of 11 pairs first and second outputs of amplifier compares and exports the electrical potential difference single-ended signal much at one between its amplitude and electrical source voltage VDD and the earth potential GND.Output control circuit 12 controls are that the output of pair amplifier 11 transmits or export earth potential GND.Hereinafter this circuit is described in detail.
Input A links to each other with the grid of Nch depletion mode transistor M1.Input B links to each other with the grid of Nch depletion mode transistor M2.Nch depletion mode transistor M1 has formed the public differential pair that is connected of source electrode with M2.The points of common connection of source electrode links to each other with the drain electrode of Nch enhancement transistor M3.The source electrode of Nch enhancement transistor links to each other with earth potential GND.Current controling signal VCTRL links to each other with the grid of Nch enhancement transistor M3.Nch enhancement transistor M3 is according to the magnitude of voltage output current I1 of current controling signal VCTRL.
A terminal of resistance R 1 links to each other with the drain electrode of Nch depletion mode transistor M1.For Nch depletion mode transistor M1, according to the input signal that is input to input A, tie point becomes first output and exports first output signal (for example internal output enable signal int_OUTa).A terminal of resistance R 2 links to each other with the drain electrode of Nch depletion mode transistor M2.This tie point is second output.Nch depletion mode transistor M2 exports second output signal (for example internal output enable signal int_OUTb) according to being input to the input signal of input B from second output.The public connection of another terminal of another terminal of resistance R 1 and resistance R 2.Resistance R 3 is connected between points of common connection and the electrical source voltage VDD.
Pch enhancement transistor M7 and M8 have formed current mirroring circuit.The source electrode of Pch enhancement transistor M7 and M8 links to each other with supply voltage VDD.The source electrode of Pch enhancement transistor M7 links to each other with the drain electrode of Nch enhancement transistor M4.The grid of Pch enhancement transistor M7 and M8 is connected with each other, and links to each other with the source electrode of Pch enhancement transistor M7.
Pch enhancement transistor M9 and M10 have formed current mirroring circuit.The source electrode of Pch enhancement transistor M9 and M10 links to each other with supply voltage VDD.The source electrode of Pch enhancement transistor M9 links to each other with the drain electrode of Nch enhancement transistor M5.The grid of Pch enhancement transistor M9 and M10 is connected with each other and links to each other with the source electrode of Pch enhancement transistor M9.
Pch enhancement transistor M11 and M12 have formed current mirroring circuit.The source electrode of Pch enhancement transistor M11 and M12 links to each other with earth potential GND.The source electrode of Pch enhancement transistor M11 links to each other with the drain electrode of Nch enhancement transistor M10.The grid of Pch enhancement transistor M11 and M12 is connected with each other and links to each other with the source electrode of Pch enhancement transistor M11.In addition, the drain electrode of Nch enhancement transistor M12 links to each other with the drain electrode of Pch enhancement transistor M8.Export the 3rd output signal (for example internal output enable signal int_OUTc) from this tie point.
Operation to the differential signal receiver 1 of first embodiment is described hereinafter.Fig. 2 A has provided the differential signal INa that is input to differential signal receiver 1 and the waveform of 1Mb.Shown in Fig. 2 A, differential signal INa and INb are the clock signals of paraphase each other.The high level voltage of differential signal is called VH, low level voltage is called VL, and DC level is called Vcm.
Be that the signal level of high level voltage VH and the differential signal INb that is input to input B is that the situation of low level voltage VL describes in detail to the signal level of the differential signal INa that is input to input A hereinafter.In this case, Nch depletion mode transistor M1 becomes conducting, and Nch depletion mode transistor M2 becomes not conducting.Therefore electric current I 1 flows to Nch depletion mode transistor M1.This can produce pressure drop V3 at resistance R 3 two ends, this pressure drop V3 is V3=R3 * I1.At the two ends of resistance R 1, produced pressure drop V1 by resistance R 1 and electric current I 1, this pressure drop V1 is V1=R1 * I1.For resistance R 2, can not produce pressure drop on the other hand, because electric current I 1 does not flow therein at the two ends of resistance R 2.Therefore the signal level Vint_Outa of internal output enable signal int_OUTa is Vint_OUTa=VDD-V3-V1.In addition, the signal level Vint_OUTb of internal output enable signal int_OUTb can be expressed as Vint_OUTb=VDD-V3.
Be that the signal level of low level voltage VL and the differential signal INb that is input to input B is that the situation of high level voltage VH describes in detail to the level signal of the differential signal INa that is input to input A hereinafter.In this case, Nch depletion mode transistor M1 become not conducting and Nch depletion mode transistor M2 become conducting.Therefore electric current I 1 flows to Nch depletion mode transistor M2.This can produce pressure drop V3 at the two ends of resistance R 3, and this pressure drop V3 is V3=R3 * I1.In addition, at the two ends of resistance R 2, produce pressure drop V2 by resistance R 2 and electric current I 1, this pressure drop V2 is V2=R2 * I1.For resistance R 1, do not produce pressure drop on the other hand, because electric current I 1 does not flow therein at the two ends of resistance R 1.Therefore the signal level Vint_OUTa of internal output enable signal int_OUTa can be expressed as Vint_OUTa=VDD-V3.In addition, the signal level Vint_OUTb of internal output enable signal int_OUTb can be expressed as Vint_OUTb=VDD-V3-V2.If the resistance value of resistance R 1 and R2 much at one, voltage VI and V2 become substantially the same voltage so.Therefore, the signal level Vint_OUTb of internal output enable signal int_OUTb can be expressed as Vint_OUTb=VDD-V3-V1.
Therefore, wave forming circuit 10 has high level voltage VH '=VDD-V3 and low level voltage VL '=VDD-V3-V1 according to input differential signal INa and INb, and the internal output enable signal int_OUTa and the int_OUTb of output difference operation.The DC level Vcm ' of internal output enable signal int_OUTa and int_OUTb is Vcm '=VDD-V3-(V1/2).Fig. 2 B has provided the waveform of internal output enable signal.
If internal output enable signal int_OUTa is greater than internal output enable signal int_OUTb in amplifier 11, so Nch enhancement transistor M5 become conducting and Nch enhancement transistor M4 become not conducting.Therefore electric current 12 flows to Nch enhancement transistor M12 by the current mirroring circuit that formed by Pch enhancement transistor M9 and M10 and by the current mirroring circuit that Nch enhancement transistor M11 and M12 form.Therefore Nch enhancement transistor M12 becomes conducting.On the other hand, because electric current 12 does not flow to Nch enhancement transistor M4, therefore the current mirroring circuit that is formed by Pch enhancement transistor M7 and M8 does not have electric current to flow through.Therefore Pch enhancement transistor M8 becomes not conducting.Therefore, the signal level Vint_OUTc of the internal output enable signal int_QUTc in the amplifier 11 becomes almost identical with earth potential GND.
If internal output enable signal int_OUTa is less than internal output enable signal int_OUTb in amplifier 11, that Nch enhancement transistor M4 becomes conducting and Nch enhancement transistor M5 becomes not conducting.Therefore current mirroring circuit that is formed by Pch enhancement transistor M9 and M10 and the current mirroring circuit that is formed by Nch enhancement transistor M11 and M12 do not have electric current to flow through.Therefore Nch enhancement transistor M12 becomes not conducting.Flow to Nch enhancement transistor M4 because of electric current I 2 on the other hand, so electric current I 2 flows to P type MOS transistor M8 by the current mirror that is formed by Pch enhancement transistor M7 and M8.Therefore Pch enhancement transistor M8 becomes conducting.Therefore, the signal level Vint_OUTc of the internal output enable signal int_OUTc of amplifier 11 become with electrical source voltage VDD much at one.
By making output control signal EN effective, output control circuit 12 is exported internal output enable signal int_OUTc by NAND circuit 13 and phase inverter 14.By making output control signal EN invalid, output control circuit 12 makes the electrical source voltage VDD voltage paraphase much at one of being exported with NAND circuit 13 by phase inverter 14 in addition.
As described hereinbefore, the wave forming circuit 10 of this embodiment comprises by the set DC level of supply voltage VDD resistance R 1 to R3 and electric current I 1, and irrelevant with the DC level Vcm of the differential signal INa of input and INb.Therefore the DC level that is input to the internal output enable signal int_OUTa of amplifier 11 and int_OUTb does not depend on the differential signal INa that is input to wave forming circuit 10 and the DC level of INb.
Therefore the operation of amplifier 11 always has equal state and irrelevant with the DC level of differential signal INa that is input to wave forming circuit 10 and INb.Therefore become very stable and irrelevant the time of delay of the internal output enable signal Vint_OUTc by amplifier 11 outputs with the DC level of differential signal INa that is input to wave forming circuit 10 and INb.
In addition, identical with first embodiment, by the resistance value of resistance R 1 and R2 and the electric current I 1 that offers by Nch depletion mode transistor M1 and the formed differential pair of M2 the internal output enable signal int_OUTa of wave forming circuit 10 and the amplitude of int_OUTb are set.According to the differential signal of input, Nch depletion mode transistor M1 and M2 operate as switch.Therefore can not fluctuate by set internal output enable signal int_OUTa of electric current I 1 and resistance R 1 and R2 and the amplitude of int_OUTb, even the DC level of the differential signal of input or amplitude fluctuation.Therefore the time of delay of wave forming circuit 10 is very stable.In the receiver of first conventional art, fluctuate along with the fluctuation of the DC level of the differential signal that is input to DC converter 121 time of delay on the other hand.
In addition, the electric current I 1 that wave forming circuit 10 is exported by a current source is provided with the power-on and power-off potential difference of amplitude, so the duty ratio of internal output enable signal int_OUTa and int_OUTb is 50% (ratio that is the high-low level ratio is identical) basically.In addition, the duty ratio of internal output enable signal int_OUTc becomes and is essentially 50%, because amplifier 11 can be that 50% internal output enable signal int_OUTa and int_OUTb operate according to having duty ratio.
As described hereinbefore, the differential signal receiver 1 of this embodiment can stably and with the duty ratio of high accuracy be carried out.
On the other hand, because the wave forming circuit of this embodiment 10 is by receiving differential signal by Nch depletion mode transistor M1 and the formed differential pair of M2, so wave forming circuit 10 comprises very wide input voltage range.For example, the VH that supposes the differential signal that is input to wave forming circuit 10 is that 0.8V, VL are that 1.0V, amplitude are 200mV, the threshold voltage Vgs=0V of Nch depletion mode transistor M1 and M2 and the saturation voltage Vdssat=0.2V of Nch enhancement transistor M1 and M2, the DC level that is input to the differential signal of wave forming circuit 10 so is Vcm=Vgsf+Vdssat=0.2V.The DC level Vcm of input signal that requires to be input to receiver on the other hand is more than or equal to 1.9V.
Second embodiment
The wave forming circuit 20 of second embodiment comprises that diode connection Nch enhancement transistor M13 is to be provided with equipment as first electrical potential difference.Nch enhancement transistor M13 has the grid and the drain electrode of connection, and drain electrode further links to each other with electrical source voltage VDD.In addition, the source electrode of Nch enhancement transistor M13 links to each other with the points of common connection of resistance R 1 and R2.
When using diode connection Nch enhancement transistor M13 as first electrical potential difference equipment to be set, the high level voltage VH ' of internal output enable signal int_OUTa and int_OUTb is VH '=VDD-Vgs[M13].On the other hand, the low level voltage VL ' of internal output enable signal int_OUTa and int_OUTb is VL '=VDD-Vgs[M13]-V1.Vgs[M13] be the threshold voltage of Nch enhancement transistor M13.The DC level Vcm ' of internal output enable signal int_OUTa and int_OUTb is Vcm '=VDD-Vgs[M13 in addition]-(V1/2).
Identical with first embodiment, the resistance value by resistance R 1 and R2 and offer the amplitude that internal output enable signal int_OUTa and int_OUTb are set by the electric current I 1 of Nch depletion mode transistor M1 and the formed differential pair of M2.In addition, according to the differential signal of input, the Nch depletion mode transistor M1 and the M2 of the wave forming circuit 20 of second embodiment operate as switch.Yet even the DC level of differential signal of input or amplitude fluctuation, the size of electric current I 1 that flows to Nch enhancement transistor M13 is also constant.Therefore can not fluctuate by set internal output enable signal int_OUTa of electric current I 1 and resistance R 1 or R2 and the amplitude of int_OUTb.Therefore the time of delay of wave forming circuit 20 is very stable.
In addition, equipment is set, compares with the situation of using resistance and can reduce the layout zone by utilizing the Nch enhancement transistor to form first electrical potential difference.
The 3rd embodiment
In the differential signal receiver 1 of second embodiment, second electrical potential difference that resistance R 1 and R2 are used for wave forming circuit 20 is provided with equipment.Yet diode connection Nch enhancement transistor M14 and M15 are used for second electrical potential difference of wave forming circuit 30 of the differential signal receiver 3 of the 3rd embodiment is provided with equipment.Fig. 4 has provided the differential signal receiver 3 of the 3rd embodiment.In Fig. 4, reference number is represented the parts identical with second embodiment, and saves detailed description thereof.
The wave forming circuit 30 of the 3rd embodiment comprises and is used for diode connection Nch enhancement transistor M14 and the M15 that second electrical potential difference is provided with equipment.Nch enhancement transistor M14 and M15 have grid and the drain electrode that is connected with each other.In addition, drain electrode is public links to each other and links to each other with the source electrode of Nch enhancement transistor M13.The source electrode of Nch enhancement transistor M14 links to each other with the drain electrode of Nch depletion mode transistor M1.The source electrode of Nch enhancement transistor M15 links to each other with the drain electrode of Nch depletion mode transistor M2.Preferably form the Nch enhancement transistor M14 and the M15 of same size.Because transistor size is identical and to flow to the transistorized magnitude of current identical, so threshold voltage also becomes identical.
When using diode connection Nch enhancement transistor M14 and M15 to be used for second electrical potential difference equipment is set, the high level voltage VH ' of internal output enable signal int_OUTa and int_OUTb is VH '=VDD-Vgs[M13].On the other hand, the low level voltage VL ' of internal output enable signal int_OUTa and int_OUTb is VL '=VDD-Vgs[M13]-Vgs[M14].Vgs[M14] be the threshold voltage of Nch enhancement transistor M14, the threshold voltage Vgs[M15 of itself and Nch enhancement mode] basic identical.In addition, the DC level Vcm ' of internal output enable signal int_OUTa and int_OUTb is Vcm '=VDD-Vgs[M13]-(Vgs[M14]/2).
Threshold voltage by Nch enhancement transistor M14 (or M15) is provided with the internal output enable signal int_OUTa of wave forming circuit 30 and the amplitude of int_OUTb.According to the differential signal of input, the Nch depletion mode transistor M1 and the M2 of the wave forming circuit 30 of the 3rd embodiment operate as switch.Even yet the DC level or the amplitude fluctuation of differential signal of input, the size of electric current I 1 that flows to Nch enhancement transistor M13 is also constant.Therefore can not fluctuate by set internal output enable signal int_OUTa of Nch enhancement transistor M14 (or M15) and the amplitude of int_OUTb.Therefore the time of delay of wave forming circuit 20 is very stable.
By utilizing the Nch enhancement transistor to form second electrical potential difference equipment is set, compares with the situation of using resistance and can reduce the layout zone.
In the above-described embodiments, can remove first electrical potential difference equipment is set, and the higher limit of the internal output enable signal of wave forming circuit output can be an electrical source voltage.In the above-described embodiments, use the differential pair that forms by the Nch depletion mode transistor, however differential pair also but form by the Pch depletion mode transistor.
It is apparent that the present invention is not limited to the foregoing description and under situation about not departing from the scope of the present invention with spirit, can make amendment and change it.
Claims (6)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006-018842 | 2006-01-27 | ||
| JP2006018842A JP4851192B2 (en) | 2006-01-27 | 2006-01-27 | Differential signal receiver |
| JP2006018842 | 2006-01-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101009478A true CN101009478A (en) | 2007-08-01 |
| CN101009478B CN101009478B (en) | 2010-10-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710008349XA Expired - Fee Related CN101009478B (en) | 2006-01-27 | 2007-01-29 | Differential signal receiver |
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| US (1) | US7675323B2 (en) |
| JP (1) | JP4851192B2 (en) |
| CN (1) | CN101009478B (en) |
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| CN105576967B (en) * | 2014-10-11 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | Voltage up converting circuit |
| CN104901683B (en) * | 2015-04-28 | 2017-10-20 | 灿芯半导体(上海)有限公司 | Signal receiving circuit |
| JP6886355B2 (en) * | 2017-06-22 | 2021-06-16 | ローム株式会社 | Operational amplifier and DC / DC converter using it |
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| US4754169A (en) * | 1987-04-24 | 1988-06-28 | American Telephone And Telegraph Company, At&T Bell Laboratories | Differential circuit with controllable offset |
| US4918336A (en) * | 1987-05-19 | 1990-04-17 | Gazelle Microcircuits, Inc. | Capacitor coupled push pull logic circuit |
| JPH01223807A (en) * | 1988-03-02 | 1989-09-06 | Matsushita Electric Ind Co Ltd | Output circuit |
| JPH05304426A (en) * | 1991-07-04 | 1993-11-16 | Ricoh Co Ltd | Semiconductor device |
| JPH07226557A (en) * | 1994-02-15 | 1995-08-22 | Hitachi Ltd | Electronic circuit and semiconductor device using the same |
| JP2798020B2 (en) * | 1995-10-25 | 1998-09-17 | 日本電気株式会社 | Semiconductor integrated circuit |
| JP3435292B2 (en) * | 1996-08-29 | 2003-08-11 | 富士通株式会社 | Operational amplifier circuit |
| JP3157746B2 (en) * | 1997-06-30 | 2001-04-16 | 日本電気アイシーマイコンシステム株式会社 | Constant current circuit |
| KR100290285B1 (en) * | 1999-01-13 | 2001-05-15 | 윤종용 | Input buffer of prescaler |
| KR100393226B1 (en) * | 2001-07-04 | 2003-07-31 | 삼성전자주식회사 | Internal reference voltage generator capable of controlling value of internal reference voltage according to temperature variation and internal power supply voltage generator including the same |
| JP2003198265A (en) | 2001-12-25 | 2003-07-11 | Seiko Epson Corp | Differential signal receiving circuit |
| JP3737058B2 (en) * | 2002-03-12 | 2006-01-18 | 沖電気工業株式会社 | Analog addition / subtraction circuit, main amplifier, level identification circuit, optical reception circuit, optical transmission circuit, automatic gain control amplification circuit, automatic frequency characteristic compensation amplification circuit, and light emission control circuit |
| KR100480916B1 (en) * | 2002-10-30 | 2005-04-07 | 주식회사 하이닉스반도체 | Input buffer circuit for reducing current of SSTL interface input device |
| US7061273B2 (en) * | 2003-06-06 | 2006-06-13 | Rambus Inc. | Method and apparatus for multi-mode driver |
| JP3827654B2 (en) * | 2003-06-23 | 2006-09-27 | 株式会社 沖マイクロデザイン | Operational amplifier |
| KR100616501B1 (en) * | 2004-07-27 | 2006-08-25 | 주식회사 하이닉스반도체 | receiver |
| US7446576B2 (en) * | 2005-09-30 | 2008-11-04 | Slt Logics, Llc | Output driver with slew rate control |
-
2006
- 2006-01-27 JP JP2006018842A patent/JP4851192B2/en not_active Expired - Fee Related
-
2007
- 2007-01-23 US US11/656,533 patent/US7675323B2/en not_active Expired - Fee Related
- 2007-01-29 CN CN200710008349XA patent/CN101009478B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105765859A (en) * | 2013-11-28 | 2016-07-13 | ams有限公司 | Amplifier arrangement |
| CN105765859B (en) * | 2013-11-28 | 2019-02-12 | ams有限公司 | Amplifier installation |
| CN105321945A (en) * | 2014-05-30 | 2016-02-10 | 德克萨斯仪器股份有限公司 | Trench mosfet having reduced gate charge |
| CN105321945B (en) * | 2014-05-30 | 2020-12-25 | 德克萨斯仪器股份有限公司 | Trench MOSFET with reduced gate charge |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007201879A (en) | 2007-08-09 |
| CN101009478B (en) | 2010-10-06 |
| US7675323B2 (en) | 2010-03-09 |
| JP4851192B2 (en) | 2012-01-11 |
| US20070188230A1 (en) | 2007-08-16 |
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