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JPH05304426A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05304426A
JPH05304426A JP16454291A JP16454291A JPH05304426A JP H05304426 A JPH05304426 A JP H05304426A JP 16454291 A JP16454291 A JP 16454291A JP 16454291 A JP16454291 A JP 16454291A JP H05304426 A JPH05304426 A JP H05304426A
Authority
JP
Japan
Prior art keywords
input
voltage
amplifier circuit
differential amplifier
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16454291A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Naka
剛志 仲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP16454291A priority Critical patent/JPH05304426A/en
Publication of JPH05304426A publication Critical patent/JPH05304426A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To make it possible to constitute a circuit where the range of common mode input voltage is VDD to VSS in normal power supply voltage by using a depression type MOSFET for an input transistor in a loop-back type differential amplifier circuit. CONSTITUTION:A depression type MOSFET is used for input transistors Tr11, Tr12. As a result, the Tr11, Tr12 are not turned off even when the voltage of an input 1 and an input 2 is in the vicinity of VSS. The voltage is not limited even when the voltage of the input 1 and the input 2 is in the vicinity of VDD. Therefore, the common mode input voltage of a differential amplifier circuit is possible to be made VDD to VSS.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、折り返しカスケード
(Folded Cascade)型差動増幅回路を構成する半導体
装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which constitutes a folded cascade type differential amplifier circuit.

【0002】[0002]

【従来の技術】従来の代表的な差動増幅回路を図3及び
図4に示す。ここで使用されているトランジスタのう
ち、図4のTr1及びTr2はデプレッション型トランジ
スタ、他は全てエンハンスメント型トランジスタであ
る。
2. Description of the Related Art A typical conventional differential amplifier circuit is shown in FIGS. Of the transistors used here, Tr1 and Tr2 in FIG. 4 are depletion type transistors, and the others are all enhancement type transistors.

【0003】また図5に、従来の折り返しカスケード型
差動増幅回路の代表的な例を示す。ここでは、全てエン
ハンスメント型トランジスタをもって構成されている。
Further, FIG. 5 shows a typical example of a conventional folded cascade type differential amplifier circuit. Here, all are configured with enhancement type transistors.

【0004】[0004]

【発明が解決しようとする課題】ところで、従来の差動
増幅回路は、同相入力電圧範囲の上限又は下限が、それ
ぞれVDDより下又はVSSより上の値に制限されていた。
By the way, in the conventional differential amplifier circuit, the upper limit or the lower limit of the common mode input voltage range is limited to a value below V DD or above V SS , respectively.

【0005】図3の例では、入力トランジスタTr1,
Tr2がエンハンスメント型であるため、入力1,入力
2の電圧がTr1,Tr2のVTHより低い場合、Tr1,
Tr2はほとんどオフになってしまい、増幅回路として
の機能を失う。
In the example of FIG. 3, the input transistors Tr1,
Since Tr2 is an enhancement type, if the voltage of input 1 and input 2 is lower than V TH of Tr1 and Tr2, then Tr1,
Tr2 is almost turned off, and the function as an amplifier circuit is lost.

【0006】図4の例では、入力トランジスタTr1,T
r2がデプレッション型であるため、入力1,入力2の
電圧がVSS付近であっても動作するが、VDD付近にある
場合、Tr1,Tr2の共通ソース端子の電圧とVDDの電
圧との差がTr3のVTHの絶対値より小さくなり、Tr
3,Tr4がほとんどオフになってしまい、増幅回路と
しての機能を失う。
In the example of FIG. 4, the input transistors Tr1 and T1
Since r2 is a depletion type, the input 1, the voltage of the input 2 is operated even near V SS, when in the vicinity of V DD, the voltage of the voltage and V DD of the common source terminal of the Tr1, Tr2 The difference becomes smaller than the absolute value of V TH of Tr3, and Tr
3, Tr4 is almost turned off, and the function as an amplifier circuit is lost.

【0007】図4の回路において、Tr1,Tr2のバッ
クゲートをVSSに接続すると、入力電圧が高いときに、
Tr1,Tr2のVTHがエンハンスメント型に移動するた
めに、同相入力範囲をVDD〜VSSとすることが可能であ
る。しかし、この場合、Tr1,Tr2のVTHがTr3,T
r4のVTHの絶対値より十分大きくなるには、大きなV
DDが必要となり、実用的ではない。
In the circuit of FIG. 4, when the back gates of Tr1 and Tr2 are connected to V SS , when the input voltage is high,
Since V TH of Tr1 and Tr2 moves to the enhancement type, it is possible to set the common mode input range to V DD to V SS . However, in this case, V TH of Tr1 and Tr2 is Tr3, T
In order to be sufficiently larger than the absolute value of V TH of r4, a large V
DD is required and not practical.

【0008】図5の例では、図3の例と同じように、入
力1,入力2の電圧がVSS付近では機能を失う。
In the example of FIG. 5, as in the example of FIG. 3, the function of the input 1 and the input 2 is lost near the voltage V SS .

【0009】本発明は、上記問題点を解決しようとする
もので、通常の電源電圧(例えば、3V,5V程度)に
おいて、同相入力電圧範囲がVDD〜VSSである差動増幅
回路を構成する半導体装置を提供することを目的とす
る。
The present invention is intended to solve the above problems, and configures a differential amplifier circuit having a common-mode input voltage range of V DD to V SS at a normal power supply voltage (for example, about 3 V and 5 V). It is an object of the present invention to provide a semiconductor device having

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、折り返しカスケード型差動増幅回路にお
いて、入力トランジスタに、デプレッション型MOSF
ETを用いたことを特徴とするものである。
To achieve the above object, the present invention provides a folded cascade type differential amplifier circuit in which a depletion type MOSF is used as an input transistor.
It is characterized by using ET.

【0011】[0011]

【作用】上記構成によれば、入力電圧がVSS付近でも入
力トランジスタはオフにならず、また、VDD付近でも電
圧が制限されない。従って、差動増幅回路の同相入力電
圧をVDDからVSSまでとすることができる。
According to the above structure, the input transistor is not turned off even when the input voltage is near V SS , and the voltage is not limited even near V DD . Therefore, the common mode input voltage of the differential amplifier circuit can be changed from V DD to V SS .

【0012】[0012]

【実施例】以下、図面に基づいて実施例を詳細に説明す
る。図1は、本発明の一実施例の折り返しカスケード型
差動増幅回路を示したものであり、図5の従来回路の入
力トランジスタTr1,Tr2をデプレッション型MOS
FET Tr11,Tr12に置き換えたものである。他の構
成は全く同じである。
Embodiments will be described below in detail with reference to the drawings. 1 shows a folded cascade type differential amplifier circuit according to an embodiment of the present invention, in which the input transistors Tr1 and Tr2 of the conventional circuit shown in FIG.
It is replaced with FETs Tr11 and Tr12. Other configurations are exactly the same.

【0013】このように、本実施例では、入力トランジ
スタTr11,Tr12がデプレッション型であるため、入力
1及び入力2の電圧がVSS付近でもTr11,Tr12はオフ
にはならない。また、入力1,入力2の電圧がVDD付近
でも、電圧が制限されることがない。例えば、定電流源
2,3に図2のTr14,Tr15を用いると、Tr13,Tr14,
Tr15が定電流値に対して十分大きなサイズであれば、
Tr14,Tr15のドレイン−ソース電圧が略0Vまで十分
定電流動作をするので、同相入力電圧範囲はVDD〜VSS
まで十分にとれる。
As described above, in this embodiment, since the input transistors Tr11 and Tr12 are of the depletion type, Tr11 and Tr12 are not turned off even when the voltage of the input 1 and the input 2 is near V SS . Further, even if the voltage of the input 1 and the input 2 is near V DD , the voltage is not limited. For example, if Tr14 and Tr15 shown in FIG. 2 are used for the constant current sources 2 and 3, Tr13, Tr14,
If Tr15 is large enough for the constant current value,
Since the drain-source voltages of Tr14 and Tr15 operate sufficiently constant current up to about 0 V, the common-mode input voltage range is from V DD to V SS.
Can take enough.

【0014】図1の回路において、入力トランジスタT
r11,Tr12のバックゲートをVSSに接続すると、入力
1,入力2がVDD付近のとき、Tr11,Tr12のデプレッ
ションしたVTHの絶対値が小さくなり、又はエンハンス
メントになるため、定電流源2,3の動作電圧が図1の
回路より確保されるため、さらに有利となる。
In the circuit of FIG. 1, the input transistor T
When the back gates of r11 and Tr12 are connected to V SS , when the input 1 and the input 2 are near V DD , the absolute value of the depleted V TH of Tr11 and Tr12 becomes small or becomes an enhancement, so that the constant current source 2 , 3 is ensured by the circuit of FIG. 1, which is more advantageous.

【0015】[0015]

【発明の効果】以上説明したように、本発明によれば、
入力に用いたデプレッション型MOSFETによって、
差動増幅回路の同相入力電圧をVDDからVSSまでとする
ことができる。
As described above, according to the present invention,
By the depletion type MOSFET used for input,
The common mode input voltage of the differential amplifier circuit can be from V DD to V SS .

【0016】また、デプレッション型MOSFETのバ
ックゲートを、Nchトランジスタの場合、VSSに接続
し、Pchトランジスタの場合、VDDに接続することによ
り、負荷の定電流回路の動作電圧を確保できるため、回
路の動作を安定化することができる。
Further, by connecting the back gate of the depletion type MOSFET to V SS in the case of the Nch transistor and connecting it to V DD in the case of the Pch transistor, the operating voltage of the constant current circuit of the load can be secured. The operation of the circuit can be stabilized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の回路構成図である。FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

【図2】図1の定電流源の具体的回路を示す図である。FIG. 2 is a diagram showing a specific circuit of the constant current source of FIG.

【図3】従来の代表的差動増幅回路の構成図である。FIG. 3 is a configuration diagram of a conventional representative differential amplifier circuit.

【図4】入力トランジスタにデプレッション型を用いた
従来の差動増幅回路の構成図である。
FIG. 4 is a configuration diagram of a conventional differential amplifier circuit using a depletion type as an input transistor.

【図5】従来の代表的な折り返しカスケード型差動増幅
回路の構成図である。
FIG. 5 is a configuration diagram of a conventional typical folded cascade type differential amplifier circuit.

【符号の説明】[Explanation of symbols]

Tr5〜Tr8 … MOSFET、 Tr11,Tr12 … デ
プレッション型MOSFET。
Tr5 to Tr8 ... MOSFET, Tr11, Tr12 ... Depletion type MOSFET.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 折り返しカスケード型差動増幅回路にお
いて、入力トランジスタに、デプレッション型MOSF
ETを用いたことを特徴とする半導体装置。
1. A depletion type MOSF is used as an input transistor in a folded cascade type differential amplifier circuit.
A semiconductor device using ET.
【請求項2】 デプレッション型MOSFETがNchト
ランジスタの場合、そのバックゲートをVSSに接続した
ことを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein when the depletion type MOSFET is an Nch transistor, its back gate is connected to V SS .
【請求項3】 デプレッション型MOSFETがPchト
ランジスタの場合、そのバックゲートをVDDに接続した
ことを特徴とする請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein when the depletion type MOSFET is a Pch transistor, its back gate is connected to V DD .
JP16454291A 1991-07-04 1991-07-04 Semiconductor device Pending JPH05304426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16454291A JPH05304426A (en) 1991-07-04 1991-07-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16454291A JPH05304426A (en) 1991-07-04 1991-07-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05304426A true JPH05304426A (en) 1993-11-16

Family

ID=15795142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16454291A Pending JPH05304426A (en) 1991-07-04 1991-07-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05304426A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006330869A (en) * 2005-05-24 2006-12-07 Sanyo Electric Co Ltd Regulator circuit
JP2007201879A (en) * 2006-01-27 2007-08-09 Nec Electronics Corp Differential signal receiving circuit
JP2007202127A (en) * 2005-12-28 2007-08-09 Nec Electronics Corp Differential amplifier and display device using the same
JP2009201119A (en) * 1996-03-19 2009-09-03 Semiconductor Components Industries Llc Low voltage operational amplifier and method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009201119A (en) * 1996-03-19 2009-09-03 Semiconductor Components Industries Llc Low voltage operational amplifier and method
JP2006330869A (en) * 2005-05-24 2006-12-07 Sanyo Electric Co Ltd Regulator circuit
JP2007202127A (en) * 2005-12-28 2007-08-09 Nec Electronics Corp Differential amplifier and display device using the same
JP2007201879A (en) * 2006-01-27 2007-08-09 Nec Electronics Corp Differential signal receiving circuit

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