CN100565472C - A kind of adjustment method that is applicable to multiprocessor karyonide system chip - Google Patents
A kind of adjustment method that is applicable to multiprocessor karyonide system chip Download PDFInfo
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- CN100565472C CN100565472C CNB2007101645846A CN200710164584A CN100565472C CN 100565472 C CN100565472 C CN 100565472C CN B2007101645846 A CNB2007101645846 A CN B2007101645846A CN 200710164584 A CN200710164584 A CN 200710164584A CN 100565472 C CN100565472 C CN 100565472C
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Abstract
The invention discloses a kind of adjustment method that is applicable to multiprocessor karyonide system chip: simulate a main control processor and debugging control station program with a virtual master control processor core module (111) that operates on the host, be responsible for sending and receiving order, the debugging of control multiprocessor karyonide system chip, send debug command to the operation debugging services station module (131) on each processor core of physics, and receive return information to the software running device that has graphic interface (110) that operates on the host.The inventive method takies less hardware resource, utilizes software to debug, and is portable strong, is applicable to multiprocessor karyonide system chip/network-on-chip platform debugging.
Description
Technical field
The present invention relates to a kind of adjustment method that is applicable to multiprocessor karyonide system chip.
Background technology
Along with the development of transistor technology and the driving of application demand in recent years, the embedded chip design enters multiprocessor karyonide system chip (MPSoC) from uniprocessor karyonide system.How the program of moving on the multiprocessor karyonide system chip is debugged, become a problem that presses for solution.
The adjustment method of traditional single core processor program has software and hardware method two big classes.Software debugging method such as GNU Debugger (GDB) run on host, operation GDB Stub on the processor, GDB provides the information of debugged program to the user, and to GDB Stub transmission debugging request, as the value of checking register, GDB Stub handles accordingly according to the debugging request, and to the GDB feedback information.The hardware debug method as JTAG, EJTAG and Trace etc., enters a specific debugging attitude by making processor core by adding debugging interface at processor; In this debugging attitude, the information that can check processor core.The advantage of software approach is lower for supporting to debug the hardware costs that increases, and only needs processor core to support breakpoint, break-poing instruction and exception handling etc.; It is fast that shortcoming is that debugging speed is not so good as hardware approach.The advantage of hardware approach is that debugging speed is very fast, and the result is not exerted an influence, low invasive (debug not occupying system resources, the behavior of reprogramming execution does not exert an influence to the result); Shortcoming is the hardware costs height, and construction cycle, chip area and power consumption increase to some extent; When integrated a plurality of processor, if each nuclear increases debugging interface and cause chip area, power consumption to increase.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of adjustment method that is applicable to multiprocessor karyonide system chip, this method can be debugged the multiprocessor karyonide system chip of isomorphism or isomery, and checks, controls debugged running state of programs by the software through pictures debugging acid on the host.
In order to solve the problems of the technologies described above, the invention provides a kind of adjustment method that is applicable to multiprocessor karyonide system chip: simulate a main control processor and debugging control station program with a virtual master control processor core module 111 that operates on the host, be responsible for sending and receiving order, the debugging of control multiprocessor karyonide system chip, send debug command to the operation debugging services station module 131 on each processor core of physics, and receive return information to the software running device that has graphic interface 110 that operates on the host.
As the improvement that is applicable to the adjustment method of multiprocessor karyonide system chip of the present invention, this method may further comprise the steps:
1), software running device 110 provides single-step debug operation, setting/removal breakpoint at the operation debugging services station module 131 on each processor core and moves to the function at breakpoint place; And above-mentioned functions is converted to the debug command bag of specific format, debug command is sent to the debugging control station module 112 of operation on virtual master control processor core module 111 by the Windows inter-process communication mechanisms;
2), virtual master control processor core module 111 successively by the Peripheral Interface on the host, with the communication interface 121 that the bus (if multiprocessor karyonide system is based on bus architecture) or the bus (if multiprocessor karyonide system is based on on-chip network structure) on the network-on-chip node of multiprocessor karyonide system chip link to each other, visit the global storage 140 on the multiprocessor karyonide system chip hardware platform;
The debug command that virtual master control processor core module 111 is received debugging control station module 112 is transmitted to the operation debugging services station module 131 on each processor core;
3), the debugged program moved on operation debugging services station module 131 pairs of these processor cores is carried out the desired action of debug command, and is produced corresponding return message;
4), operation debugging services station module 131 and virtual master control processor core module 111 communicate by letter by communication protocol, therefore above-mentioned return message arrives virtual master control processor core modules 111 by communication interface 121, finally does corresponding demonstration at software running device 110.
Therefore, the present invention mainly comprises the content of three parts.First is the software running device that has graphic interface 110 on the host.Second portion is a virtual master control processor core module 111 on the host, this virtual master control processor core module 111 can be by the Peripheral Interface on the host (as USB, serial ports, parallel port etc.) communicate by letter with multiprocessor nuclear hardware open platform, the shared storage space (being global storage 140) of the bus (if multiprocessor karyonide system is based on bus architecture) that this virtual master control processor core module 111 can be by being connected to multiprocessor karyonide system chip or the Peripheral Interface access system chip of the bus (if multiprocessor karyonide system is based on on-chip network structure) on the network-on-chip node is (if multiprocessor karyonide system is based on on-chip network structure, virtual master control processor core module (111) sends the debug command that debugging control station module (112) is received, this debug command arrives on the processor core specified in the debug command by the network-on-chip route).Third part is the operation debugging services station module 131 on each processor core.The hardware abstraction of multiprocessor karyonide system chip and software configuration are as shown in Figure 1.Specify as follows:
First, the software running device that has graphic interface 110 on the host (called after GUIMPSoC Debugger, below replace with GMD abbreviation) mainly show the ruuning situation of the operation debugging services station module 131 on each processor core, the address that stops as the program of moving on each processor, the value of register, the data of the length-specific on the particular memory space, and provide single-step debug to move at the operation debugging services station module 131 on each processor core to the user, setting/removal breakpoint, move to the function at breakpoint place, this software running device 110 is responsible for these functions are converted to the debug command bag of specific format, debug command is sent to the debugging control station module 112 of operation on the virtual master control processor core module 111 of second portion by the Windows inter-process communication mechanisms, and wait for that packets of information that operation debugging services station module 131 is returned upgrades the situation of debugged program on each processor that shows on the software running device 110 of graphic interface.
Second portion, the virtual master control processor core module 111 on the host (Virtual Mainprocessor Core below is abbreviated as VMC) is the software simulator of RISC nuclear expansion.This emulator by with host that the communication interface 121 of the hardware platform of multiprocessor karyonide system chip links to each other on Peripheral Interface visit the global storage 140 (GM:GlobalMemory) that multiprocessor is examined hardware platform.An operation debugging control station module 112 (Debugger Control Station below is abbreviated as DCS) on the virtual master control processor core module 111, the debug command that debugging control station module 112 receives from software running device 110 is transmitted to processor core;
Third part, operation debugging services station module 131 (Debugger ServiceStation on the processor core, below be abbreviated as DSS), this part is carried out the desired action of debug command to the debugged program of moving on this processor core, and the generation return message, this part and virtual master control processor core module 111 are communicated by letter by communication protocol.
The inventive method at hardware abstraction as shown in Figure 1: suppose physically to have 1 RISC nuclear and N-1 RISC/DSP to examine, overall situation storage 140 (GM) are arranged, RISC nuclear is connected to bus/network-on-chip, and DSP nuclear is by direct memory access (DMA:Direct Memory Access) visit GM (DSP nuclear also can be connected to bus/network-on-chip).
The present invention is applicable to the adjustment method of multiprocessor karyonide system chip, be characterized in adopting method for testing software, by operating in the software running device 110 on the host, check the debugged program information that moves on each processor, data of the length-specific on the address that stops as the program of moving on each processor, register value, the particular memory space etc.; Control the running status of the operation debugging services station module 131 on each processor, be provided with etc. as single-step debug and breakpoint.
The present invention is applicable to the adjustment method of multiprocessor karyonide system chip, be by the operation debugging services station module 131 on each specific processor core and operate in communication protocol, communication mechanism between the debugging control station module 112 on the host, at one/a plurality of processor cores when long-play (obstruction), debugging control station module 112 on the host guarantees that by the unblock mode other processor cores still can be debugged.
The present invention is applicable to the adjustment method of multiprocessor karyonide system chip, by adopting the virtual master control processor core module of moving on the host 111, according to specific communication protocol, send debug command to the operation debugging services station module of moving on each processor core in the multiprocessor karyonide system 131, receive the method that the operation debugging services station module 131 moved on each processor core replys and carry out the debugging of multiprocessor karyonide system chip.By specific mechanism, can guarantee one or more processor cores when long-play (obstruction), other processor cores still can be debugged.This method takies less hardware resource, utilizes software to debug, and is portable strong, is applicable to multiprocessor karyonide system chip/network-on-chip platform debugging.
In sum, compare with existing method, the adjustment method of multiprocessor karyonide system chip that is applicable to of the present invention has following advantage: portable strong, can be adapted to isomorphism/heterogeneous multi-processor karyonide system chip based on bus/network-on-chip communication pattern; Hardware cost is low, and the additional hardware resources of support debug system comprises the buffer zone of the overall memory block of two 32 bytes, (4 * N+1) individual 1 bit registers (N is the processor core number); Can guarantee one or more processor cores when long-play (obstruction), other processor cores still can be debugged.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
Fig. 1 is the abstract and software architecture diagram of multiprocessor karyonide system chip hardware;
Fig. 2 is the overall flow figure that handles debug command (non-definite order and definite order) DCS;
Fig. 3 is the overall flow figure that handles debug command (non-definite order and definite order) GMD;
Fig. 4 is the overall flow figure that handles debug command (non-definite order and definite order) DSS.
Embodiment
The form that the present invention defines mode order bag, return message bag is: processor core number, and thread number (optional), basic command (or returning the bag basic format), as follows:
Single step run:
MP_step＝{C1_s，C2_s，...，{C
i_thread1_s，C
i_thread2_s，...}，..}
Return_MP_step＝{C1_S_address，C2_S_address，...，{C
i_thread1_S_address，C
i_thread2_S_address，...}，...}
Increase breakpoint:
MP_add_break＝{C1_z_address，C2_z_address，...，{C
i_thread1_z_address，C
i_thread2_z_address...}，..}
Return_MP_add_break＝{C1_zOK，C2_zOK，...，{C
i_thread1_zOK，C
i_thread2_zOK...}，...}
The deletion breakpoint:
MP_delete_break＝{C1_Z_address，C2_Z_address，...，{C
i_thread1_Z_address，C
i_thread2_Z_address，...}，..}
Return_MP_delete_break＝{C1_ZOK，C2_ZOK，...，{C
i_thread1_ZOK，C
i_thread2_ZOK...}，...}
Check the value of register:
MP_register＝{C1_r，C2_r，...，{C
i_thread1_r，C
i_thread2_r...}，..}
Return_MP_register＝{C1_rvalue，C2_rvalue，...，{C
i_thread1_rvalue，C
i_thread2_rvalue...}，...}
Check the value of storer:
MP_memory＝{C1_m_addr_length，C2_m_addr_length，...，{C
i_thread1_m_addr_length，C
i_thread2_m_addr_length...}，..}
Return_MP_register＝{C1_mvalue，C2_mvalue，...，{C
i_thread1_mvalue，C
i_thread2_mvalue...}，...}
Specify the start address of each debugged program:
MP_start_address＝{C1_start_address，C2_start_address，...，{C
i_thread1_start_address，C
i_thread2_start_address...}，..}
Return_MP_start_address＝{C1_address，C2_address，...，{C
i_thread1_address，C
i_thread2_address...}，...}
Specify a debugged EOP (end of program) debugging:
MP_end＝{C1_end，C2_end，...，{C
i_thread1_end，C
i_thread2_end...}，..}
Return_MP_end＝{C1_endOK，C2_endOK，...，{C
i_thread1_endOK，C
i_thread2_endOK...}，...}
Continue to move up to breakpoint:
MP_continue＝{C1_c，C2_c，...，{C
i_thread1_c，C
i_thread2_c，...}，..}
It is as shown in table 1 below that this returns the bag basic format:
Table 1, continuation move up to the debug command basic format of breakpoint and return the bag basic format
| Order bag basic format | Return the bag basic format |
| c | [Signal number][exception address]， |
| If in a regular time, return; Not_ready is if can't return in the set time |
C1 in above debug command/return information form, C2 ..., C
i... represent the number of processor core respectively, C
i_ thread1, C
i_ thread2 etc. represent the thread number moved on the i processor core respectively.Because in actual applications, operating on certain processor core of task may be divided into a plurality of threads, also may have only single thread, so, the debug command that is similar to the C1_s form the task on certain processor core of being aimed at has only the situation of single thread, when the debug command that is similar to the C3_thread2_s form the task on certain processor core of being aimed at is refined as a plurality of thread to the debug command of some specific thread.
Concrete implementation step of the present invention comprises following several respects (below be to be that bus connecting mode is an example with the hardware platform):
I), the download and the initialization of the operation debugging services station module 131 on the processor:
1, on host, by cross compilation environment (as GCC instrument chain), generation runs on the machine code file that loads/move of the operation debugging services station module 131 on each processor core, and produce the machine code file that loads/move of debugged assembly routine, they are incorporated in the file file that is referred to as to integrate;
2, the file of integrating in 1 is downloaded to global storage 140 after, by the reset button, value with N VMC_write_ready register, the value of N VMC_read_ready register, the value of N Physical_Core_write_ready register, the value of N Physical_Core_read_ready register all is initialized as 0, and the Lock initialization of register is 1.RISC/DSP nuclear starts the DMA communication channel, and the program (comprising operation debugging services station module 131 and debugged program) that operates in this integrating document on the par-ticular processor is transported on the local storage of par-ticular processor;
3, after carrying finishes, debugging services station module 131 on each processor core begins to carry out, exception handler is copied to a certain unusual inlet, and operation debugging services station module 131 just begins to inquire about the Start_Address[addr of wait at the debugged program on this processor core] order;
4, the software running device 110 on the startup host, and on the virtual master control processor core module 111 on the host, move debugging control station module 112, the debug commands of software running device 110 by sending are waited in module 112 inquiries in debugging control station.
II), debugging beginning:
1, the user specifies the debugging start address of i processor core on software running device 110, and software running device 110 sends " Core[i] _ Start_Address[addr] " by the Windows inter-process communication mechanisms, and (1≤i≤N) gives the debugging control station module 112 of operation on the virtual master control processor core module 111;
2, when debugging control station module 112 is received the debug command of software running device 110, at first with the value of N VMC_read_ready register, be made as 0 with the value of N VMC_write_ready register, and the value of Lock register is made as 1, the virtual master control processor core is put in this order write buffering 141, and the value of i VMC_write_ready register is made as 1, and wait for the answer of i processor core;
3, the value that the debugging services station module of moving on i processor core 131 inquires i VMC_write_ready register is 1; I),, be transported on the private room with regard to starting the order that DMA writes the virtual master control processor core on the buffering 141 ii) if DSP nuclear if RISC nuclear just reads this order;
4, the instruction on operation module 131 save routine addresses [addr], debugging services station on i the processor core, and the instruction of this address replaced with a break-poing instruction (break), begin to carry out from jumping to program address [addr] then, obviously, because break-poing instruction will enter unusual inlet;
5, at unusual inlet, operation debugging services station module 131 at first goes up original instruction with the program address [addr] of preserving and recovers, with Core[i] _ [exception address] (1≤i≤N) put into physics nuclear to write buffering 142, the value of i Physical_Core_write_ready register is made as 1, and notice debugging control station module 112 reads;
6, find that i Physical_Core_write_ready is 1 when debugging control station module 112, just the return information that physics nuclear is write in the buffering 142 reads and returns to software running device 110, the value that i VMC_read_ready register is set simultaneously is 1, notifies i operation debugging services station module 131 to read and finishes;
7, i operation debugging services station module 131 finds that the value of i VMC_read_ready register is 1, just the value of i Physical_Core_read_ready register and the value of i Physical_Core_write_ready register are made as 0, and begin to wait for other debug commands;
8, the debugging start address of debugged program on i processor core of software running device 110 update displayed.
III), handle debug command:
When traditional uniprocessor remote debugging scheme expands to multiprocessor karyonide system chip, the single step order, viewing command, increase/removal breakpoint commands etc. meet with a response in can be at a fixed time, wherein may occur is to read a large amount of storage data than long response time, the data length that reads by the once multipotency of agreement restriction, agreement once reads M word (can dispose appointment by the user) at most in the inventive method, like this after the regulation, the answer of then above order can arrive in a time restriction all that (maximum delay of for example, supposing to read a word of storer is T
m, then once reading M word required time is M * T
m).And for continuing to carry out (continue) this debug command, the debugged program on some processor cores, may be arranged on after the needs execution circulation for a long time by a breakpoint, perhaps because program is rigorous inadequately, this circulation is that an endless loop is (since be debugged program, contain defectiveness probably), such situation can cause virtual master control processor core module 111 to take a long time waiting for debugged program run on some processor cores to breakpoint, and the debugged program on other processor cores can't continue debugging.For addressing this problem, the communication protocol of the present invention's definition is handled with different mechanism and is continued action command (being called non-definite order) and other orders (be called and determine order).
A), at determining order:
1, the user uses and determines order, as debugged program on i the processor core is carried out single-step debug, the debugging control station module 112 of software running device 110 on virtual master control processor core module 111 sends " Core[i] _ s " (1≤i≤N), and wait for and replying;
2, debugging control station module 112 finds that software running device 110 sends order, at first the value of N VMC_read_ready register and the value of N VMC_write_ready register are put 0, then this order is put into the virtual master control processor core and write buffering 141, and the value of i VMC_write_ready register put 1, wait for that operation debugging services station module 131 is replied on i the processor core;
3, the value that inquires i VMC_write_ready register of the operation debugging services station module 131 on i processor core is 1, i) if RISC nuclear, just read this order, ii) if DSP nuclear, the virtual master control processor core is write the order of buffering on 141 be transported on the local storage with regard to starting DMA, and the value of i Physical_Core_read_ready register is changed to 1;
4, to inquire the value of i Physical_Core_read_ready register be 1 to debugging control station module 112, and just the value with i VMC_write_ready register is changed to 0;
5, operation debugging services station module 131 is made corresponding action according to debug command, then return information is write physics nuclear and is write buffering 142, and the value of i Physical_Core_write_ready register is changed to 1;
6, to inquire the value of i Physical_Core_write_ready be 1 to debugging control station module 112, just the answer that physics nuclear is write in the buffering 142 is read, and the value of i VMC_read_ready register is changed to 1, and answer is sent to software running device 110;
7, the value that inquires i VMC_read_ready register of the operation debugging services station module 131 on i processor core is 1, just with the value of i Physical_Core_read_ready register, the value of Physical_Core_write_ready register is changed to 0, and begins new one and take turns the inquiry debug command;
8, software running device 110 upgrades the information of i debugged program on showing.
Increased by three mechanism for continuing non-definite debug command, made a processor core when long-play (obstruction), other processor cores still can be debugged.
Mechanism 1: use timer on the debugging control station module 112.After debugging control station module 112 is received a non-definite order at the debugged program on i the processor core, open a timer, and wait for the response of i operation debugging services station module 131, if before timer finishes, do not receive the return information of i operation debugging services station module 131, then send Core[i to software running device 110] _ not_ready, and the debug command inquiry of a beginning new round.Receive not_ready when software running device 110, just stop to wait for the response of this non-definite order, and show on i the processor core debugged program still the operation;
Mechanism 2: still moving when software running device 110 shows the debugged program on i the processor core, the user can debug the debugged program on other processor cores.Software running device 110 will be issued debugging control station module 112 to these orders, and at this moment, the debugged program on i processor core may arrive the breakpoint place, and will send a reply.So whether all can at first inquire about during all over beginning in each of debugging control station module 112 inquiry debug commands has certain operation debugging services station module 131 to put into physics nuclear at the answer of before continuation debug command to write buffering 142, if have, then should reply record, when receiving the debug command of software running device 110, software running device 110 is returned in the answer that will write down earlier, returns the pairing answer of this debug command in the communication protocol afterwards again.Software running device 110 is received when a form is different from answer on the communication protocol, illustrate that this is the preceding exectorial answer that once continues, update displayed information then: the program of moving on previous i the processor core has run to the breakpoint place, waits for the answer at this debug command afterwards once more;
Mechanism 3: mechanism may be brought a stationary problem in 2: certain operation debugging services station module 131 is being prepared to write in the buffering 142 to physics nuclear and is being write answer, and the debugged program on another processor core is carried out to the breakpoint place, also prepare to write buffering 142 to physics nuclear and write answer, this can constitute competition.Solution is to use the Lock register of a 1bit, its value is 1 expression unlocking condition, it is 0 expression locking state, when a plurality of operation debugging services station module 131 is prepared to write physics nuclear and is write buffering 142, at first inquire about the value of Lock register, certain operation debugging services station module 131 is got lock, and the value of Lock register is changed to 0 (locking), and other operation debugging services station modules 131 will wait for that unblank (value 1 that Lock is register) just can write physics nuclear and write buffering 142 like this.The operation debugging services station module 131 of getting lock writes physics nuclear with answer and writes buffering 142, and inquire after VMC_read_ready is 1, the value of Lock register is changed to 1 (unblanking), and then, remaining operation debugging services station module 131 just can be robbed lock once more;
B) at non-definite order:
We only consider to continue exectorial answer and fail situation about arriving before timer finish, if arrived before timer finishes, then process is the same with the rule absolute processing mode:
1, the user will carry out the debugged program on i the processor core and continue action command, and software running device 110 sends " Core[i] _ c " (debugging control station module 112 on the virtual master control processor core module 111 of 1≤i≤N);
2, the order that module 112 query software debuggers 110 in debugging control station send, at first with the value of N VMC_read_ready register, the value of N VMC_write_ready register puts 0, and check that whether the value of certain Physical_Core_write_ready register is arranged is 1 (before continuing the answer of action command), if have, just write the buffering 142 and read return information and return to software running device 110 from physics nuclear, then the order of software running device 110 is put into the virtual master control processor core and write buffering 141, and the value of i VMC_write_ready register put 1, wait for that operation debugging services station module 131 is replied on i the processor core;
3, the value that inquires i VMC_write_ready register of the operation debugging services station module 131 on i processor core is 1, i) if RISC nuclear, just read this order, ii) if DSP nuclear, the virtual master control processor core is write the order of buffering on 141 be transported to local storage with regard to starting DMA, and the value of i Physical_Core_read_ready register is changed to 1;
4, to inquire the value of i Physical_Core_read_ready register be 1 to debugging control station module 112, just the value with i VMC_write_ready register is changed to 0, and starts a timer and wait for i answer that moves debugging services station module 131;
5, operation debugging services station module 131 is made corresponding action according to debug command, then return information is write physics nuclear and is write buffering 142, and the value of i Physical_Core_write_ready register is changed to 1;
Do not find that as yet the value of i Physical_Core_write_ready register is 1 if 6 finish debugging control station module 112 to timer, just send Core[i to software running device 110] _ not_ready, and the order inquiry of a beginning new round;
7, the debugged program on software running device 110 update displayed information, i processor core still in operation, can not debug, but the debugged program on other processor cores still can be debugged;
8, the user debugs the debugged program on other processor cores, and software running device 110 sends order to debugging control station module 112, as going up debugged program at j nuclear.Debugging control station module 112 is in the order inquiry of a new round, previous continuation action command may be replied (value that debugging control station module 112 inquires i Physical_core_write_ready register is 1), if like this, debugging control station module 112 is noted this answer, and after debugging control station module 112 was received an order, at first the answer that will write down sent to software running device 110;
If 9 software running devices 110 find that the answer form of receiving not is to stipulate on the communication protocol, represent that this answer continues action command at last one, software running device 110 at first upgrades Debugging message, debugged program on i processor core arrives the breakpoint place, and waits for the answer at this debug command once more;
If 10 i, j operation debugging services station module 131 finished corresponding debugging action simultaneously, and prepares to write in the buffering 142 toward physics nuclear and write answer, and it is synchronous then to use a Lock register, method such as above machine-processed 3 descriptions;
Debugging control station module 112, software running device 110, operation debugging services station module 131 is handled overall flow figure such as Fig. 2 of debug command (non-definite order and definite order), and Fig. 3 is shown in Figure 4.
IV) debugging finishes:
The user prepares to finish the debugging of the debugged program on certain processor core, may still debug other processor cores, so increased debug command a: end among the present invention, form such as preamble introduction.This order sends to each operation debugging services station module 131 by debugging control station module 112, and method determines that with the processing of front order is the same, and operation debugging services station module 131 is replied OK, and left unusual inlet when receiving this order.This processor core debugging of update displayed finishes after software running device 110 is received endOK.
If hardware platform is the network-on-chip syndeton, basic skills is constant so, just with (4 * N+1) individual VMC_write_ready at each processor core, VMC_read_ready, Physical_Core_write_ready, Physical_Core_read_ready register and Lock register change the variable of 4 * N+1 1bit length in overall situation storage into, and other are constant.
At last, it is also to be noted that what more than enumerate only is specific embodiments of the invention.Obviously, the invention is not restricted to above examples of implementation, many distortion can also be arranged.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention all should be thought protection scope of the present invention.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9513985B1 (en) | 2015-06-29 | 2016-12-06 | International Business Machines Corporation | Efficiency of cycle-reproducible debug processes in a multi-core environment |
| US9626265B2 (en) | 2015-06-29 | 2017-04-18 | International Business Machines Corporation | Efficiency of cycle-reproducible debug processes in a multi-core environment |
| US9678151B2 (en) | 2015-06-29 | 2017-06-13 | International Business Machines Corporation | Efficiency of cycle-reproducible debug processes in a multi-core environment |
| US9852037B2 (en) | 2015-06-29 | 2017-12-26 | International Business Machines Corporation | Efficiency of cycle-reproducible debug processes in a multi-core environment |
| TWI775307B (en) * | 2021-02-04 | 2022-08-21 | 新唐科技股份有限公司 | Semiconductor device and operation method thereof |
| US11663101B2 (en) | 2021-02-04 | 2023-05-30 | Nuvoton Technology Corporation | Semiconductor device and operation method thereof |
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