CN111176926B - IP core simulation system and simulation method based on dual-port SRAM - Google Patents
IP core simulation system and simulation method based on dual-port SRAM Download PDFInfo
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Abstract
The invention provides an IP core simulation system and a simulation method based on a dual-port SRAM, wherein the simulation system comprises a design module to be verified, a central processing unit and the dual-port SRAM; the CPU is used for constructing a hierarchical CPU bus function model, and the bus function module is used for realizing the purpose of accessing the dual-port SRAM module to make corresponding data structures for preparing to transmit read-write data to the dual-port SRAM and transmitting read-write commands according to a register configuration interface of the design module to be verified; the dual-port SRAM is used for replacing a bus controller and an arbiter in the traditional system to realize direct access of two MASTERs to the SRAM, so that the complexity of the simulation system is greatly reduced, and meanwhile, the hierarchical CPU bus function model is arranged, and when the module interface is changed, only the corresponding MASTER BFM is selected for instantiation, so that the simulation system can be used continuously. The multiplexing of the whole verification assembly is greatly improved, different modules can use the system to quickly construct own simulation system, and the working efficiency of verification personnel is greatly improved.
Description
Technical Field
The present disclosure relates to the field of interface module verification technologies, and in particular, to an IP core simulation system and a simulation method based on a dual-port SRAM.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
Development and multiplexing of IP (Intellectual Property) are key technologies of System on Chip (SoC), and IP verification is a core link of IP development. The time and workload of functional timing simulation, testing and verification of IP greatly exceeds that of system and logic design. Thus, simulation testing of IP becomes a critical part of the design. The general verification method of the soft IP core is to perform software simulation under a software environment to verify the correctness of the IP (Intellectual Property) core function, then write the software simulation into a FPGA (Field Progamable Gate Array) device to verify a hardware circuit, complete the verification of the IP core if the test is correct, and return to modify the IP core again if the test has a problem.
The interface module is one of the IP cores and is used for realizing data transmission between different devices or different systems, so that the data transmission process of the interface module, especially the high-speed interface module, is often complex at present, and the participation of a CPU and an SRAM is needed in many cases. The number of bus function models, BFMs, required to authenticate such interface modules is relatively large, thus forming a small system, which requires the participation of various bus controllers and arbiters to coordinate. Because the bus controller and the arbiter are often complex, the design and application are both relatively labor and time intensive.
Many interface modules, especially high-speed interface modules, need to configure a certain data structure in advance to SRAM through a bus by means of a CPU to realize high-speed data transmission. In this case, two hosts simply called MASTERs access the SRAM through an interface (one is a CPU connection interface and one is a data interface of a module), if an ordinary SRAM is used at this time, the accesses of the two MASTERs must be arbitrated, and in general, the system performs arbitration between different MASTERs through a bus controller, and the two MASTERs may also use different interfaces, which requires multiple bus controllers, and a conversion interface needs to be constructed between the two controllers, so that the whole verification system becomes very huge, which is unfavorable for the fast compiling simulation of the simulator.
Disclosure of Invention
In order to solve the above problems, the present disclosure provides an IP core simulation system and a simulation method based on a dual-port SRAM, where a design under test module (DUT) is tightly combined with a CPU and an SRAM through the dual-port SRAM to form a simulation subsystem with definite division of work and simple operation, the CPU has the dual functions of accessing the SRAM to prepare corresponding data structures for the module and accessing the module register, and the two interfaces of the dual-port SRAM can be used to perform read and write respectively, so that the arbitration process can be omitted, and both host MASTERs can directly access the SRAM to share the data of the SRAM without error due to resource competition, thereby reducing the complexity of the verification system.
In order to achieve the above purpose, the present disclosure adopts the following technical scheme:
one or more embodiments provide an IP core emulation system based on a dual-port SRAM, including a design module to be verified, a central processor, and a dual-port SRAM;
and the central processing unit: the method comprises the steps of constructing a hierarchical CPU bus function model, wherein the bus function model is used for realizing that a dual-port SRAM module is accessed to make corresponding data structures for preparing to transmit read-write data to the dual-port SRAM, and transmitting read-write commands according to a register configuration interface of a design module to be verified;
the design module to be verified: the dual-port SRAM is used for reading and writing data according to a read-write command received from a CPU;
double-port SRAM: the system is configured to realize data interaction between the CPU connected through the two interfaces and the design module to be verified.
Further, the hierarchical CPU bus functional model comprises an interface task layer, a read-write task generation layer and a simulation use case construction layer;
interface task layer: the data conversion interface is configured for data transmission among the CPU, the dual-port SRAM and the design module to be verified according to different interfaces;
a read-write task generation layer: the data conversion interface type is used for abstracting the read-write task according to the interface type and abstracting the read-write task into a read-write task corresponding to interface type conversion;
simulation use case construction layer: and acquiring a simulation case input by a user, calling a read-write task generation layer according to the simulation case, and generating simulation configuration corresponding to function verification of the design module to be verified, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to the verification function.
Further, the data conversion interface of the interface task layer includes a host bus function model respectively selected according to a register configuration interface of the design module to be verified and an interface of the dual-port SRAM, and accesses to the dual-port SRAM and the register of the design module to be verified are respectively completed through read-write tasks of two host bus function models, i.e., MASTER BFM.
Further, the selected host bus function model is not matched with the register configuration interface, a second interface conversion bridge is arranged to convert the host bus function model into a MASTER interface corresponding to the DUT register configuration interface, and connection between the DUT register configuration interface and the interface of the dual-port SRAM is established;
or alternatively
When the selected host bus function model is not matched with the interface of the dual-port SRAM, an additional first interface conversion bridge 1 is needed to convert the host bus function model into a MASTER interface corresponding to the CPU, namely, the connection between the CPU and the interface of the dual-port SRAM is established.
Further, the dual-port SRAM creation module is used for defining the storage data type of the dual-port SRAM and defining two interface relations.
Further, the stored data of the dual-port SRAM is defined as a two-dimensional array, or the two interfaces of the SRAM are in an asynchronous relationship.
An IP simulation method based on a dual-port SRAM comprises the following steps:
acquiring a simulation case aiming at a software module to be tested;
generating simulation configuration corresponding to function verification of the design module to be verified according to the simulation use case, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to the verification function;
according to the register configuration interface of the design module to be verified and the interface of the dual-port SRAM, data conversion interfaces are respectively configured for data transmission among the CPU, the dual-port SRAM and the design module to be verified;
according to the configured data conversion interface and simulation configuration, abstracting the read-write task of the CPU, abstracting the read-write task into the read-write task corresponding to the interface type conversion of the data conversion interface, and executing the read-write task to complete the simulation verification of the software module to be tested.
Further, the obtaining of the simulation use case constructs a random use case or a directional use case through the task/function of the system verilog language, or directly transplants the firmware code construction through the DPI interface.
Further, the host bus function model which is selected respectively according to a register configuration interface of the design module to be verified and an interface of the dual-port SRAM is MASTER BFM;
or alternatively
When the interface conversion can not be realized through the set MASTER BFM, a conversion bridge is set, wherein the conversion bridge comprises a first interface conversion bridge for realizing the data communication between the dual-port SRAM and the CPU and a second interface conversion bridge for realizing the data communication between the dual-port SRAM and the design module to be verified.
Further, according to the configured data conversion interface and the simulation configuration, the read-write task of the CPU is abstracted, wherein the abstracting step comprises the following steps: the configuration operation to the register and the read-write operation to the SRAM are distinguished by different addresses.
Compared with the prior art, the beneficial effects of the present disclosure are:
(1) The system and the method can be widely applied to module-level verification of the interface module, and the dual-port SRAM is utilized to replace a bus controller and an arbiter in the traditional system to realize direct access of two MASTERs to the SRAM, so that the complexity of a simulation system is greatly reduced, and the workload of verification personnel is greatly reduced.
(2) The hierarchical CPU bus function model provided by the disclosure can be continuously used only by selecting the corresponding MASTER BFM for instantiation when the module interface changes. The multiplexing of the whole verification assembly is greatly improved, different modules can use the system to quickly construct own simulation system, and the working efficiency of verification personnel is greatly improved.
(3) The method provides an alternative interface conversion module that provides a simple and portable simulation environment for verifying the selection of different DUTs and different CPUs. The verifier only needs to select the corresponding interface conversion module to be converted into an interface capable of operating the SRAM according to the data interface of the module and the interface of the CPU BFM. The independent design is convenient for a verifier to replace and recycle the interface conversion module according to different modules.
The system can be directly transplanted to the system level from the module level, and can be directly used as a BFM for the simulation use cases of the system level building module, and all the module level simulation use cases can be directly transplanted to the system level without changing, so that the verification workload of the system level to the module is greatly simplified, and precious verification time and manpower resources can be saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate and explain the exemplary embodiments of the disclosure and together with the description serve to explain and do not limit the disclosure.
FIG. 1 is a block diagram of a simulation system of embodiment 1 of the present disclosure;
FIG. 2 is a diagram of a CPU bus functional model architecture of embodiment 1 of the present disclosure;
fig. 3 is a flowchart of a simulation method of embodiment 2 of the present disclosure.
The specific embodiment is as follows:
the disclosure is further described below with reference to the drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments in accordance with the present disclosure. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof. It should be noted that, without conflict, the various embodiments and features of the embodiments in the present disclosure may be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.
Technical term interpretation:
SRAM: a Static Random-Access Memory (SRAM) is one type of Random Access Memory. By "static", it is meant that such memory is constantly maintained for data stored therein as long as it remains powered on.
CPU: (Central Processing Unit) a central processing unit.
BFM: (Bus Functional Model) bus function model.
DUT: (Design Under Test) design under test.
PHY: physical Layer interface.
The SystemVerilog is simply called SV language, is an extension enhancement of the IEEE 1364Verilog-2001 standard and is compatible with Verilog 2001, combines hardware description language with modern high-level verification language, and becomes a language for next generation hardware design and verification recently.
The design module to be verified: refers to a software module, also called an IP core, that is programmed to perform a certain function to be tested. The interface module is one type of IP core.
Example 1
In the technical scheme disclosed in one or more embodiments, as shown in fig. 1, an IP core simulation system based on a dual-port SRAM includes a design module to be verified, a central processing unit, and a dual-port SRAM;
the CPU is used for constructing a hierarchical CPU bus function model, and the bus function model is used for realizing that the dual-port SRAM module is accessed to make corresponding data structure for preparing to transmit read-write data to the dual-port SRAM, and transmitting read-write commands according to a register configuration interface of the design module to be verified;
design to be verified module, i.e., design Under Test (DUT): the dual-port SRAM is used for reading and writing data according to a read-write command received from a CPU;
double-port SRAM: is configured to enable data interaction between a CPU and a design under verification module (DUT) connected through two interfaces.
The hierarchical CPU bus function model comprises an interface task layer, a read-write task generation layer and a simulation use case construction layer.
Interface task layer: the data conversion interface is configured for data transmission among the CPU, the dual-port SRAM and the design module to be verified according to different interfaces;
optionally, the data conversion interface may include a register configuration interface according to the design module to be verified and a host bus function model that is MASTER BFM and is selected according to the interface of the dual-port SRAM, respectively; the access to the interfaces required by the two CPUs can be respectively completed through the read-write tasks of the two MASTER BFM, namely the access of the CPU to the dual-port SRAM and the register of the design module to be verified.
As a further technical scheme, when the selected host bus function model is not matched with the register configuration interface, a second interface conversion bridge is arranged to convert the host bus function model into a MASTER interface corresponding to the DUT register configuration interface, and connection between the DUT register configuration interface and the interface of the dual-port SRAM is established; or when the selected host bus function model is not matched with the interface of the dual-port SRAM, an additional first interface conversion bridge 1 is required to convert the host bus function model into a MASTER interface corresponding to the cpu, i.e. to establish connection between the cpu and the interface of the dual-port SRAM.
The host bus function model is a functional model that is used to provide functional instantiation for software testing, and may be a functional verification that has been implemented by a verifier before.
In this embodiment, two instantiations of MASTER BFM are selected to implement interface conversion: the method is used for realizing data communication of different interface types, and can also comprise the steps of providing a first interface conversion bridge 1 for the dual-port SRAM to realize data communication between the dual-port SRAM and a CPU, and providing a second interface conversion bridge 2 for the dual-port SRAM to realize data communication between the dual-port SRAM and a design module to be verified (DUT).
And selecting a second interface conversion bridge 2 according to the selected MASTER BFM for realizing data transmission of interfaces of the MASTER BFM and the SRAM, and selecting a first interface conversion bridge 1 according to a data interface of a design module DUT to be verified, wherein the two bridges are respectively connected with two interfaces of the SRAM. Thus, the CPU and the data interface of the DUT can perform random read-write operation on the content of the SRAM.
A read-write task generation layer: the interface type abstraction module is used for abstracting the read-write task according to the interface type according to the interface types of the first interface conversion bridge 1 and the second interface conversion bridge 2, and abstracting the read-write task into a read-write task corresponding to interface type conversion; the read-write behavior of the CPU is simulated, and the operation of which interface is distinguished by different offset addresses is just like the decoder of the real bus controller.
Simulation use case construction layer: and acquiring a simulation case input by a user, calling a read-write task generation layer according to the simulation case, and generating simulation configuration corresponding to function verification of the design module to be verified, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to the verification function.
The method for obtaining the simulation use cases can be flexible, and optionally, the random or directional use cases can be constructed through tasks/functions of a system verilog language, and the use cases of a firmware code construction closer to a system layer can be directly transplanted through a DPI interface, so that a verifier can select different modes according to specific situations and requirements.
The dual-port SRAM further comprises a dual-port SRAM creation module, which is used for defining the storage data type of the dual-port SRAM and defining two interface relations, and optionally, the storage data of the dual-port SRAM can be defined as a two-dimensional array, the width of the array is defined as 8 bits (1 Byte), the two interfaces of the SRAM are asynchronous relations, the two-dimensional array can be independently read and written, and the definition can be specifically W is Bit [7:0] sram_array [1024].
In other embodiments, further, the two interface relationships of the dual-port SRAM may be: the two interfaces can simultaneously perform read operation, and when the two interfaces perform write operation on the two-dimensional array at the same time, the write operation of one interface is judged to be effective.
Optionally, the IO interface of the software module under test DUT is connected to an external PHY or other module.
Example 2
The embodiment also provides an IP simulation method based on a dual-port SRAM, as shown in fig. 2 and 3, including the following steps:
step 1, obtaining a simulation case aiming at a software module to be tested;
step 2, generating simulation configuration corresponding to function verification of the design module to be verified according to a simulation use case, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to the verification function;
step 3, configuring data conversion interfaces for data transmission among the CPU, the dual-port SRAM and the design module to be verified according to the register configuration interface of the design module to be verified and the interface of the dual-port SRAM;
and step 4, abstracting a read-write task of the CPU according to the configured data conversion interface and simulation configuration, abstracting the read-write task into a read-write task corresponding to interface type conversion of the data conversion interface, and executing the read-write task to complete simulation verification of the software module to be tested.
In step 1, a simulation case for a software module to be tested is obtained, the simulation case is set by a verifier according to the functional requirements of different software modules to be tested, and the different software modules to be tested are different, so that the verifier is required to input configuration. Random or directional use cases can be constructed through tasks/functions of the system verilog language, and use cases closer to a system layer can be constructed through direct transplanting of firmware codes through a DPI interface, so that a verifier can select different modes according to specific situations and requirements.
The DPI interface is called a direct compilation interface, and SystemVerilog introduces a direct compilation interface (DPI, direct Programming Interface) that enables simpler connections C, C ++ or other non-verilog programming languages.
MASTER BFM can be mapped to C language through DPI interface, thus module simulation can be more similar to real application, and firmware driver can be transplanted directly to provide reference of more practical application for verifier construction use case.
In step 2, generating simulation configuration corresponding to function verification of the design module to be verified according to a simulation use case, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to verification functions, and the method specifically comprises the following steps:
and step 21, generating a configuration task and a read-write task for the register according to the simulation use case and the register of the software module DUT to be tested.
Step 22, generating a read-write task for the SRAM according to the simulation use case.
In step 3, the data conversion interface includes a host bus function model which can be selected respectively according to a register configuration interface of the design module to be verified and an interface of the dual-port SRAM, namely MASTER BFM; the access to the interfaces required by the two CPUs can be respectively completed through the read-write tasks of the two MASTER BFM; when the conversion of the interface cannot be realized through the set MASTER BFM, a conversion bridge may be additionally provided, as shown in fig. 2, a dual-port SRAM may be further provided to provide a first interface conversion bridge 1 to realize the data communication between the dual-port SRAM and the CPU, and a second interface conversion bridge 2 may be provided to provide a dual-port SRAM to realize the data communication between the dual-port SRAM and the design module to be verified (DUT).
And selecting a second interface conversion bridge 2 according to the selected MASTER BFM for realizing data transmission of interfaces of the MASTER BFM and the SRAM, and selecting a first interface conversion bridge 1 according to a data interface of the DUT, wherein the two bridges are respectively connected with two interfaces of the SRAM. Thus, the CPU and the data interface of the DUT can perform random read-write operation on the content of the SRAM.
In step 4, according to the configured data conversion interface and simulation configuration, abstracting a read-write task of the CPU, abstracting the read-write task into a read-write task corresponding to interface type conversion of the data conversion interface, and executing the read-write task to complete simulation verification of the software module to be tested, wherein the abstracting step comprises: the configuration operation on the register and the read-write operation on the SRAM are distinguished by different addresses, and can be completed by the same read-write task.
The method also comprises the step of creating the dual-port SRAM, wherein the step comprises the steps of defining the storage data type of the dual-port SRAM and defining two interface relations, and optionally, the storage data of the dual-port SRAM can be defined as a two-dimensional array, the width of the array is defined as 8 bits (1 Byte), the two interfaces of the SRAM are asynchronous relations, and the two-dimensional array can be independently subjected to read-write operation. The data dimension and the data width of the stored data defining the dual port SRAM may be set as required, and may be defined as a 1-dimensional array, or as a 2-bit array but the data width is not 8 bits. The SRAM is stored by taking Byte as a unit, the serial numbers of the arrays in the SRAM correspond to the addresses of the SRAM one by one, and verification personnel can conveniently and directly acquire data through the serial numbers of the arrays in the SRAM for comparison.
The foregoing description of the preferred embodiments of the present disclosure is provided only and not intended to limit the disclosure so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
While the specific embodiments of the present disclosure have been described above with reference to the drawings, it should be understood that the present disclosure is not limited to the embodiments, and that various modifications and changes can be made by one skilled in the art without inventive effort on the basis of the technical solutions of the present disclosure while remaining within the scope of the present disclosure.
Claims (6)
1. An IP core simulation system based on a dual-port SRAM is characterized in that: the system comprises a design module to be verified, a central processing unit and a dual-port SRAM;
and the central processing unit: the method comprises the steps of constructing a hierarchical CPU bus function model, wherein the bus function model is used for realizing that a dual-port SRAM module is accessed to make corresponding data structures for preparing to transmit read-write data to the dual-port SRAM, and transmitting read-write commands according to a register configuration interface of a design module to be verified;
the design module to be verified: the dual-port SRAM is used for reading and writing data according to a read-write command received from a CPU;
double-port SRAM: the system comprises a CPU, a design module to be verified and a data processing module, wherein the CPU is configured to realize data interaction through two interfaces;
the hierarchical CPU bus functional model comprises an interface task layer, a read-write task generation layer and a simulation use case construction layer; the interface task layer is used for configuring a data conversion interface for data transmission among the CPU, the dual-port SRAM and the design module to be verified according to different interfaces; a read-write task generation layer: the data conversion interface type is used for abstracting the read-write task according to the interface type and abstracting the read-write task into a read-write task corresponding to interface type conversion; simulation use case construction layer: the method comprises the steps of obtaining a simulation case input by a user, calling a read-write task generation layer according to the simulation case, and generating simulation configuration corresponding to function verification of a design module to be verified, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to verification functions;
the data conversion interface of the interface task layer comprises a register configuration interface according to a design module to be verified and a host bus function model respectively selected according to an interface of the dual-port SRAM, and accesses of the CPU to the dual-port SRAM and the register of the design module to be verified are respectively completed through read-write tasks of two host bus function models, namely MASTER BFM;
when the selected host bus function model is not matched with the register configuration interface, a second interface conversion bridge is arranged to convert the host bus function model into a MASTER interface corresponding to the DUT register configuration interface, and connection between the DUT register configuration interface and the interface of the dual-port SRAM is established;
when the selected host bus function model is not matched with the interface of the dual-port SRAM, a first interface conversion bridge is arranged to convert the host bus function model into a MASTER interface corresponding to the central processing unit, namely, the connection between the central processing unit and the interface of the dual-port SRAM is established.
2. The dual-port SRAM-based IP core emulation system of claim 1, wherein: the dual-port SRAM creation module is used for defining the storage data type of the dual-port SRAM and defining two interface relations.
3. The dual-port SRAM-based IP core emulation system of claim 1, wherein: the storage data of the dual-port SRAM is defined as a two-dimensional array, or two interfaces of the dual-port SRAM are in asynchronous relation.
4. An IP simulation method based on a dual-port SRAM, applied to the IP core simulation system based on a dual-port SRAM as set forth in any one of claims 1 to 3, comprising the steps of:
acquiring a simulation case aiming at a software module to be tested;
generating simulation configuration corresponding to function verification of the design module to be verified according to the simulation use case, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to the verification function;
according to the register configuration interface of the design module to be verified and the interface of the dual-port SRAM, data conversion interfaces are respectively configured for data transmission among the CPU, the dual-port SRAM and the design module to be verified;
according to the configured data conversion interface and simulation configuration, abstracting the read-write task of the CPU, abstracting the read-write task into the read-write task corresponding to the interface type conversion of the data conversion interface, and executing the read-write task to complete the simulation verification of the software module to be tested.
5. The method for simulating IP based on the dual-port SRAM as claimed in claim 4, wherein the method comprises the following steps: the acquisition of the simulation use case constructs a random use case or a directional use case through tasks/functions of a system verilog language, or directly transplants firmware code construction through a DPI interface.
6. The method for simulating IP based on the dual-port SRAM as claimed in claim 4, wherein the method comprises the following steps:
abstracting a read-write task of the CPU according to the configured data conversion interface and the simulation configuration, wherein the abstracting step comprises the following steps: the configuration operation to the register and the read-write operation to the SRAM are distinguished by different addresses.
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| WO2021087528A1 (en) * | 2020-06-15 | 2021-05-06 | Zeku, Inc. | Data stack mips analysis tool for data plane |
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