CN100549772C - LCD and method of testing thereof - Google Patents

Abstract

The present invention provides a liquid crystal display, which includes a plurality of pixel electrodes arranged in a matrix and having first sub-pixels and second sub-pixels with different sizes from each other. A first switching element and a second switching element are respectively connected to the first sub-pixel electrode and the second sub-pixel electrode. The first gate line and the second gate line are respectively connected to the first switching element and the second switching element. The data line is connected to the first switching element and the second switching element to transmit data voltage. The first gate short bar and the second gate short bar are respectively connected to the first gate line and the second gate line. The gate line connected to each sub-pixel is connected to two or four gate shorting bars for array test and visual inspection test, thereby detecting the electric bridge between electrodes of each adjacent sub-pixel in a simple way.

Description

Liquid crystal display and its test method

This application claims the benefit of Korean Patent Application No. 2005-0014578 filed on February 22, 2005 and Korean Patent Application No. 2005-0047262 filed on June 2, 2005, the entire contents of which are hereby incorporated by reference.

technical field

The invention relates to a liquid crystal display and a testing method of the liquid crystal display. More specifically, the present invention relates to a liquid crystal display and a testing method thereof, which can easily detect electric bridges formed between sub-pixel electrodes and data lines of the liquid crystal display.

Background technique

A liquid crystal display ("LCD") is a widely used flat-panel display device that includes two display panels on which field-induced electrodes such as pixel electrodes and common electrodes are mounted, and a liquid crystal layer interposed between the electrodes. . The LCD generates an electric field in the LC layer by applying a voltage to the field-generating electrodes, and aligns liquid crystal molecules in the liquid crystal layer to adjust the polarization of incident light, thereby displaying desired images.

Various tests should be performed to detect wire breaks or shorts during LCD manufacturing, such as open/short (“OS”) testing, array testing, visual inspection testing (“VI”), gross testing, and module testing .

During the process of manufacturing a thin film transistor ("TFT"), when the source electrode and the drain electrode on the first panel in the LCD are separated from each other, an OS test is performed to detect a disconnection of a signal line or a short circuit of a TFT by applying a predetermined voltage . Before the motherglass is divided into a plurality of cells, an array test is performed to detect a disconnection of a display signal line by applying a predetermined voltage and identifying the presence or absence of an output voltage. After dividing the plain glass into a plurality of units and combining the upper panel and the lower panel with each other, a VI test is performed to visually detect a disconnection of a display signal line by applying a predetermined voltage. Before installing the driving circuit, conduct a rough test to detect the quality of the display image and the disconnection of the display signal line by applying the same voltage as the actual driving voltage and identifying the state of the display screen. After the driver circuit is installed, a module test is performed to finally check the optimal operation of the driver circuit.

A vertical alignment ("VA") mode LCD is an LCD in which liquid crystal molecules are oriented vertically to upper and lower panels without an applied electric field, which provides high contrast and a wide reference viewing angle. The reference viewing angle refers to a viewing angle with a contrast ratio of 1:10 or a critical angle for luminance inversion of a middle gray scale.

According to a VA mode LCD, cutouts or protrusions may be formed on the field electrodes to realize a wide viewing angle. Since the directions of the inclined liquid crystal molecules are determined by the cutouts or protrusions, the inclined directions of the liquid crystal molecules are made different, thereby widening the reference viewing angle.

However, a VA mode LCD has poor visibility on its side compared to its front visibility. For example, in the case of a patterned vertical orientation ("PVA") mode LCD with cutouts, its brightness is enhanced as it reaches its sides, and in severe cases, the brightness difference between high gray levels is eliminated, thereby The displayed image may appear distorted.

In order to enhance the visibility of the sides, it has been proposed that each pixel should be divided into two sub-pixels, while the sub-pixels in each pixel receive different voltages. However, when the electrodes of the sub-pixels are patterned during the manufacturing process of the LCD, a bridge may be formed so that the bridges interconnect the sub-pixel electrodes or adjacent data lines. From a circuit point of view, this means that those electrodes or data lines are shorted to each other. Therefore, the same voltage is applied to each sub-pixel instead of different voltages, thereby degrading the quality of the displayed image.

Contents of the invention

When electrodes or data lines are shorted by connections, the bridge formed should be detected by conducting various tests. Accordingly, the present invention provides a liquid crystal display ("LCD") and a method for testing an LCD that can easily detect bridges formed between sub-pixel electrodes and data lines.

The present invention provides an LCD having the following characteristics and a testing method thereof.

According to an exemplary embodiment of the present invention, the LCD includes a plurality of pixel electrodes arranged in a matrix, each pixel electrode has a first sub-pixel and a second sub-pixel with different sizes; and is connected to the first sub-pixel electrode and the second sub-pixel respectively. The first switch element and the second switch element of the two sub-pixel electrodes. The first gate line and the second gate line are respectively connected to the first switching element and the second switching element. The data line is connected to the first switching element and the second switching element and transmits a data voltage. The first gate short bar and the second gate short bar are respectively connected to the first gate line and the second gate line.

A first gate test signal and a second gate test signal different from each other may be applied to the first gate short bar and the second gate short bar, respectively.

Positive data voltages may be applied to the data lines in the case of applying the first gate test signal, and negative data voltages may be applied to the data lines in the case of applying the second gate test signal.

The positive data voltage and the negative data voltage may have substantially the same magnitude.

The data short bars may be connected to the data lines, and may be formed in the same layer of the LCD as the first and second gate lines.

The shielding electrode may overlap the data line, and may be disposed between two adjacent pixel electrodes.

The shield electrode may overlap at least one of the first and second gate lines.

The magnitudes of the data voltages applied to the first subpixel electrode and the second subpixel electrode may be different from each other, and may be obtained from one image information group.

The size of the first subpixel electrode may be larger than that of the second subpixel electrode, and the magnitude of the data voltage applied to the first subpixel electrode may be smaller than the magnitude of the data voltage applied to the second subpixel electrode.

The first and second gate short bars may be formed in the same layer of the liquid crystal display as the data lines, and may be substantially parallel to the data lines.

The first gate shorting bar and the second gate shorting bar may be outside the edge of the LCD display panel.

The LCD may further include gate pads respectively connected to the first gate line and the second gate line, and gate pads respectively connected to the first gate shorting bar and the second gate shorting bar. pole extension line.

According to other exemplary embodiments of the present invention, the LCD includes a plurality of pixel electrodes arranged in a matrix, each pixel electrode has a first sub-pixel and a second sub-pixel with different sizes from each other; and is connected to the first sub-pixel and the second sub-pixel respectively. The first switching element and the second switching element of the second sub-pixel. The first gate line and the second gate line are respectively connected to the first switching element and the second switching element. The data line is connected to the first switching element and the second switching element and transmits a data voltage. The first gate short bar and the second gate short bar are connected to the first gate line and the second gate line in the odd pixel row. The third gate short bar and the fourth gate short bar are connected to the first gate line and the second gate line in the even pixel rows.

The first to fourth gate test signals may be respectively applied to the first to fourth gate shorting bars.

A positive data voltage may be applied to the data line while applying the first gate test signal and a fourth gate test signal, and a negative data voltage may be applied while applying the second gate test signal and the third gate test signal. down is applied to the data lines.

According to other exemplary embodiments of the present invention, a method for testing an LCD is provided, and the LCD includes: a plurality of pixel electrodes having a first sub-pixel electrode and a second sub-pixel electrode; a first switching element and a second switch elements, respectively connected to the first sub-pixel electrode and the second sub-pixel electrode; the first gate line and the second gate line, respectively connected to the first switching element and the second switching element; and connected to the first switching element and The data line of the second switching element. The test method includes: providing a first gate shorting bar and a second gate shorting bar, which are respectively connected to the first gate line and the second gate line; providing a data shorting bar, which is connected to the data line; applying a positive data voltage to the bar; applying a first gate test signal to the first gate shorting bar to apply a positive data voltage to the first sub-pixel electrode; applying a negative voltage to the data shorting bar; and applying a negative voltage to the second gate shorting bar The second gate test signal to apply a negative data voltage to the second sub-pixel electrode.

The method may further include detecting polarities of the first subpixel electrode and the second subpixel electrode, such as by performing an array test.

The method may further include identifying the presence of a bridge between the first subpixel electrode and the second subpixel electrode, wherein the positive pixel voltage and the negative pixel voltage of the first subpixel electrode and the second subpixel electrode having the bridge are within It cannot be supplied continuously when positive data voltage and negative data voltage are applied.

The method may further include inspecting the brightness uniformity of the LCD, such as by performing a visual inspection test.

The method may further include identifying a gap between the first sub-pixel electrode and the second sub-pixel electrode when the luminance of the pixel with the bridge first sub-pixel and the second sub-pixel is different from the luminance of other pixels without the bridge. presence of the bridge.

The method may further include identifying the presence of a bridge between the first subpixel electrode and the shield electrode.

The method may further include separating the first gate shorting bar and the second gate shorting bar from the first gate line and the second gate line, and separating the data shorting bar from the data line.

According to other exemplary embodiments of the present invention, a method for testing an LCD is provided, and the LCD includes: a plurality of pixel electrodes having a first sub-pixel electrode and a second sub-pixel electrode; a first switching element and a second switch elements, respectively connected to the first sub-pixel electrode and the second sub-pixel electrode; the first gate line and the second gate line, respectively connected to the first switching element and the second switching element; and connected to the first switching element and The data line of the second switching element. The test method includes: providing a first gate shorting bar and a second gate shorting bar, which are respectively connected to the first gate line and the second gate line in the odd pixel row; providing the third gate shorting bar and the second gate shorting bar Four gate shorting bars, which are respectively connected to the first gate line and the second gate line in the even pixel row; provide data shorting bars, which are connected to the data lines; apply a positive data voltage to the data shorting bars; The gate short bar applies the first gate test signal to apply the positive data voltage to the first sub-pixel electrode in the odd pixel row; the negative data voltage is applied to the data short bar; the second gate short bar and the third gate The shorting bar applies the second gate test signal and the third gate test signal to apply a negative data voltage to the second sub-pixel electrodes in the odd pixel rows and the first sub-pixel electrodes in the even pixel rows; and apply a negative data voltage to the fourth gate The pole-shorting bar applies a fourth gate test signal to apply a positive data voltage to the second sub-pixel electrode in the even-numbered pixel row.

The method may further include detecting polarities of the first subpixel electrode and the second subpixel electrode.

The method may further include identifying the presence of a bridge between the first subpixel electrode and the second subpixel electrode.

The method may further include identifying the presence of a bridge between the first sub-pixel electrodes of adjacent electrodes.

The positive data voltage and the negative data voltage may have substantially the same magnitude.

The method may further include detecting brightness uniformity of the LCD.

The method may further include separating the first and second gate shorting bars from the first and second gate lines in odd pixel rows, and separating the third and fourth gate shorting bars from the first and second gate lines in even pixel rows. The second gate line is separated, and the data short bar is separated from the data line.

According to an exemplary embodiment of the present invention, the LCD includes a plurality of pixel electrodes arranged in a matrix, and each pixel electrode has a first sub-pixel electrode and a second sub-pixel electrode with different sizes from each other; and is respectively connected to the first sub-pixel electrode and the first switching element and the second switching element of the second sub-pixel electrode. The gate line is connected to the first switching element and the second switching element. The first and second data lines cross the gate lines and are connected to the first and second switching elements, respectively. The first data short bar and the second data short bar are respectively connected to the first data line and the second data line.

Data voltages of different polarities from each other may be applied to the first and second data shorting bars.

The data voltages having polarities different from each other may have substantially the same magnitude.

A gate shorting bar may be connected to the gate line.

The magnitudes of the data voltages applied to the first subpixel electrode and the second subpixel electrode may be different from each other, and may be obtained from one image information group.

The size of the first subpixel electrode may be larger than that of the second subpixel electrode, and the magnitude of the data voltage applied to the first subpixel electrode is smaller than the magnitude of the data voltage applied to the second subpixel electrode.

The first data short bar and the second data short bar may be formed in the same layer of the liquid crystal display as the gate lines.

The first data shorting bar and the second data shorting bar may be substantially parallel to the gate lines.

The first data short bar and the second data short bar may be outside the edge of the LCD display panel.

According to other exemplary embodiments of the present invention, a method for testing an LCD is provided, and the LCD includes: a plurality of pixel electrodes having a first sub-pixel electrode and a second sub-pixel electrode; a first switching element and a second switch element, respectively connected to the first sub-pixel electrode and the second sub-pixel electrode; the gate line, respectively connected to the first switching element and the second switching element; and the first data line and the second data line, respectively connected to the first a switching element and a second switching element. The test method includes: providing a first data shorting bar and a second data shorting bar, which are connected to the first data line and the second data line; providing a gate shorting bar, which is connected to the gate line; applying a positive data voltage; applying a negative data voltage to the second data shorting bar; applying a gate test signal to the gate shorting bar to apply a positive data voltage to the first sub-pixel electrode and a negative data voltage to the second sub-pixel electrode.

The method includes testing the brightness uniformity of the LCD.

The method may further include identifying the presence of a bridge between the first data line and the second data line.

The method may further include identifying the presence of a bridge between the first subpixel electrode and the second subpixel electrode.

The positive data voltage and the negative data voltage have substantially the same magnitude.

The method may further include separating the first and second data short bars from the first and second data lines, and separating the gate short bars from the gate lines.

Description of drawings

The present invention will become more apparent by describing in detail embodiments with reference to the accompanying drawings, in which:

1 is a schematic diagram of an exemplary embodiment of an LCD according to the present invention;

2 is an equivalent circuit diagram of an exemplary pixel of an exemplary embodiment of an LCD according to the present invention;

3 is an equivalent circuit diagram of an exemplary subpixel of an exemplary embodiment of an LCD according to the present invention;

4 is a plan view of an exemplary embodiment of an LCD according to the present invention;

5 and 6 are cross-sectional views of an exemplary embodiment of an LCD taken along lines V-V' and lines VI-VI' of FIG. 4;

7 is an enlarged view of an exemplary gate shorting bar of the exemplary embodiment of the LCD shown in FIG. 1;

8 is a cross-sectional view of an exemplary embodiment of an LCD taken along line VIII-VIII' of FIG. 7;

9 is a test waveform diagram of an exemplary embodiment of an LCD according to the present invention;

Figure 10 shows the polarity of an exemplary pixel according to an exemplary embodiment of an LCD of the present invention;

11 is a schematic diagram of another exemplary embodiment of an LCD according to the present invention;

12 is an enlarged view of an exemplary gate shorting bar of the exemplary embodiment of the LCD shown in FIG. 11;

13 is a test waveform diagram of another exemplary embodiment of an LCD according to the present invention;

Fig. 14 shows the polarity of the pixel according to another exemplary embodiment of the LCD of the present invention;

15 is a schematic diagram of another exemplary embodiment of an LCD according to the present invention;

16 is an equivalent circuit diagram of an exemplary pixel of another exemplary embodiment of an LCD according to the present invention;

17 is a plan view of another exemplary embodiment of an LCD according to the present invention;

18 is a cross-sectional view of an exemplary embodiment of an LCD taken along line XVIII-XVIII' of FIG. 17;

19 is an enlarged view of an exemplary data shorting bar of the exemplary embodiment of the LCD shown in FIG. 15;

20 is a cross-sectional view of an exemplary embodiment of an LCD taken along line XX-XX' of FIG. 19;

21 is a test waveform diagram of another exemplary embodiment of an LCD according to the present invention; and

FIG. 22 shows polarities of exemplary pixels according to another exemplary embodiment of an LCD of the present invention.

Detailed ways

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention can be implemented in many different ways and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will fully disclose and fully cover the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout the drawings of the specification. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

It will be understood that when an element or layer is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present therebetween. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections are not limited to these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Therefore, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit of the present invention.

The terms used herein are for describing particular embodiments only and do not limit the present invention. As used herein, the singular forms "a", "the" and "the" also include plural forms, unless the context clearly indicates otherwise. It should be further understood that when the terms "comprising" and/or "comprising" are used in this application document, it means that there are claimed features, integers, steps, operations, elements, and/or parts, but it does not exclude the presence of Or additional one or more other features, integers, steps, operations, elements, parts, and/or combinations thereof.

For ease of description, spatial relational terms such as "under", "beneath", "beneath", "above", and "above" may be used herein, To describe the relationship of one element or mechanism to another element or mechanism as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" encompasses an orientation of above as well as below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationships described herein interpreted accordingly.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. For a further understanding of the term, for example, defined terms commonly used in dictionaries should be interpreted as meanings consistent with the meanings in the relevant technical context, and unless specifically defined here, they should not be interpreted as ideal or too formal explanation.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the invention. Also, it is contemplated that factors such as manufacturing techniques and/or tolerances may cause variations in the illustrations. Thus, embodiments of the invention should not be construed as limited to the particular shapes shown herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat, will, typically, have rough and/or non-linear characteristics. Additionally, sharp corners shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the invention.

Hereinafter, an exemplary embodiment of an LCD according to the present invention and a testing method thereof will be described with reference to the accompanying drawings.

1 is a schematic diagram of an exemplary embodiment of an LCD according to the present invention, FIG. 2 is an equivalent circuit diagram of an exemplary pixel of an exemplary embodiment of an LCD according to the present invention, and FIG. 3 is an exemplary implementation of an LCD according to the present invention. The equivalent circuit diagram of an exemplary sub-pixel of the example.

As shown in FIG. 1 , an exemplary embodiment of an LCD includes a liquid crystal panel assembly, which has a plurality of display signal lines G1a-Gnb and D1-Dm from the viewpoint of an equivalent circuit; and a plurality of pixels PX, roughly arranged in a matrix form and connect to display signal lines G1a-Gnb and D1-Dm. According to the structure shown in FIG. 3 , the liquid crystal display panel assembly includes a lower panel 100 and an upper panel 200 and a liquid crystal layer 3 between the panels 100 and 200 . The lower panel 100 may also be called a thin film transistor ("TFT") panel or a first panel, and the upper panel 200 may also be called a common electrode panel, a color filter panel, or a second panel.

Display signal lines G1a-Gnb and D1-Dm are provided on the lower panel 100, which has a plurality of gate lines G1a-Gnb for transmitting gate signals (also referred to as “scanning signals”) and a plurality of gate lines G1a-Gnb for transmitting data signals. Data lines D1-Dm. The gate lines G1-Gn extend along the direction of pixel rows, which are substantially parallel to each other in a first direction, and the data lines D1a-Dmb extend along the direction of pixel columns, which are substantially parallel to each other in a second direction. The first direction may be substantially perpendicular to the second direction.

The liquid crystal display panel assembly further includes gate pads PG1a-PGnb respectively connected to the gate lines G1a-Gnb and data pads PD1-PDm respectively connected to the data lines D1-Dm. That is, each gate line G1a-Gnb is connected to one gate pad PG, and each data line D1-Dm is connected to one data pad PD. The first gate shorting bar 320a and the second gate shorting bar 320b are connected to the corresponding gate pads PG1-PGnb, and the data shorting bar 310 is connected to the respective data pads PD1-PDm.

The first gate short bar 320a is connected to the first gate pads PG1a, PG2a, PG3a, ... through the first gate extension lines (gate extension line) 321a, 322a, 323a, ..., and the second gate The pole shorting bar 320b is connected to the second gate pads PG1b, PG2b, . . . through the second gate extension lines 321b, 322b, . . . The first gate shorting bar 320a and the second gate shorting bar 320b may extend substantially perpendicular to the gate lines G1a-Gnb and substantially parallel to the data lines D1-Dm. The data short bar 310 is connected to the data pads PD1, PD2, PD3, . . . through the data extension lines 311, 312, 313, . . . The data short bars 310 may extend substantially perpendicular to the data lines D1-Dm and substantially parallel to the gate lines G1a-Gnb. Thus, the respective first gate lines G1a-Gna are connected to each other through the first gate shorting bar 320a, and the respective second gate lines G1b-Gnb are connected to each other through the second gate shorting bar 320b. In addition, the respective data lines D1 - Dm are connected to each other through data short bars 310 . Separate pads (not shown) are provided at the ends of the gate shorting bars 320a and 320b and the data shorting bar 310 to apply various test signals, which will be further described below.

The gate shorting bars 320a and 320b, and the data shorting bar 310 are subjected to several tests and then removed along their LX lines. That is, elements in the interior of the LX edge are reserved for the LCD, and elements outside the LX edge, such as the first gate shorting bar 320a, the second gate shorting bar 320b, and the data shorting bar 310, are removed. Therefore, by removing the shorting bars 320a, 320b, and 310, the respective gate lines G1a-Gnb and the data lines D1-Dm are separated from each other. A gate driver (not shown) and a data driver (not shown) are externally connected to the gate pads PG1a-PGnb and the data pads PD1-PDm to apply gate signal and data signal. However, in the case that the gate driver is integrated into the liquid crystal panel assembly, the gate pads may be omitted when extending the gate extension lines 321a, 321b, 322a, 322b, . . . from the gate driver.

2 shows an equivalent circuit diagram of display signal lines and an exemplary pixel PX, wherein the display signal lines include gate lines denoted by GLa and GLb, data lines denoted by DL, and gate lines almost parallel to the gate lines GLa and GLb. The storage electrode line SL that extends and divides the pixels Px.

Each pixel Px includes a pair of subpixels Pxa and Pxb, each having switching elements Qa and Qb connected to corresponding gate lines GLa and GLb and data line DL; liquid crystal capacitors C _Lca and C _LCb connected to the switching elements Qa and Qb; storage capacitors C _STa and C _STb connected to switching elements Qa and Qb; and a storage electrode line SL. In alternative embodiments, the storage capacitors C _STa and C _STb may be omitted, and in this case, the storage electrode line SL may be omitted.

As shown in FIGS. 1 and 2 , all of the first gate lines GLa are connected to the first gate shorting bar 320a, and all of the second gate lines GLb are connected to the second gate shorting bar 320b. Thus, the same signal can be applied to each first subpixel Pxa, and the same signal can be applied to each second subpixel Pxb, however, the signal applied to the first subpixel Pxa can be different from that applied to the second subpixel Pxa. The signal of the sub-pixel Pxb will be further described below.

As shown in FIG. 3 , the switching elements Q of the respective sub-pixels Pxa and Pxb are formed with a TFT formed on the lower panel 100, which is a triode device having a control terminal (gate) connected to the gate line GL, connected to The input terminal (source) of the data line DL, and the output terminal (drain) connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST . While only one sub-pixel Pxb is shown in FIG. 3 , it should be understood that each pixel PX also includes a sub-pixel Pxa as shown in FIG. 2 above.

The liquid crystal capacitor C _LC uses the sub-pixel electrode PE of the lower panel 100 and the common electrode CE of the upper panel 200 as two terminals. The liquid crystal layer 3 located between the two electrodes PE and CE acts as a dielectric. The subpixel electrode PE is connected to the switching element Q, and the common electrode CE is formed on the entire surface, or substantially the entire surface, of the upper panel 200 to receive the common voltage Vcom. Optionally, the common electrode CE may also be provided at the lower panel 100, and in this case, at least one of the two electrodes PE and CE is formed in a wire or rod shape.

Regarding the storage capacitor C _ST of the auxiliary liquid crystal capacitor, the storage electrode line SL and the pixel electrode PE provided on the lower panel 100 overlap each other while interposing an insulator, and a predetermined voltage such as a common voltage Vcom is applied to the storage electrode line SL. Optionally, when an insulator is interposed, a storage capacitor can be formed by overlapping the sub-pixel electrode PE with the closest front-end gate line.

In order for the liquid crystal panel assembly to display colors, each pixel can either inherently exhibit one of the primary (primary) colors (spatial division) or selectively exhibit the primary colors in temporal order (time division) so that the spatial and the sum over time to see the desired color. Primary colors preferably include red, green, and blue, however, alternative colors are also within the scope of these embodiments. FIG. 3 shows an example of time division, where each pixel has a color filter CF exhibiting one of the primary colors in the area of the upper panel 200 . In alternative embodiments, the color filter CF may be formed on or under the sub-pixel electrode PE of the lower panel 100 .

Referring to FIGS. 4 to 6, the structure of the LCD will be further described.

4 is a plan view of an exemplary embodiment of an LCD according to the present invention, and FIGS. 5 and 6 are cross-sectional views of the exemplary embodiment of the LCD taken along lines V-V' and VI-VI' of FIG. 4 .

The LCD shown in FIGS. 4 to 6 includes a lower panel 100 , an upper panel 200 facing the lower panel 100 , and a liquid crystal layer 3 between the panels 100 and 200 .

First, the lower panel 100 will be further described.

The insulating substrate 110 based on transparent glass or plastic is covered by a plurality of pairs of first and second gate lines 121 a and 121 b and a plurality of storage electrode lines 131 .

The gate lines 121a and 121b extend horizontally, such as in a lateral direction or a first direction, and are physically-electrically separated from each other to transmit gate signals. The first gate line 121a and the second gate line 121b include a plurality of portions that deviate from the longitudinal direction of the first gate line 121a and the second gate line 121b and have end portions 129a and 129b of left wide areas, with To connect the plurality of first gate electrodes 124a and 124b protruding from the first gate line 121a and the second gate line 121b to another layer or an external driving circuit. Optionally, the ends 129a and 129b may be arranged on the left and right sides, for example alternately, or both are only arranged on the right side.

The storage electrode line 131 also extends horizontally substantially parallel to the first gate line 121a and the second gate line 121b, and is closer to the first gate line 121a than to the second gate line 121b. Each storage electrode line 131 includes a plurality of storage electrodes 137 protruding from the storage electrode line 131 and having a wide area. The storage electrode 137 may be rectangular in shape and symmetrical to the storage electrode line 131 . A predetermined voltage, such as a common voltage applied to the common electrode 270 of the upper panel 200 of the LCD, is applied to the storage electrode line 131 .

The gate lines 121a and 121b and the storage electrode lines 131 are made of aluminum-based metal materials such as aluminum (Al) and aluminum alloys, silver-based metal materials such as silver (Ag) and silver alloys, copper (Cu) and copper alloys. Copper-based metal materials, molybdenum (Mo) and molybdenum-based metal materials of molybdenum alloys, chromium (Cr), titanium (Ti), or tantalum (Ta) are formed. Alternatively, the gate lines 121a and 121b and the storage electrode line 131 may have a multilayer structure with two conductive layers (not shown) having different physical properties. If a multilayer structure is adopted, one layer of the conductive layer may be formed of a low-resistivity metal material such as an aluminum-based metal material, a silver-based metal material, and a copper-based metal material, whereby the gate line 121a and the gate line 121a can be reduced. 121b and the signal delay or voltage drop of the storage electrode line 131. Conversely, another conductive layer in the multilayer structure may be formed of a material having good contact characteristics relative to other materials such as indium tin oxide ("ITO") or indium zinc oxide ("IZO"), such as a molybdenum-based metallic material , chromium, titanium, and tantalum. Examples of such combinations include structures with a chromium-based lower panel and an aluminum-based upper panel, and structures with an aluminum-based lower panel and a molybdenum-based upper panel. Although specific embodiments and examples have been described, the gate lines 121a and 121b and the storage electrode line 131 may also be formed of various other metal materials and conductors.

Sides of the gate lines 121a and 121b and the storage electrode lines 131 are inclined with respect to the surface of the insulating substrate 110, and the inclination angle thereof is preferably between about 30° and about 80°.

A gate insulating layer 140 is formed on the gate lines 121 a and 121 b and the storage electrode line 131 , and may be further formed on the exposed portion of the insulating substrate 110 . The gate insulating layer 140 may be formed of silicon nitride (SiNx) or the like.

A plurality of island-shaped semiconductors 154 a , 154 b and 156 having hydrogenated amorphous silicon (“a-Si”) are formed on the gate insulating layer 140 . Semiconductors 154a and 154b are formed on the gate electrodes 124a and 124b, respectively. A semiconductor 156 is formed on the gate lines 121 a and 121 b and the storage electrode line 131 .

A plurality of island-shaped ohmic contacts 163a, 165a, and 166 having n+ hydrogenated a-Si doped with high-concentration n-type impurities such as silicide and phosphorus are formed on the semiconductors 154a, 154b, and 156 . A pair of first ohmic contacts 163a and 165a and a pair of second ohmic contacts (not shown) are respectively disposed on the semiconductors 154a and 154b and separated from each other to form channels on the semiconductors 154a and 154b.

Sides of the semiconductors 154a, 154b and 156 and the ohmic contacts 163a, 165a and 166 are inclined with respect to the surface of the insulating substrate 110, and the inclination angle thereof is preferably in a range of about 30° to about 80°.

A plurality of data lines 171 and pairs of drain electrodes 175 a and 175 b separated from the data lines 171 are formed on the ohmic contacts 163 a , 165 a , 166 and the gate insulating layer 140 .

The data line 171 extends vertically, such as in a longitudinal or second direction, so as to cross the gate lines 121a and 121b and the storage electrode line 131 to transmit the data voltage thereto. The data line 171 is insulated from the gate line by the gate insulating layer 140 disposed between the gate lines 121a and 121b. Each data line 171 includes a plurality of first source electrodes 173a and second source electrodes 173b respectively extending toward the first drain electrode 175a and the second drain electrode 175b and an end portion 179 with an enlarged width for communicating with another layers or external devices such as data driver circuits.

The first drain electrode 175a and the second drain electrode 175b extend toward the storage electrode 137 from rod-shaped end portions located above the semiconductors 154a and 154b in the first direction and the second direction, and have a wide extension overlapping the storage electrode 137. ) 177a and 177b. The respective source electrodes 173a and 173b are bent so that they surround the rod-shaped ends of the drain electrodes 175a and 175b. The first gate electrode 124a and the second gate electrode 124b, the first source electrode 173a and the second source electrode 173b, and the first drain electrode 175a and the second drain electrode 175b together with the semiconductors 154a and 154b form a first thin film transistor (“TFT”). ”) Qa and the second thin film transistor Qb. Channels of the TFTs Qa and Qb are formed on the semiconductors 154a and 154b between the first and second source electrodes 173a, 173b and the first and second drain electrodes 175a, 175b and between the island-shaped ohmic contacts 163a and 165a.

The data line 171 and the drain electrodes 175a, 175b are preferably formed of a chromium-based metal material, a molybdenum-based metal material, or a refractory metal material such as tantalum and titanium, and may have a multilayer structure including refractory-based A lower layer (not shown) of molten metal and an upper layer (not shown) formed of a low resistance material on the lower layer. Examples of the multilayer structure include, but are not limited to, a three-layer structure having a molybdenum layer-aluminum layer-molybdenum layer in addition to a two-layer structure having a chromium or molybdenum-based lower layer and an aluminum-based upper layer. However, the data line 171 and the drain electrodes 175a, 175b may be made of various metals or conductors.

Like the gate lines 121a and 121b and the storage electrode lines 131, the sides of the data lines 171 and the drain electrodes 175a and 175b have inclined side profiles with respect to the surface of the insulating substrate 110, and the inclination angle thereof is between about 30° to about 80°. ° between.

The ohmic contacts 163a, 163b, 165a, 165b and 166 are only interposed between the lower semiconductors 154a, 154b and 156 and the overlying data line 171 and the drain electrodes 175a and 175b to reduce the contact resistance therebetween. The semiconductors 154a and 154b have portions exposed through the source electrodes 173a and 173b and the drain electrodes 175a and 175b. Furthermore, as described above, the semiconductor 156 is formed in the region where the gate lines 121a, 121b intersect the storage electrode line 131 and the data line 171 and the region where the drain electrodes 175a, 175b intersect the storage electrode 137, so that outside those intersecting regions The pattern is smooth and prevents the intersection of the data line 171 and the drain electrodes 175a, 175b.

A passivation layer 180 is formed on the data line 171, the drain electrodes 175a, 175b, and exposed portions of the semiconductors 154a and 154b. As shown, a passivation layer 180 may be further formed on the exposed portion of the gate insulating layer 140 . The passivation layer 180 is formed of an inorganic material based on silicon nitride or silicon oxide, an organic material having good flattening characteristics and photosensitivity, or a material such as a-Si :C:O and a-Si:O:F are formed of low dielectric insulating materials. Alternatively, the passivation layer 180 may have a double-layer structure having a lower inorganic layer and an upper inorganic layer to protect exposed portions of the semiconductors 154a and 154b while ensuring good characteristics of the organic layer.

A plurality of contact holes 182, 187a and 187b are formed at the passivation layer 180 to expose the end 179 of the data line 171 and the extensions 177a and 177b of the drain electrodes 175a and 175b. A plurality of contact holes 181a and 181b are formed at the passivation layer 180 and the gate insulating layer 140 to expose end portions 129a and 129b of the gate lines 121a and 121b.

A plurality of pixel electrodes 190 having first and second subpixels 190 a and 190 b , a plurality of shield electrodes 88 , and a plurality of contact assistants 81 a , 81 b , and 82 are formed on the passivation layer 180 . The pixel electrode 190, the shield electrode 88, and the contact assistants 81a, 81b, and 82 are formed of a transparent conductive material such as ITO or IZO, or a reflective conductive material for a reflective LCD such as aluminum.

The first sub-pixel electrode 190a and the second sub-pixel electrode 190b are physically-electrically connected to the first drain electrode 175a and the second drain electrode 175b through the contact holes 187a and 187b, so as to receive signals from the first drain electrode 175a and the second drain electrode 175b. data voltage. With respect to one input image signal, predetermined voltages different from each other are applied to a pair of subpixel electrodes 190a and 190b, and their dimensions are determined according to the shape and size of the subpixel electrodes 190a and 190b. In addition, regions of the subpixel electrodes 190a and 190b may be different from each other. For example, the second subpixel electrode 190b receives a higher voltage than the first subpixel electrode 190a, and has a smaller area than the first subpixel electrode 190a.

According to the received data voltage, the sub-pixel electrodes 190a and 190b generate an electric field together with the common electrode 270 of the opposite panel 200 supplied with a common voltage, and adjust the liquid crystal in the liquid crystal layer 3 between the two electrodes 190a and 190b and the common electrode 270 molecular.

As described above, the subpixel electrodes 190a and 190b and the common electrode 270 form liquid crystal capacitors C _LCa and C _LCb to maintain the voltage applied thereto even after the TFTs Qa and Qb are turned off. The storage capacitors C _STa and C _STb are arranged in parallel to the liquid crystal capacitors C _LCa and C _LCb to enhance the voltage storage capacity. Storage capacitors _CSTa and _CSTb are formed by overlapping the first subpixel electrode 190a, the second subpixel electrode 190b with the drain electrodes 175a, 175b and the storage electrode 137 connected thereto.

Each pixel electrode 190 is chamfered or edge-cut at its right corner, and the angle of the cut-leg relative to the gate lines 121a and 121b is about 45°.

When the gap 94 is inserted, a pair of the first subpixel electrode 190a and the second subpixel electrode 190b forming one pixel electrode 190 are joined to each other, and the outer shape of the pixel electrode 190 is approximately rectangular. The shape of the second sub-pixel electrode 190b is a rotated equilateral trapezoid, which has a concave bottom surface of the trapezoid. The second subpixel electrode 190b is mostly surrounded by the first subpixel electrode 190a, that is, the second subpixel electrode 190b falls into the first subpixel electrode 190a. The first subpixel electrode 190a is formed of an upper trapezoid, a lower trapezoid, and a middle trapezoid connected to each other on the left side thereof. The first sub-pixel 190a has a pair of cutouts 91a and 91b extending from the top side of the upper trapezoid and the bottom side of the lower trapezoid to its right side. The cutout 91a is formed of two sub-cutouts separated from each other at a region joined to the first gate line 121a. The central trapezoid of the first subpixel electrode 190a is installed in the concave bottom surface of the second subpixel electrode 190b. The first sub-pixel electrode 190a has a slit 92 extending along the storage electrode line 131, and the slit 92 has an entrance for a pixel on the left side of the first sub-pixel electrode 190a adjacent to the data line 171, and a horizontally extending horizontally from the entrance. part. The entrance of the cutout 92 has a pair of legs forming an angle of about 45° with the storage electrode line 131 . The gap 94 between the first sub-pixel electrode 190a and the second sub-pixel electrode 190b has two pairs of upper inclined portions having the same width at an angle of about 45° to the first gate line 121a and the second gate line 121b and a lower sloping portion, and three vertical portions of substantially the same width. For ease of description, gap 94 may also be referred to as a cutout.

The pixel electrode 190 has cutouts 91 a , 91 b and 92 , and is divided into a plurality of regions by the cutouts 91 a , 91 b and 92 and gaps 94 . The cutouts 91 a , 91 b and 92 obliquely extend from the left side to the right side of the pixel electrode 190 and are mirror-symmetrical to the storage electrode line 131 . The cutouts make an angle of about 45° with the gate lines 121a and 121b. The cutout 91 a and the inclined portion of the gap 94 disposed on the upper half of the pixel electrode 190 are substantially perpendicular to the cutout 91 b and the inclined portion of the gap 94 disposed on the lower half of the pixel electrode 190 .

Thus, the upper half and the lower half of the pixel 190 are respectively divided into four regions by the cutouts 91 a , 91 b , and 92 and the gap 94 . Although specific arrangements have been illustrated and described, the number of separation regions or cutouts may also vary depending on design factors such as pixel size, horizontal to vertical side length ratio of the pixel 190, and type or characteristics of the liquid crystal layer 3.

The pixel electrode 190 overlaps the adjacent gate line 121 to increase the aperture ratio.

The shielding electrode 88 extends along the data line 171 and the gate line 121b, and a portion located above the data line 171 completely covers the data line 171 . A portion of the shield electrode 88 located above the gate line 121b is located within the boundary of the gate line 121b, which has a smaller width than the gate line 121b. The data line 171 disposed between two adjacent pixel electrodes 190 is completely covered by the shielding electrode 88 . However, the width of the shield electrode 88 may be controlled to be smaller than that of the data line 171, or to have a boundary outside the boundary of the gate line 121b. A common voltage is applied to the shield electrode 88 . For this, the shielding electrode 88 is connected to the storage electrode line 131 through a contact hole (not shown) in the passivation layer 180 and the gate insulating layer 140, or is connected to a short-circuit point (not shown), where the common voltage It is applied from the lower panel 100 to the upper panel 200 . The aperture ratio is preferably minimized to shorten the distance between the shield electrode 88 and the pixel electrode 190 as much as possible.

When the shielding electrode 88 receiving the common voltage is located above the data line 171, the shielding electrode 88 shields the electric field formed between the data line 171 and the pixel electrode 190 and between the data line 171 and the common electrode 270, thereby reducing the voltage of the pixel electrode 190. Distortion and signal delay and distortion of the data voltage transmitted by the data line 171 .

In addition, the pixel electrode 190 and the shield electrode 88 should be separated from each other by a sufficient distance to prevent short circuiting thereof. Therefore, the pixel electrode 190 protrudes far enough from the data line 171 to reduce the parasitic capacitance therebetween. In addition, since the dielectric constant of the liquid crystal layer 3 is higher than that of the passivation layer 180, the parasitic capacitance between the data line 171 and the shielding electrode 88 is smaller than that between the data line 171 and the common electrode 270 without the shielding electrode 88. the parasitic capacitance between them.

Since the pixel electrode 190 and the shielding electrode 88 are formed of the same layer, the distance between them remains consistent, so the dielectric constant between them remains unchanged.

The contact assistants 81a, 81b and 82 are connected to the end portions 129a and 129b of the gate lines 121a and 121b and the end portion 179 of the data line 171 through the contact holes 181a, 181b and 182, respectively. The contact assistants 81a, 81b, and 82 serve to enhance adhesion between the exposed end portions 129a and 129b of the gate lines 121a and 121b and the exposed end portion 179 of the data line 171 and external devices and protect them.

An alignment layer 11 is formed on the pixel electrode 190 , the shield electrode 88 , the contact assistants 81 a , 81 b and 82 , and the passivation layer 180 to align the liquid crystal layer 3 . The alignment layer 11 may be a horizontal alignment layer.

Next, the common electrode panel 200 will be described.

The light blocking member 220, also called a black matrix, is formed on the insulating substrate 210 based on transparent glass or plastic to prevent leakage of light. The light blocking member 220 faces the pixel electrode 190 and has a plurality of opening portions having the same shape as the pixel electrode 190 . Alternatively, the light blocking member 220 may be formed of a portion corresponding to the data line 171 and a portion corresponding to the TFTs Qa and Qb. However, the light blocking member 220 may be formed in a different shape to prevent leakage of light around the pixel electrode 190 and the TFTs Qa and Qb.

A plurality of color filters 230 are formed on the substrate 210 . The color filter 230 is mostly disposed in a region surrounded by the light blocking member 220 and extends horizontally and vertically with respect to the pixel electrode 190 . The color filter 230 may exhibit one of three colors of red, green, and blue, although other colors are within the scope of these embodiments.

An overcoat or overcoat 250 is formed on the color filter 230 and the light blocking member 220 to prevent the color filter 230 from being exposed and to provide a flat surface. The capping layer 250 may be made of an organic insulator.

The common electrode 270 is formed on the capping layer 250 and is formed of a transparent conductive material such as, but not limited to, ITO and IZO.

The common electrode 270 has multiple sets of cutouts 271-274b.

Each set of cutouts 271-274b faces one pixel electrode 190, and includes middle cutouts 271 and 272, upper cutouts 273a and 274a, and lower cutouts 273b and 274b. The cutouts 271-274b are disposed on the common electrode 270 corresponding to positions between the cutouts 91a, 91b, 92 and 94 of adjacent pixel electrodes 190 and between the legs of the pixel electrode 190 and the surrounding cutouts 91a and 91b. In addition, each of the cutouts 271 - 274 b includes at least one inclined portion extending parallel to the cutouts 91 a , 91 b , 92 and the gap 94 of the pixel electrode 190 .

The lower and upper cutouts 273a-274b include inclined portions, horizontal and vertical portions, which extend along the common electrode 270 from a position corresponding to the right side of the pixel electrode 190 to its lower and upper sides, and when the horizontal and vertical portions are aligned with When the sides of the pixel electrode overlap and form an obtuse angle with respect to the inclined portion, they protrude along the side of the pixel electrode 190 from positions corresponding to respective ends of the inclined portion.

The first middle cutout 271 has a central horizontal portion, which is located on the common electrode 270, and protrudes horizontally from a position corresponding to the left side of the pixel electrode 190; The position of the end of the horizontal portion protrudes toward the left side of the pixel electrode 190; out. The second middle cutout 272 includes a vertical portion, which is located on the common electrode 270, and extends along a position corresponding to the right side of the second sub-pixel electrode 190b when overlapping with the second sub-pixel electrode; The position of each end of the vertical portion protrudes to the left side of the pixel electrode 190; protrudes along the left side of the second sub-pixel electrode 190b.

Triangular notches are formed at inclined portions of the cutouts 271-274b. Optionally, the shape of each notch may be rectangular, trapezoidal, or semicircular, and may be convex or concave. The notches determine the alignment of the liquid crystal molecules 3 located at the edges of the regions corresponding to the notches 271-274b.

Although a particular arrangement has been illustrated and described, the number of cutouts 271-274b may vary depending on design factors, and the light shield 220 may overlap the cutouts 271-274b to prevent light leakage around the cutouts 271-274b.

Since the same voltage is applied to the common electrode 270 and the shield electrode 88 , there is no electric field between the common electrode 270 and the shield electrode 88 . Therefore, the liquid crystal molecules disposed between the common electrode 270 and the shield electrode 88 continuously maintain their original vertically aligned state, and block light incident thereto.

The alignment layer 21 is coated on the common electrode 270 and the cover layer 250 to align the liquid crystal layer 3 . The alignment layer 21 may be a horizontal alignment layer.

Polarizing plates 12 and 22 are disposed on outer surfaces of the panels 100 and 200, and light transmission axes of the two polarizing plates 12 and 22 are perpendicular to each other. One light transmission axis (or light absorption axis) of the two polarizing plates 12 and 22 is extended in the horizontal direction. In the case of a reflective LCD, one of the two polarizing plates 12 and 22 may be omitted.

The liquid crystal layer 3 has negative dielectric anisotropy, and when no voltage is applied, the liquid crystal molecules of the liquid crystal layer 3 have a director aligned vertically with respect to both panel surfaces.

When the common electrode is applied to the common electrode 270 and the data voltage is applied to the pixel electrode 190, an electric field almost perpendicular to the surfaces of the panels 100 and 200 is generated. The cutouts 91a-94 and 271-274b of the electrodes 190 and 270 disrupt this electric field and form components perpendicular to the sides of the cutouts 91a-94 and 271-274b.

Thus, the electric field is inclined with respect to the direction perpendicular to the surfaces of the panels 100 and 200 . Liquid crystal molecules align in response to an electric field so that their orientation is perpendicular to the electric field. At this time, the electric field formed around the cutouts 91a-94 and 271-274b and the sides of the pixel electrode 190 is not parallel to the orientation of the liquid crystal molecules but at a predetermined angle thereto. Therefore, the liquid crystal molecules turn a short moving distance on the panel between the orientation and the electric field in that direction. Thus, a group of cutouts 91a-94 and 271-274b and the side faces of the pixel electrode 190 divide the liquid crystal layer 3 on the pixel electrode 190 into a plurality of domains, in which the tilt directions of the liquid crystal molecules are different from each other, thereby increasing the number of domains. Increased baseline viewing angle.

At least one of the cutouts 91a-94 and 271-274b may be replaced by a protruding or concave portion, and the shape and arrangement of the cutouts 91a-94 and 271-274b may be changed.

Hereinafter, an exemplary gate shorting bar according to an exemplary embodiment of an LCD of the present invention will be further described with reference to FIGS. 7 and 8 .

7 is an enlarged view of an exemplary gate shorting bar of the exemplary embodiment of the LCD shown in FIG. 1, and FIG. 8 is a cross-sectional view of the exemplary embodiment of the LCD taken along line VIII-VIII' of FIG.

Gate pads PG1a-PGnb are formed on the insulating substrate 110, and gate extension lines 321a, 321b, 322a, 322b, . Extend horizontally. The gate pads PG1a-PGnb and the gate extension lines 321a, 321b, 322a, 322b, . . . may be formed in the same manufacturing process as the gate lines 121a and 121b. A gate insulating layer 140 is formed thereon, and when elongated in a vertical direction, gate short bars 320a and 320b are formed of the same material as the data line 171 on the gate insulating layer 140 . The gate short bars 320 a and 320 b may be formed during the same manufacturing process as the data line 171 . A passivation layer 180 is formed on the gate short bars 320a and 320b.

Contact holes 351 a , 352 a , . . . for exposing the first gate shorting bar 320 a and contact holes 351 b , 352 b , . . . for exposing the second gate shorting bar 320 b are formed through the passivation layer 180 . Contact holes 361 a , 361 b , 362 a , 362 b , . . . for exposing the gate extension lines 321 a , 321 b , 322 a , 322 b , .

The connectors 341a, 341b, 342a, 342b, . . . are formed of ITO or IZO on the passivation layer 180 . The connectors 341a, 341b, 342a, 342b, . . . may be formed during the same manufacturing process as the pixel electrode 190 . The first connectors 341a, 342a, ... physically-electrically connect the first gate shorting bar 320a to the first gate extension lines 321a, 322a through the first contact holes 351a and 361a and 352a and 362a, ... respectively. ,... The second connectors 341b, 342b, ... physically-electrically connect the second gate shorting bar 320b to the second gate extension lines 321b, 322b through the second contact holes 351b and 361b and 352b and 362b, ... respectively. ,...

Meanwhile, grid extension lines 321a, 321b, 322a, 322b, . .

An array test and a VI test of an exemplary embodiment of an LCD according to the present invention will be described with reference to FIGS. 9 and 10 .

FIG. 9 is an exemplary test waveform diagram of an exemplary embodiment of an LCD according to the present invention, and FIG. 10 illustrates polarities of exemplary pixels of an exemplary embodiment of an LCD according to the present invention.

As shown in FIG. 9 , the gate test signals Vga and Vgb are applied to the gate shorting bars 320 a and 320 b with a period of T2 . The gate test signals Vga and Vgb include a phase difference of 180°. Taking T2 as a period, a positive data voltage V+ and a negative data voltage V− are alternately applied to the data short bar 310 . The positive and negative polarities represent the polarity of the data voltage Vdata relative to the common voltage Vcom, and the positive data voltage V+ and the negative data voltage V− are equal in magnitude, or at least substantially equal. In other words, both the positive data voltage V+ and the negative data voltage V− have the same or substantially the same amount of deviation from the common voltage Vcom. In the case of applying the positive data voltage V+, the first gate test signal Vga is applied to turn on the first switching element Qa. In the case of applying the negative data voltage V-, the second gate test signal Vgb is applied to turn on the second switching element Qb.

Subsequently, as shown in FIG. 10, the first sub-pixel electrode 190a is charged with a positive pixel voltage, and the second sub-pixel electrode 190b is charged with a negative pixel voltage. A positive pixel voltage and a negative pixel voltage are continuously supplied to the first sub-pixel electrode 190a and the second sub-pixel electrode 190b, respectively.

However, as shown in the pixel on the upper right side of FIG. 10, the first subpixel electrode and the second subpixel electrode of the sandwich bridge ST1 are alternately charged with the same positive voltage V _PST1 as shown in FIG. pixel voltage and negative pixel voltage. Thus, the bridge ST1 shown in FIG. 10, or any other bridge located between the first subpixel and the second subpixel of each pixel, can be easily detected by array testing to detect the polarity of the electrodes of each subpixel. easily identifiable.

At the same time, when the pulse width of the gate test signals Vga and Vgb is properly controlled to reduce the charging speed of the data voltage, the first sub-pixel electrode and the second sub-pixel electrode with the bridge are charged with less than the positive data voltage V+ and The voltage of the negative data voltage V-. In other words, the magnitude of the voltage charged on the first sub-pixel electrode and the second sub-pixel electrode with the bridge is smaller than the magnitude of the positive data voltage V+ and the negative data voltage V−. However, since the positive data voltage V+ and the negative data voltage V− are continuously applied to the normal first and second subpixel electrodes, the same voltage as the positive data voltage V+ and the negative data voltage V− is maintained there. Therefore, by detecting the brightness difference between the pixel and other pixels through the VI test, the electric bridge between the first sub-pixel electrode 190 a and the second sub-pixel electrode 190 b can be easily identified.

If a bridge is formed between the first subpixel electrode 190a and the shielding electrode 88, and the common voltage Vcom is applied to the shielding electrode 88, the first pixel electrode 190a will not be charged with a normal positive pixel voltage. Thus, through the VI test and the array test, the existence of the bridge between the first sub-pixel electrode 190a and the shielding electrode 88 can be easily identified.

Another exemplary embodiment of an LCD according to the present invention and a testing method thereof will be further described with reference to FIGS. 11 to 14 .

FIG. 11 is a schematic diagram of another exemplary embodiment of an LCD according to the present invention, and FIG. 12 is an enlarged view of an exemplary gate short bar of the exemplary embodiment of the LCD shown in FIG. 11 . FIG. 13 is a test waveform diagram of another exemplary embodiment of an LCD according to the present invention, and FIG. 14 shows polarities of exemplary pixels according to another exemplary embodiment of an LCD of the present invention.

The exemplary embodiment of the LCD described with reference to FIGS. 11 to 14 is very similar to the LCD of the previous embodiment, and thus, only the parts different from the previous embodiment will be further described.

As shown in FIG. 11, the portion of the LCD located inside the LX line is substantially the same as that of the previous embodiment. For the LCD according to the present embodiment, the shielding electrode 88 shown in FIG. 4 is omitted, and thus, the first pixel electrode 190a and the second pixel electrode 190b may overlap the data line 171, thereby increasing the aperture ratio thereof.

In addition, the data shorting bar 310 according to the present embodiment is the same as the data shorting bar according to the previous embodiment. However, the LCD according to the present embodiment includes four gate shorting bars 420a-420d connected to the gate pads PG1a-PGnb instead of the two gate shorting bars 320a and 320b in the previous embodiment.

The gate pads PG1a-PGnb are sequentially connected to the four gate shorting bars 420a-420d. That is, the gate pads PG1a, PG1b, PG2a and PG2b are respectively connected to the gate short bars 420a, 420b, 420c and 420d through the gate extension lines 421a, 421b, 421c and 421d. The next group of gate pads PG3a, . so proceed.

As shown in FIG. 12 , except that the number of gate shorting bars 420a-420d is increased to four and the connection sequence with gate pads PG1a-PGnb is different, the interconnection of gate shorting bars 420a-420d and gate extension lines The interconnection structure is basically the same as the interconnection structure of the gate shorting bars 320a and 320b and the gate extension lines shown in FIGS. 7 and 8 . In other words, each fourth gate extension line is connected to the same gate shorting bar.

As shown in FIG. 13 , with a period of T4 , gate test signals Vga-Vgd are applied to the gate short bars 420 a - 420 d, thereby applying the gate test signals to the gate lines. The gate test signals Vga-Vgd include a phase difference of 90°. Taking T4 as a period, the positive data voltage V+ and the negative data voltage V− are alternately applied to the data short bar 310 , thereby applying the positive data voltage and the negative data voltage to the data lines.

In the case of applying positive data voltage V+ and negative data voltage V- to the data line, the first gate test signal Vga and the fourth gate test signal Vgd are applied to the gate line to turn on the first The switching element Qa and the second switching element Qb in the even pixel row, while applying the negative data voltage V- to the data line, the second gate test signal Vgb and the third gate test signal Vgc are applied to the gate line to turn on the second switching element Qb in the odd pixel row and the first switching element Qa in the even pixel row.

Subsequently, as shown in FIG. 14, the first sub-pixel electrodes 190a in odd pixel rows are charged with positive pixel voltages, and the second sub-pixel electrodes 190b in odd pixel rows are charged with negative pixel voltages. In addition, the first subpixel electrodes 190a in the even pixel rows are charged with a negative pixel voltage, and the second subpixel electrodes 190b in the even pixel rows are charged with a positive pixel voltage. Each of the sub-pixel electrodes 190a and 190b without any bridge sandwiched thereon maintains the once-charged positive pixel voltage or negative pixel voltage continuously.

However, as shown on the right top of FIG. 14, the two first subpixel electrodes 190a in adjacent pixels sandwiching the bridge ST2 are alternately charged with the same positive voltage as the voltage V _PST2 shown in FIG. negative voltage. In addition, as shown in the right bottom of FIG. 14, the first subpixel electrode 190a and the second subpixel electrode 190b in the same pixel sandwiching the bridge ST3 are alternately charged with the same voltage V _PST3 as shown in FIG. positive and negative voltages. Thus, the bridge ST3 shown in FIG. 14 or any other bridge that may exist between the first subpixel electrode 190a and the second subpixel electrode 190b of each pixel, and the bridge ST3 shown in FIG. 14 ST2 or any other bridge existing between two adjacent first sub-pixel electrodes 190a can be easily identified by detecting the polarity of each sub-pixel electrode through an array test.

When the pulse width T3 of the gate test signal Vga-Vgd is properly controlled to reduce the charging speed of the data voltage, the two first sub-pixel electrodes 190a with the bridge are charged with voltages less than the positive data voltage V+ and the negative data voltage V -, and the first sub-pixel electrode 190a and the second sub-pixel electrode 190b with the bridge are also charged with a voltage lower than the positive data voltage V+ and the negative data voltage V-. In other words, the magnitude of the voltage charged on the first sub-pixel electrode and the second sub-pixel electrode with the bridge is smaller than the magnitude of the positive data voltage V+ and the negative data voltage V−. Thus, any other electrical bridges between the first sub-pixel electrodes 190a and between the first sub-pixel electrodes 190a and the second sub-pixel electrodes 190b can be easily identified by detecting the brightness difference between the pixel and other pixels through the VI test.

Although the exemplary embodiment of the LCD according to the present invention has been described as having one data shorting bar, it should be understood that the LCD may optionally include a plurality of data shorting bars, such as two or three data shorting bars. As with the embodiment of the LCD including multiple gate shorting bars, array testing and VI testing can also be performed in the embodiment of the LCD having multiple data shorting bars.

Next, another exemplary embodiment of an LCD according to the present invention will be described with reference to FIGS. 15 and 16 .

FIG. 15 is a schematic diagram of another exemplary embodiment of an LCD according to the present invention, and FIG. 16 is an equivalent circuit diagram of an exemplary pixel of another exemplary embodiment of an LCD according to the present invention.

As shown in FIG. 15, the LCD includes a liquid crystal panel assembly. From the perspective of an equivalent circuit, the panel assembly includes a plurality of display signal lines G1-Gn and D1a-Dmb and a plurality of display signal lines connected to the display signal lines and arranged in a matrix. pixel px.

The display signal lines G1-Gn and D1a-Dmb include a plurality of gate lines G1-Gn for transmitting gate signals and a plurality of data lines D1a-Dmb for transmitting data signals. The gate lines G1-Gn extend along the direction of pixel rows, which are substantially parallel to each other in a first direction, and the data lines D1a-Dmb extend along the direction of pixel columns, which are substantially parallel to each other in a second direction. The first direction may be substantially perpendicular to the second direction.

The liquid crystal panel assembly includes gate pads PG1-PGn respectively connected to the gate lines G1-Gn and data pads PD1a-PDmb respectively connected to the data lines D1a-Dmb so that each gate line G1-Gn is connected to one gate pad PG, and each data line D1a-Dmb is connected to one data pad PD. The gate shorting bar 320 and the data shorting bars 310a and 310b are respectively connected to the gate lines G1-Gn and the data lines D1a-Dmb.

The gate short bar 320 is connected to the gate pads PG1 , PG2 , . . . through gate extension lines 321 , 322 . . . Thus, the respective gate lines G1 -Gn are connected to each other through the gate short bar 320 . The gate short bar 320 may extend substantially perpendicular to the gate lines G1-Gn and substantially parallel to the data lines D1a-Dmb.

The first data short bar 310a is connected to the first data pads PD1a, PD2a, PD3a, ... through the first data extension lines 311a, 312a, 313a, ..., and the second data short bar 310b is passed through the second data The extension lines 311b, 312b, . . . are connected to the second gate pads PD1b, PD2b, . . . Thus, each of the first data lines D1a-Dma is connected to each other through the data shorting bar 310a, and each of the second data lines D1b-Dmb is connected to each other through the data shorting bar. The data short bars 310a and 310b may extend substantially perpendicular to the data lines D1a-Dmb and substantially parallel to the gate lines G1-Gn.

Separate pads (not shown) are provided at the ends of the gate shorting bar 320 and the data shorting bars 310 a and 310 b to apply various test signals, which will be further described below.

After the gate shorting bar 320 and the data shorting bars 310a and 310b have undergone several tests, they are removed along the LX line. That is, elements in the interior of the LX edge are retained for the LCD, and elements outside the LX edge, such as the gate shorting bar 320 and the data shorting bars 310a and 310b, are removed. Accordingly, the gate lines G1-Gn and the data lines D1a-Dmb are separated from each other by removing the shorting bars 320, 310a, and 310b. A gate driver (not shown) and a data driver (not shown) are connected to the gate pads PG1-PGn and the data pads PD1a-PDmb as external devices to supply the gate lines G1-Gn and the data lines D1a-Dmb Apply gate and data signals. However, in the case of integrating the gate driver on the liquid crystal panel assembly, the gate pad may be omitted, and the gate extension lines 321, 322, . . . protrude from the gate driver.

FIG. 16 shows a display signal line and an equivalent circuit diagram at one exemplary pixel PX. The display signal lines include gate lines denoted by GL, data lines denoted by DLa and DLb, and storage electrode lines SL extending substantially parallel to the gate lines GL. Therefore, compared with the previous embodiment in which each pixel includes two gate lines GLa and GLb and a single data line DL, each pixel of this embodiment includes a single gate line GL and a pair of data lines DLa and DLb.

Each pixel PX includes a pair of subpixels PXc and PXd, and each of PXc and PXd includes switching elements Qc and Qd connected to the corresponding gate line GL and data lines DLa and DLb, and liquid crystal capacitors connected to those switching elements. C _LCc and C _LCd and storage capacitors C _STc and C _STd . In alternative embodiments, the storage capacitors C _STc and C _STd may be omitted, and in this case, the storage electrode line SL may be omitted.

As shown in FIGS. 15 and 16, all gate lines GL are connected to the gate shorting bar 320, all first data lines DLa are connected to the first data shorting bar 310a, and all second data lines DLb are connected to the second Data shorting bar. Thereby, the same signal, which is different from the signal applied to the first subpixel PXc, may be applied to each first subpixel PXc, and the same signal may be applied to each second subpixel PXd.

Since the respective subpixels PXc and PXd are substantially the same as those shown in FIG. 3 , detailed descriptions thereof will be omitted.

Next, the structure of the LCD will be further described with reference to FIGS. 17 and 18 .

17 is a plan view of another exemplary embodiment of an LCD according to the present invention, and FIG. 18 is a cross-sectional view of the exemplary embodiment of the LCD taken along line XVIII-XVIII' of FIG. 17 .

As shown in FIGS. 17 and 18 , the LCD includes a lower panel 101 , an upper panel 201 facing the lower panel 101 , and a liquid crystal layer 3 between the panels 101 and 201 . The lower panel 101 may also be called a TFT panel or a first panel, and the upper panel 201 may also be called a common electrode panel, a color filter panel, or a second panel.

First, the lower panel 101 will be described.

A plurality of gate lines 121 and a plurality of storage electrode lines 131a are formed on a transparent glass or plastic based insulating substrate 110 .

The gate lines 121 extend horizontally, such as in a lateral direction or a first direction, and are separated from each other to transmit gate signals. Each of the gate lines 121 has a plurality of protrusions for forming the gate electrodes 124c and 124d and wide-area end portions 129 connected to other layers or external devices.

The storage electrode line 131a also extends horizontally substantially parallel to the gate line 121, and has a plurality of protrusions for forming storage electrodes 133a and 133b. The storage electrodes 133a and 133b may be rectangular in shape and symmetrical to the storage electrode line 131a.

The gate insulating layer 140 is formed on the gate line 121 and the storage electrode line 131 a, and may be further formed on the exposed portion of the insulating substrate 110 . The gate insulating layer 140 may be made of silicon nitride (SiNx) or the like.

A plurality of island-shaped semiconductors 154c, 154d, 156b, and 157b are formed of hydrogenated a-Si or polysilicon on the gate insulating layer 140 . Semiconductors 154c and 154d are located on gate electrodes 124c and 124d, respectively.

A plurality of island-shaped ohmic contacts 163c, 163d, 165c, 165d, 166b, and 167 having n+ hydrogenated a-Si in which doping such as silicide and high concentrations of n-type impurities of phosphorus. Pairs of ohmic contacts 163c and 165c and ohmic contacts 163d and 165d are located on semiconductors 154c and 154d, while other ohmic contacts 166b and 167 are located on semiconductors 156b and 157b, respectively.

A plurality of data lines 171 a and 171 b and drain electrodes 175 c and 175 d separated from the data lines 171 a and 171 b are formed on the gate insulating layer 140 and the ohmic contacts 163 c , 163 d , 165 c , 165 d , 166 b and 167 .

The data lines 171a and 171b extend vertically, such as in a longitudinal direction or a second direction, so as to cross the gate lines 121 and the storage electrode lines 131a to transmit data voltages. The data lines 171a and 171b are separated from the gate line 121 by the gate insulating layer 140 disposed between the gate line and the data line. The data lines 171a and 171b include a plurality of source electrodes 173c and 173d and end portions 179a and 179b having enlarged widths for connecting other layers thereof or external devices.

The first drain electrode 175c and the second drain electrode 175d are separated from the data lines 171a and 171b, and face the source electrodes 173c and 173d around the gate electrodes 124c and 124d, respectively. The first drain electrode 175c and the second drain electrode 175d have rod-shaped ends, which are located on the semiconductors 154c and 154d; overlapping. Rod-shaped ends of drain electrodes 175c and 175d are partially surrounded by U-shaped bent source electrodes 173c and 173d.

The first gate electrode 124c and the second gate electrode 124d, the first source electrode 173c and the second source electrode 173d, the first drain electrode 175c and the second drain electrode 175d form the first TFT Qc and the second TFT together with the semiconductors 154c and 154d. Qd. The channels of the TFTs Qc and Qd are formed in the semiconductor 154c between the first source electrode 173c and the second source electrode 173d and the first drain electrode 175c and the second drain electrode 175d and between the ohmic contacts 163c, 163d and 165c, 165d and 154d.

The ohmic contacts 163c, 163d, 165c, 165d, 166b, and 167 are interposed only between the underlying semiconductors 154c, 154d, 156b, and 157b and the overlying data lines 171a, 171b and drain electrodes 175a, 175b to reduce contact resistance therebetween. . The island-shaped semiconductors 154c and 154d have portions exposed through the source electrodes 173c and 173d and the drain electrodes 175c and 175d, and the semiconductors 156b and 157b smooth the contours on the gate line 121 and the storage electrode line 131a, thereby preventing the data lines 171a and 171b from And the drain electrodes 175c and 175d intersect.

A passivation layer 180 is formed on the data lines 171a, 171b, the drain electrodes 175c, 175d, and exposed portions of the semiconductors 154c and 154d. As shown, a passivation layer 180 may be further formed on the exposed portion of the gate insulating layer 140 .

A plurality of contact holes 185c, 185d, 182a, and 182b are formed through the passivation layer 180 to expose extensions 177c, 177d of the drain electrodes 175c, 175d and end portions 179a, 179b of the data lines 171a, 171b, respectively. A plurality of contact holes 181 are formed through the passivation layer 180 and the gate insulating layer 140 to expose the end portions 129 of the gate lines 121 .

A plurality of pixel electrodes 191 having first and second subpixels 191 a and 191 b , a plurality of shield electrodes 88 a , and a plurality of auxiliary contacts (contact assistants) 81 , 82 a , and 82 b are formed on the passivation layer 180 . The plurality of pixel electrodes 191, the plurality of shield electrodes 88a, and the plurality of auxiliary contacts 81, 82a, and 82b may be made of a transparent conductive material such as ITO or IZO, or a light-reflective conductive material such as aluminum used in reflective LCDs. production.

The first subpixel electrode 191a and the second subpixel electrode 191b are physically-electrically connected to the first drain electrode 175c and the second drain electrode 175d through the contact holes 185c and 185d, so as to receive signals from the first drain electrode 175c and the second drain electrode 175d. data voltage. Predetermined voltages different from each other are applied to the pixel electrodes 191a and 191b with respect to one input image signal, and the magnitude of the voltages may be determined according to the shape and size of the subpixel electrodes 191a and 191b. In addition, regions of the subpixel electrodes 191a and 191b may be identical to each other. Compared with the first subpixel electrode 191a, the second subpixel electrode 191b receives a higher voltage, and its area is smaller than that of the first subpixel electrode 190a.

The sub-pixel electrodes 191a and 191b for receiving the data voltage are combined with the common electrode 270 of the opposite panel 200 provided with a common voltage to generate an electric field, thereby determining the arrangement of liquid crystal molecules in the liquid crystal layer 3 between the two electrodes 191 and 270 .

The respective subpixel electrodes 191a and 191b and the common electrode 270 form liquid crystal capacitors C _LCc and C _LCd , and maintain the applied voltage even after the TFTs Qc and Qd are turned off. Storage capacitors _CSTc and _CSTd are formed by overlapping the first subpixel electrode 191a, the second subpixel electrode 191b and the extensions 177c, 177d of the drain electrodes 175c, 175d connected thereto with the storage electrodes 133a and 133b, which are connected in parallel to Liquid crystal capacitors C _LCc and C _LCd to enhance voltage storage capacity.

A pair of first and second subpixel electrodes 191a and 191b forming the pixel electrode 191 are joined to each other with a gap 93 interposed therebetween, and the outer shape of the pixel electrode 191 is approximately rectangular. The second subpixel electrode 191b roughly forms a rotated equilateral trapezoid, which has a trapezoidal concave bottom, and most of the second subpixel electrode is surrounded by the first subpixel electrode 191a, that is, the second subpixel electrode 191b falls into the first sub-pixel electrode 191a. The first subpixel electrode 191a has an upper trapezoidal portion, a lower trapezoidal portion, and a middle trapezoidal shape connected to each other on the left side thereof. The central trapezoidal portion of the first subpixel electrode 191a fits into the concave bottom surface of the second subpixel electrode 191b. The gap 93 between the first subpixel electrode 191a and the second subpixel electrode 191b roughly has two pairs of upper and lower inclined portions with a uniform width at an angle of about 45° to the gate line 121, and three pairs with substantially Vertical sections of uniform width. For ease of description, the gap 93 may also be referred to as a cutout.

The first sub-pixel 191a has cutouts 96a, 96b, 97a, and 97b extending from the top surface of the upper trapezoidal portion and the bottom surface of the lower trapezoidal portion to the right thereof. The first subpixel electrode 191a has cutouts 91 and 92a extending along the storage electrode line 131a, and the cutouts 91 and 92a have a horizontal portion extending horizontally from the center thereof and two legs at an angle of about 45° to the storage electrode line 131a. The second subpixel electrode 191b has cutouts 94a and 94b extending from left to right. The cutouts 91 , 92 a , 94 a , 94 b , 96 a , 96 b , 97 a , and 97 b are mirror-symmetrical to the storage electrode line 131 a and extend substantially perpendicular or parallel to each other when forming an angle of about 45° with the gate line 121 . That is to say, the cutouts on the upper half of the pixel electrode 191 are arranged parallel to each other, the cutouts on the lower half of the pixel electrode 191 are arranged parallel to each other, and the cutouts on the upper half are perpendicular to the cutouts on the lower half. . The upper and lower halves of the pixel electrode 191 are divided into eight regions by the cutouts 91-97b.

Although specific arrangements have been illustrated and described, the number of separation regions or cutouts may also vary depending on design factors such as pixel size, horizontal to vertical length ratio of pixels 191 , and type or characteristics of liquid crystal layer 3 .

The shield electrode 88 a has a vertical portion extending along the data lines 171 a and 171 b and a horizontal portion extending along the gate line 121 . The vertical portion completely covers the data lines 171 a and 171 b , and the horizontal portion completely covers the gate line 121 .

The shielding electrode 88a shields the electric field between the data lines 171a and 171b and the pixel electrode 191 and between the data lines 171a and 171b and the common electrode 270, so as to reduce the voltage distortion of the pixel electrode 191 and the distortion of the data voltage transmitted by the data lines 171a and 171b. Signal delay. In addition, the pixel electrode 191 and the shield electrode 88a should be separated from each other by a sufficient distance to prevent them from short-circuiting. Therefore, since the pixel electrode 191 extends far enough from the data lines 171a and 171b and the gate line 121, the parasitic capacitance between them is reduced.

The auxiliary contacts 81, 82a and 82b are connected to the end 129 of the gate line 121 and the ends 179a and 179b of the data lines 171a and 171b, respectively. The auxiliary contacts 81, 82a, and 82b function to enhance adhesion between the exposed end portions 129 of the gate line 121 and the exposed end portions 179a and 179b of the data lines 171a and 171b and external devices, and protect them.

The alignment layer 11 is formed on the pixel electrode 191 , the auxiliary contacts 81 , 82 a and 82 b and the passivation layer 180 to align the liquid crystal layer 3 .

Next, the upper panel 201 will be described.

A light blocking member 220 (also referred to as a black matrix), a plurality of color filters 230, an overcoat layer 250, and a common electrode 270 are sequentially formed on the insulating substrate 210 based on transparent glass or plastic.

The common electrode 270 has a plurality of sets of cutouts 71, 72, 73a, 74a, 75c, 75d, 76c, 76d, 77a, 77b, 78a, and 78b.

Each set of cutouts 71-78 faces one pixel electrode 191 and includes middle cutouts 71, 72, 73a and 74a, upper cutouts 75c, 76c, 77a and 78a, and lower cutouts 75d, 76d, 77b and 78b. The cutouts 71-78b are provided on the common electrode 270, which correspond to the left center of the pixel electrode 191, between the adjacent cutouts of the pixel electrode 191, and between the outermost cutouts 97a and 97b and the corners of the pixel electrode 191. . In addition, the cutouts 72 - 78 b include at least one inclined portion extending parallel to the cutouts 91 - 97 b of the pixel electrode 191 .

The lower and upper cutouts 75c-78b include an inclined portion, a horizontal portion and a vertical portion, the inclined portion extends from the position corresponding to the right side of the pixel electrode 191 along the common electrode 270 to the bottom surface or the top surface, and when the horizontal and vertical portions are aligned with the pixel electrode 191 The electrodes protrude along the sides of the pixel electrode 191 from positions corresponding to the respective ends of the inclined portion when the sides thereof overlap and form an obtuse angle with respect to the inclined portion.

The first middle cutout 71 has a vertical portion on the common electrode 270 extending along a position corresponding to the left side of the pixel electrode 191 when overlapping the pixel electrode; and a horizontal portion extending from the center of the vertical portion along the storage electrode line 131a. out. The second and third middle cutouts 72 and 73a include a horizontal portion on the common electrode 270 extending along a position corresponding to the storage electrode line 131a; and a vertical end, when it overlaps the left side of the pixel electrode and forms an obtuse angle with the inclined portion, protrudes from the end of the inclined portion along a position corresponding to the left side of the pixel electrode 191 . The fourth middle cutout 74a includes a vertical portion located on the common electrode 270, extending along a position corresponding to the right side of the pixel electrode 191 when overlapping with the pixel electrode; The position on the left side of the electrode 191 extends; and the vertical end, when overlapping the pixel electrode and forming an obtuse angle with the inclined portion, extends from the end of the inclined portion along the position corresponding to the left side of the second sub-pixel electrode 191b on the common electrode 270 .

Triangular notches are formed on the inclined portions of the cutouts 72-77b. Optionally, the shape of each notch may be rectangular, trapezoidal, or semicircular, and have a protruding or concave shape.

Although a particular arrangement has been illustrated and described, the number of cutouts on the common electrode 270 may vary depending on design factors.

The alignment layer 21 is formed on the common electrode 270 and the capping layer 250 to align the liquid crystal layer 3 .

Polarizing plates 12 and 22 are attached to the outer surfaces of the display panels 101 and 201 . In the case of a reflective LCD, one of the two polarizing plates 12 and 22 may be omitted.

Many features of the previous embodiments of the LCD described with reference to FIGS. 4 to 6 can be applied to the LCD shown in FIGS. 17 and 18 .

Exemplary data shorting bars according to this embodiment will be further described with reference to FIGS. 19 and 20 .

19 is an enlarged view of an exemplary data short bar of the exemplary embodiment of the LCD shown in FIG. 15 , and FIG. 20 is a cross-sectional view of the exemplary embodiment of the LCD taken along line XX-XX' of FIG. 19 .

The data short bars 310a and 310b are formed on the insulating substrate 110, are formed of the same material as the gate line 121, and the gate insulating layer 140 is formed thereon. The data short bars 310 a and 310 b may be formed during the same manufacturing process as the gate line 121 . Data pads PD1a-PDmb are formed on the gate insulating layer 140, and data extension lines 311a, 311b, 312a, 312b, . . The data pads PD1a-PDmb and the data extension lines 311a, 311b, 312a, 312b, . . . may be formed in the same manufacturing process as the data lines 171a and 171b. A passivation layer 180 is formed on the data extension lines 311a, 311b, 312a, 312b, . . . .

Contact holes 381a, 381b, 382a, 382b, . . . are formed through the passivation layer 180 to expose the data extension lines 311a, 311b, 312a, 312b, . The contact holes 391a, 392a, . . . for exposing the first gate shorting bar 310a and the contact holes 391b, 392b, . Layer 140 is formed.

The connectors 371a, 371b, 372a, 372b, . . . are formed of ITO or IZO on the passivation layer 180 . The connectors 371a, 371b, 372a, 372b, . . . may be formed during the same manufacturing process as the pixel electrode 191 . The first connectors 371a, 372a, ... are physically-electrically interconnected with the first data short bar 310a and the data extension lines 311a, 312a, ... respectively connected, and the second connectors 371b, 372b, . - electrical interconnection.

Meanwhile, the data extension lines 311a, 311b, 312a, 312b, . . . may extend over the data short bars 310a and 310b so that they are connected to an antistatic auxiliary line (not shown).

Next, a VI test for an exemplary embodiment of an LCD according to the present invention will be described with reference to FIGS. 21 and 22 .

FIG. 21 is an exemplary test waveform diagram of another exemplary embodiment of an LCD according to the present invention, and FIG. 22 shows pixel polarity of another exemplary embodiment of an LCD according to the present invention.

As shown in FIG. 2 , the gate test signal Vg is applied to the gate short bar 320 according to the period of T6 . A positive data voltage V+ is applied to the first gate shorting bar 310a, and a negative data voltage V− is applied to the second gate shorting bar 310b. The magnitudes of the positive data voltage V+ and the negative data voltage V- are equal, or at least substantially equal. In other words, both the positive data voltage V+ and the negative data voltage V− have the same or substantially the same amount of deviation from the common voltage. Due to the application of the gate test signal, the switching elements Qc and Qd are turned on, so that the first subpixel electrode 191a is charged with a positive pixel voltage, and the second subpixel voltage 191b is charged with a negative pixel electrode. A positive pixel voltage and a negative pixel voltage are continuously provided on the first sub-pixel electrode 191a and the second sub-pixel electrode 190b.

However, as shown in FIG. 22, in the case where a bridge ST4 is formed between the data lines D2b and D3a, a voltage V _PST4 (for example, a common voltage) smaller than the positive data voltage V+ and the negative data voltage V- is applied to the bridge ST4 connected thereto. The first sub-pixel electrode and the second sub-pixel electrode. That is, the sub-pixel electrodes connected to the data lines D2b and D3a are applied with a voltage V _PST4 such as a common voltage, which has a magnitude smaller than the positive data voltage V+ and the negative data voltage V-, since it is not as positive data voltage V+ and the negative data voltage V- deviate too much from the common voltage. Therefore, the bridge between the first data line 171a and the second data line 171b can be easily identified by detecting the difference in brightness between the pixel column and the adjacent column through the VI test.

In addition, even when the bridge ST5 is formed between the first subpixel electrode 191a and the second subpixel electrode 191b, the subpixel electrode is charged with a voltage V _PST5 smaller than the positive data voltage V+ and the negative data voltage V−. Therefore, the bridge between the first data line 191a and the second data line 191b can be easily identified by detecting the brightness difference between a pixel and adjacent pixels through the VI test.

As described above, with the structure of the present invention, the gate lines connected to the respective sub-pixels are connected with two or four gate shorting bars, and the array test and the VI test are completed. Thus, the bridge between the respective adjacent sub-pixel electrodes can be easily detected.

In addition, the data lines connected to each sub-pixel are connected to two or four data shorting bars, and the array test and VI test are completed. Thus, the electric bridges between adjacent data lines and between adjacent sub-pixel electrodes can be easily detected.

Although the present invention has been described in detail with reference to preferred embodiments, as described in the appended claims, for those skilled in the art, the present invention can be modified without departing from the spirit and scope of the present invention. Various modifications and equivalents are made.

Claims (41)

1. A liquid crystal display, comprising: a plurality of pixel electrodes arranged in a matrix, and each pixel electrode has a first sub-pixel electrode and a second sub-pixel electrode with different sizes from each other; a first switching element and a second switching element connected to the first sub-pixel electrode and the second sub-pixel electrode, respectively; a first gate line and a second gate line connected to the first switching element and the second switching element, respectively; a data line connected to the first switching element and the second switching element and transmitting a data voltage; and a first gate shorting bar and a second gate shorting bar connected to the first gate line and the second gate line respectively and supplied with a first gate test signal and a second gate test signal respectively , wherein a positive data voltage is applied to the data line when the first gate test signal is applied, and a negative data voltage is applied to the data line when the second gate test signal is applied, and the positive data voltage and the negative data voltage have substantially the same magnitude, Wherein, the first gate test signal and the second gate test signal have a phase difference of 180°. 2. The liquid crystal display of claim 1, further comprising a data shorting bar connected to the data line. 3. The liquid crystal display of claim 2, wherein the data short bar is formed in the same layer of the liquid crystal display as the first and second gate lines. 4. The liquid crystal display of claim 1, further comprising a shielding electrode overlapping the data line and disposed between two adjacent pixel electrodes. 5. The liquid crystal display of claim 4, wherein the shielding electrode overlaps at least one of the first gate line and the second gate line. 6. The liquid crystal display according to claim 1, wherein magnitudes of data voltages applied to the first sub-pixel electrode and the second sub-pixel electrode are different from each other when an image signal is input, and the data voltages Obtained from a set of image information. 7. The liquid crystal display according to claim 6, wherein the first sub-pixel electrode is larger in size than the second sub-pixel electrode, and when an image signal is input, the first sub-pixel electrode is applied to the first sub-pixel electrode The magnitude of the data voltage is smaller than the magnitude of the data voltage applied to the second sub-pixel electrode. 8. The liquid crystal display of claim 1, wherein the first and second gate shorting bars are formed in the same layer of the liquid crystal display as the data lines. 9. The liquid crystal display of claim 1, wherein the first gate shorting bar and the second gate shorting bar are substantially parallel to the data lines. 10. The liquid crystal display according to claim 1, wherein the first gate short bar and the second gate short bar are located outside the edge of the display panel of the liquid crystal display. 11. The liquid crystal display according to claim 1 , further comprising gate pads respectively connected to the first gate line and the second gate line and respectively connected to the first gate shorting bar and the The grid extension line of the second grid short bar. 12. A liquid crystal display comprising: A plurality of pixel electrodes are arranged in a matrix, and each pixel electrode has a first sub-pixel electrode and a second sub-pixel electrode with different sizes from each other. a first switching element and a second switching element connected to the first sub-pixel electrode and the second sub-pixel electrode, respectively; a first gate line and a second gate line connected to the first switching element and the second switching element, respectively; a data line connected to the first switching element and the second switching element and transmitting a data voltage; The first gate shorting bar and the second gate shorting bar are respectively connected to the first gate line and the second gate line of the odd pixel row, and are provided with the first gate test signal and the second gate line respectively. two gate test signals; and The third gate shorting bar and the fourth gate shorting bar are respectively connected to the first gate line and the second gate line of the even-numbered pixel row, and are provided with the third gate test signal and the second gate line respectively. Quad gate test signal, Wherein, a positive data voltage is applied to the data line when the first and fourth gate test signals are applied, and a negative data voltage is applied when the second and third gate test signals are applied. to the data line, and the positive data voltage and the negative data voltage have substantially the same magnitude, Wherein, the first gate test signal, the second gate test signal, the third gate test signal and the fourth gate test signal have a phase difference of 90°. 13. The liquid crystal display of claim 12, further comprising a data shorting bar connected to the data line. 14. The liquid crystal display of claim 13, wherein the data short bar is formed in the same layer of the liquid crystal display as the first and second gate lines. 15. The liquid crystal display according to claim 12, further comprising: connected to the first gate test signal, the second gate test signal, the third gate test signal and the fourth gate test signal respectively. The gate pad of the gate test signal and respectively connect the first gate short bar, the second gate short bar, the third gate short bar and the fourth gate short bar to the The gate extension line of the gate pad. 16. A method for testing a liquid crystal display, the liquid crystal display comprising a plurality of pixels having a first sub-pixel electrode and a second sub-pixel electrode; respectively connected to the first sub-pixel electrode and the second sub-pixel electrode a first switching element and a second switching element; a first gate line and a second gate line respectively connected to the first switching element and the second switching element; and a first gate line connected to the first switching element and the second switching element; For the data line of the second switching element, the testing method includes: providing a first gate shorting bar and a second gate shorting bar respectively connected to the first gate line and the second gate line; providing a data shorting bar connected to said data line; applying a positive data voltage to the data shorting bar; applying a first gate test signal to the first gate short bar to apply the positive data voltage to the first sub-pixel electrode; applying a negative data voltage to the data shorting bar; and applying a second gate test signal to the second gate short bar to apply the negative data voltage to the second sub-pixel electrode, wherein the positive data voltage and the negative data voltage have substantially the same magnitude, Wherein, the first gate test signal and the second gate test signal have a phase difference of 180°. 17. The method of claim 16, further comprising detecting polarities of the first subpixel electrode and the second subpixel electrode. 18. The method of claim 17, wherein detecting the polarity of the first subpixel electrode and the second subpixel electrode comprises performing an array test. 19. The method of claim 18, further comprising identifying the presence of a bridge between the first subpixel electrode and the second subpixel electrode. 20. The method according to claim 19, wherein the positive voltage of the first sub-pixel electrode and the second sub-pixel electrode having a bridge is provided discontinuously under the condition of applying a positive data voltage and a negative data voltage. Pixel voltage and negative pixel voltage. 21. The method of claim 19, further comprising detecting brightness uniformity of the liquid crystal display. 22. The method of claim 21, wherein inspecting brightness uniformity includes performing a visual inspection test. 23. The method of claim 21 , further comprising identifying when a pixel having the first sub-pixel and the second sub-pixel with a bridge has a different brightness than a pixel without a bridge. The presence of a bridge between the first sub-pixel electrode and the second sub-pixel electrode. 24. The method of claim 16, further comprising separating the first and second gate shorting bars from the first and second gate lines, and separating the data shorting bars from the data lines separate. 25. A method for testing a liquid crystal display, the liquid crystal display comprising a plurality of pixels having a first sub-pixel electrode and a second sub-pixel electrode; respectively connected to the first sub-pixel electrode and the second sub-pixel electrode a first switching element and a second switching element; a first gate line and a second gate line respectively connected to the first switching element and the second switching element; and a first gate line connected to the first switching element and the second switching element; For the data line of the second switching element, the testing method includes: providing a first gate shorting bar and a second gate shorting bar respectively connected to the first gate line and the second gate line of odd pixel rows; providing a third gate shorting bar and a fourth gate shorting bar respectively connected to the first gate line and the second gate line of an even pixel row; providing a data shorting bar connected to said data line; applying a positive data voltage to the data shorting bar; applying a first gate test signal to the first gate short bar to apply the positive data voltage to the first sub-pixel electrode of the odd pixel row, applying a negative data voltage to the data shorting bar; Applying a second gate test signal and a third gate test signal to the second and third gate shorting bars, so as to provide the second sub-pixel electrodes of the odd pixel rows and all of the even pixel rows applying the negative data voltage to the first sub-pixel electrode; and applying a fourth gate test signal to the fourth gate short bar to apply the positive data voltage to the second sub-pixel electrode of the even pixel row, wherein the positive data voltage and the negative data voltage have substantially the same magnitude, and Wherein, the first gate test signal, the second gate test signal, the third gate test signal and the fourth gate test signal have a phase difference of 90°. 26. The method of claim 25, further comprising detecting polarities of the first subpixel electrode and the second subpixel electrode. 27. The method of claim 25, further comprising identifying the presence of a bridge between the first subpixel electrode and the second subpixel electrode. 28. The method of claim 25, further comprising identifying the presence of a bridge between first subpixel electrodes of adjacent pixels. 29. The method of claim 25, further comprising detecting brightness uniformity of the liquid crystal display. 30. The method of claim 25, further comprising connecting the first gate shorting bar and the second gate shorting bar to the first gate line and the second gate line of the odd pixel row. gate line separation; separating the third gate short bar and the fourth gate short bar from the first gate line and the second gate line of the even pixel row; and separating the The data short bar is separated from the data line. 31. A liquid crystal display comprising: A plurality of pixel electrodes are arranged in a matrix, and each pixel electrode has a first sub-pixel electrode and a second sub-pixel electrode with different sizes from each other. a first switching element and a second switching element connected to the first sub-pixel electrode and the second sub-pixel electrode, respectively; a gate line connected to the first switching element and the second switching element; a gate shorting bar connected to the gate line; a first data line and a second data line crossing the gate line and connected to the first switching element and the second switching element, respectively; and a first data short bar and a second data short bar connected to the first data line and the second data line respectively and provided with data voltages having different polarities from each other, wherein the data voltages having different polarities from each other have substantially the same magnitude, Wherein, a gate test signal is applied to the gate short bar to apply a positive data voltage to the first sub-pixel electrode and a negative data voltage to the second sub-pixel electrode. 32. The liquid crystal display according to claim 31, wherein magnitudes of data voltages applied to the first sub-pixel electrode and the second sub-pixel electrode are different from each other when an image signal is input, and the data voltage Obtained from an image infogroup. 33. The liquid crystal display according to claim 32, wherein the first subpixel electrode is larger in size than the second subpixel electrode, and the first subpixel electrode is applied to the first subpixel electrode when an image signal is input. The magnitude of the data voltage is smaller than the magnitude of the data voltage applied to the second subpixel electrode. 34. The liquid crystal display of claim 31, wherein the first data short bar and the second data short bar are formed in the same layer of the liquid crystal display as the gate lines. 35. The liquid crystal display of claim 31, wherein the first data short bar and the second data short bar are substantially parallel to the gate lines. 36. The liquid crystal display according to claim 31, wherein the first data short bar and the second data short bar are outside the edge of the display panel of the liquid crystal display. 37. A method for testing a liquid crystal display, the liquid crystal display comprising a plurality of pixels having a first sub-pixel electrode and a second sub-pixel electrode; respectively connected to the first sub-pixel electrode and the second sub-pixel electrode the first switching element and the second switching element; the gate lines respectively connected to the first switching element and the second switching element; and the gate lines respectively connected to the first switching element and the second switching element For the first data line and the second data line, the test method includes: setting a first data shorting bar and a second data shorting bar connected to the first data line and the second data line respectively; providing a gate shorting bar connected to the gate line; applying a positive data voltage to the first data short bar; applying a negative data voltage to the second data shorting bar; and applying a gate test signal to the gate short bar to apply the positive data voltage to the first sub-pixel electrode and the negative data voltage to the second sub-pixel electrode, Wherein, the positive data voltage and the negative data voltage have substantially the same magnitude. 38. The method of claim 37, further comprising detecting brightness uniformity of the liquid crystal display. 39. The method of claim 37, further comprising identifying the presence of a bridge between the first and second data lines. 40. The method of claim 37, further comprising identifying the presence of a bridge between the first subpixel electrode and the second subpixel electrode. 41. The method of claim 37, further comprising separating the first and second data shorting bars from the first and second data lines, and separating the gate shorting bars from the gate lines separate.

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