CN101419345B - Display driver and its built-in test circuit - Google Patents

Abstract

A display driver and a built-in test circuit thereof. The test circuit comprises a test control unit and a switch unit. The test control unit determines a test mode according to the control signal, wherein the test mode comprises a first mode and a second mode. The switch unit is coupled to a display panel and receives a first gray scale voltage and a second gray scale voltage, wherein the display panel comprises a first data line and a second data line. Accordingly, the switching unit transmits the first gray scale voltage to the first data line and transmits the second gray scale voltage to the second data line in the first mode. And the switch unit transmits the first gray scale voltage to the second data line and transmits the second gray scale voltage to the first data line in the second mode.

Description

Display driver and its built-in test circuit

technical field

The present invention relates to a display driver and its built-in test circuit, and in particular to a display driver and its built-in test circuit for testing the assembly quality of a display.

Background technique

In recent years, liquid crystal displays (Liquid Crystal Displays, LCDs) have been widely accepted and used, and have replaced traditional cathode ray tube displays (CRTs). With the vigorous development of semiconductor technology, liquid crystal displays have the advantages of low power consumption, thinness, high resolution, high color saturation and long service life, so they are widely used in mobile phones, notebook computers, desktops, etc. Computer LCD screens and LCD TVs (LCD TV) and other electronic products that are closely related to life. Among them, the quality of the display panel is an important key to determine the quality of the liquid crystal display.

Therefore, in order to ensure the quality of the liquid crystal display, testing the assembly quality of the product is a necessary part of the production process. The traditional liquid crystal display module inspection method is to use a timing controller to generate test samples, and output the test samples to the display panel, and the display panel displays images according to the test samples. Therefore, the defects can be seen from the picture presented by the display panel, and then the quality of the assembly quality in the production process of the liquid crystal display can be judged.

In the process of using the traditional liquid crystal display module inspection method to inspect the assembly quality, it usually uses the test pins of the test fixture to contact the test points provided on the X-board of the display for data input. Check the quality with the output. Since the timing controller of the test machine can output the test sample to the X-board through the test pins on the test fixture, the test can be performed after the test fixture is directly electrically connected to the X-board. However, the test fixture is quite expensive, so that manufacturers must increase a lot of cost when testing the assembly quality of the LCD. Therefore, it is necessary to simplify the assembly quality test, which not only may increase the test speed, but also greatly reduces the production cost.

Contents of the invention

The invention provides a test circuit, which can achieve the test purpose with a small number of test pins in the test process, so the test process can be fully simplified and the test speed can be improved.

The present invention further provides a display driver, which can generate test samples by using a small number of test pins without using a timing controller to generate test samples, thus effectively solving the problems faced by the prior art.

The invention provides a test circuit for testing a display panel, which includes a test control unit and a switch unit. The test control unit determines a test mode according to a control signal, wherein the test mode includes a first mode and a second mode. The switch unit is controlled by the test control unit, which is coupled to a display panel and receives the first gray-scale voltage and the second gray-scale voltage, wherein the display panel includes a first data line and a second data line. Therefore, when the switch unit is in the first mode, it transmits the first gray-scale voltage to the first data line, and transmits the second gray-scale voltage to the second data line. When the switch unit is in the second mode, it transmits the first grayscale voltage to the second data line, and transmits the second grayscale voltage to the first data line.

From another point of view, the present invention provides a display driver electrically connected to a display panel through a plurality of wires, which includes a test circuit. Wherein, the test circuit includes a test control unit and a switch unit. The test control unit determines a test mode according to a control signal, wherein the test mode includes a first mode and a second mode. The switch unit is controlled by the test control unit, which is coupled to a display panel and receives the first gray-scale voltage and the second gray-scale voltage, wherein the display panel includes a first data line and a second data line. Therefore, when the switch unit is in the first mode, it transmits the first gray-scale voltage to the first data line, and transmits the second gray-scale voltage to the second data line. When the switch unit is in the second mode, it transmits the first grayscale voltage to the second data line, and transmits the second grayscale voltage to the first data line.

The present invention adopts the method of building a test circuit in the driver, so that the driver can generate test samples, so the test purpose can be achieved without using a timing controller. Therefore, in addition to simplifying the test process and improving the test speed, it can also effectively Solve the problems faced by the prior art.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 shows a structural diagram of a test circuit coupled to a display panel according to an embodiment of the present invention.

FIG. 1A shows a characteristic curve of gray scale voltage and gray scale of a display panel under polarity switching according to an embodiment of the present invention.

FIG. 2 shows a structural diagram of a test circuit coupled to a display panel according to another embodiment of the present invention.

Fig. 3 shows an embodiment of the counter in Fig. 2 in four test modes.

FIG. 4 shows an implementation of the logic unit in FIG. 2 in four test modes.

Fig. 5 shows an implementation of the polarity switching unit in Fig. 2 in four test modes.

FIG. 6 shows an implementation manner of the first multiplexer to the third multiplexer in the four test modes of FIG. 2 .

FIG. 7 shows a structural diagram of a display driver according to another embodiment of the present invention.

Description of reference symbols

100, 200, 700: display driver

101, 201: drive circuit

102, 202, 710: Test circuit

110, 210, 711: Test control unit

120, 220, 712: switch unit

130, 230: display panel

111, 211: counter

112, 212: logic unit

121, 221: first multiplexer

122, 222: second multiplexer

124, 224: polarity switching unit

223: The third multiplexer

L1-L2, L21-L23: data lines

V1-V4, V _COM : Voltage

S1-S4, SP1-SP3: signal

320, 330: Triggers

310, 521-538: Inverter

411, 413, 415, 416, 501-512: AND gate

421-423: OR gate

601-612: Transistors

D1, D2, CLK1, CLK2, CLKB1, CLKB2, Q1, Q2, QB1, QB2: used to illustrate the signal terminals in Figure 3

FR, FG, FB: Used to illustrate the signal terminals in Figure 4

R1-R4, G1-G4, B1-B4: used to illustrate the signal terminals in Figure 5

P1-P3: Used to illustrate the signal terminals in Figure 6.

Detailed ways

FIG. 1 shows a structural diagram of a display driver coupled to a display panel according to an embodiment of the present invention. In FIG. 1 , a display driver 100 includes a driving circuit 101 and a testing circuit 102 . The driving circuit 101 is electrically connected to the display panel 130 through a plurality of wires. The test circuit 102 includes a test control unit 110 and a switch unit 120 . The test control unit 110 determines a test mode according to the control signal S1, wherein the test mode includes a first mode and a second mode. The switch unit 120 is coupled to the display panel 130 and receives the first grayscale voltage V1 and the second grayscale voltage V2. The switch unit 120 is controlled by the test control unit 110 . Through the switch unit 120 , the test control unit 110 can decide to output the first grayscale voltage V1 or the second grayscale voltage V2 to the data lines of the display panel 130 . In FIG. 1 , only the first data line L1 and the second data line L2 are shown to represent a plurality of data lines of the display panel 130 .

In the first mode, the switch unit 120 selects to transmit the first grayscale voltage V1 to the first data line L1 and to transmit the second grayscale voltage V2 to the second data line L2. In the second mode, the switch unit 120 selects to transmit the first grayscale voltage V1 to the second data line L2, and to transmit the second grayscale voltage V2 to the first data line L1.

It is assumed here that in the display panel 130 , the first data line L1 is connected to the pixel unit of the first color, and the second data line L2 is connected to the pixel unit of the second color. Therefore, through the control of the control signal S1, the test circuit 102 can drive the display panel 130 to display the first color image in the first mode, and drive the display panel 130 to display the second color image in the second mode, and detect Assembly quality.

For a chip-on-film display driver, the display includes a display panel, a driver packaged on a film, and an X circuit board. The X circuit board is electrically connected with the display panel through the film. The traditional test method is to use the timing controller to generate samples to drive the display panel through the driver, and then determine whether the assembly quality is good or not according to the displayed picture. However, using the timing controller to generate samples requires more input probes, thereby increasing the test cost.

In this embodiment, the test sample is generated by the test circuit 102 of the driver 100, so the timing controller can not be used to generate the test sample to test whether the electrical connection between the film and the display panel 130 is correct, so that the test time can be reduced. The number of probes required.

Another embodiment will be described below. FIG. 1A is a characteristic curve diagram illustrating gray scale voltage and gray scale of a display panel under the application condition of "polarity switching" according to an embodiment of the present invention. If the application requirement of "polarity conversion" is considered, the switch unit 120 can further receive the third gray-scale voltage V3 and the fourth gray-scale voltage V4. Here, it is assumed that the gray-scale voltages V1 and V2 are positive gray-scale voltages, and the gray-scale voltages V3 and V4 are negative gray-scale voltages.

Please refer to FIG. 1 and FIG. 1A , in this embodiment, the test control unit 110 includes a counter 111 and a logic unit 112 , wherein the counter 111 is coupled to the logic unit 112 . The switch unit 120 includes a first multiplexer 121, a second multiplexer 122, and a polarity switching unit 124, wherein the polarity switching unit 124 is coupled to the first multiplexer 121, the second multiplexer Multiplexer 122 and logic unit 112 . In addition, the display panel 130 has a first data line L1 and a second data line L2, wherein the first data line L1 is coupled to the first multiplexer 121, and the second data line L2 is coupled to the second multiplexer 121. multiplexer 122 .

First, the test control unit 110 determines a test mode according to the received control signal S1, and the test mode includes a first mode and a second mode. In more detail, the internal counter 111 of the test control unit 110 generates a count value according to the trigger of the control signal S1, and the internal logic unit 112 activates the first mode or the second mode according to the count value, and Simultaneously output a color signal corresponding to the first mode or the second mode. Then, the switch unit 120 responds to the control of the color signal of the test control unit 110, transmits the first gray-scale voltage V1 or the fourth gray-scale voltage V4 to the first data line L1 in the first mode, and transmits the second gray-scale voltage V2 Or the third grayscale voltage V3 is transmitted to the second data line L2, and in the second mode, the first grayscale voltage V1 or the fourth grayscale voltage V4 is transmitted to the second data line L2, and the second grayscale voltage V2 or the third gray scale voltage V3 is transmitted to the first data line L1.

That is to say, after the polarity switching unit 124 receives a switching signal SP1, it will control the first multiplexer 121 and the second multiplexer 121 according to the switching signal SP1 and the color signal output by the test control unit 110. The output of device 122. In other words, the first multiplexer 121 outputs the first grayscale voltage V1 or the fourth grayscale voltage V4 in the first mode in response to the control of the polarity switching unit 124, and outputs the second grayscale voltage V4 in the second mode. The gray-scale voltage V2 or the third gray-scale voltage V3. In response to the control of the polarity switching unit 124, the second multiplexer 122 outputs the first gray-scale voltage V1 or the fourth gray-scale voltage V4 in the second mode, and outputs the second gray-scale voltage V2 in the first mode. Or the third gray scale voltage V3.

Therefore, in the first mode, the first data line L1 of the display panel 130 receives the first grayscale voltage V1 or the fourth grayscale voltage V4 to display the first color picture; in the second mode, the second data line L2 Receive the first grayscale voltage V1 or the fourth grayscale voltage V4 to display the second color picture. Therefore, by switching the switching signal SP1, besides displaying the first color picture or the second color picture, the polarity switching of the liquid crystal molecules can also be taken into account, so that the liquid crystal molecules can work normally.

FIG. 2 shows a structural diagram of a display driver coupled to a display panel according to another embodiment of the present invention. In FIG. 2 , only the first data line L21 , the second data line L22 and the third data line L23 are shown to represent a plurality of data lines of the display panel 230 . In FIG. 2 , the display driver includes a driving circuit 201 and a testing circuit 202 . The driving circuit 201 is electrically connected to the display panel 230 through a plurality of wires. The test circuit 202 includes a test control unit 210 and a switch unit 220 . Wherein, the test control unit 210 is coupled to the switch unit 220 . The test control unit 210 receives a control signal S2, and determines a test mode according to the control signal S2. The switch unit 220 is coupled to the display panel 230 for receiving the first gray-scale voltage V1 , the second gray-scale voltage V2 , the third gray-scale voltage V3 and the fourth gray-scale voltage V4 . Further, the test control unit 210 includes a counter 211 and a logic unit 212 , wherein the counter 211 is coupled to the logic unit 212 . The switch unit 220 includes a first multiplexer 221, a second multiplexer 222, a third multiplexer 223 and a polarity switching unit 224, wherein the polarity switching unit 224 is coupled to the first multiplexer The multiplexer 221 , the second multiplexer 222 , the third multiplexer 223 and the logic unit 212 . In addition, the display panel 230 has a first data line L21, a second data line L22 and a third data line L23, wherein the first data line L21 is coupled to the first multiplexer 221, and the second data line L22 is coupled to To the second multiplexer 222 , the third data line L23 is coupled to the third multiplexer 223 .

In this embodiment, the test mode of the test control unit 210 includes a first mode, a second mode and a third mode, which are selected according to a control signal S2. More specifically, the counter 211 inside the test control unit 210 generates a count value according to the trigger of the control signal S2, and the logic unit 212 activates the first, second or third mode according to the count value, and outputs the corresponding A color signal in the first, second or third mode.

Next, the switch unit 220 responds to the control of the test control unit 210, and transmits the first grayscale voltage V1 to the first data line L21 in the first mode, and transmits the second grayscale voltage V2 to the second data line L22 and the second data line L22. Three data lines L23. In the second mode, the first grayscale voltage V1 is transmitted to the second data line L22, and the second grayscale voltage V2 is transmitted to the first data line L21 and the third data line L23. In the third mode, the first grayscale voltage V1 is transmitted to the third data line L23, and the second grayscale voltage V2 is transmitted to the first data line L21 and the second data line L22. That is to say, the first multiplexer 221 inside the switch unit 220 outputs the first grayscale voltage V1 in the first mode according to the color signal, and outputs the second grayscale voltage in the second mode and the third mode. V2. The second multiplexer 222 outputs the first grayscale voltage V1 in the second mode according to the color signal, and outputs the second grayscale voltage V2 in the first mode and the third mode. The third multiplexer 223 outputs the first grayscale voltage V1 in the third mode according to the color signal, and outputs the second grayscale voltage V2 in the first mode and the second mode. In this embodiment, the first grayscale voltage V1 makes the grayscale displayed by the corresponding pixel bright, and the second grayscale voltage V2 makes the grayscale displayed by the corresponding pixel black.

In addition, when considering the polarity conversion of the liquid crystal, the polarity switching unit 224 inside the switch unit 220 will receive a switching signal SP2, and control the first multiplexer 221, the second multiplexer 221 according to the switching signal SP2 and the color signal. Outputs of the multiplexer 222 and the third multiplexer 223 . Therefore, the first multiplexer 221 outputs the first grayscale voltage V1 or the fourth grayscale voltage V4 in the first mode, and outputs the second grayscale voltage V2 or the third grayscale voltage in the second mode and the third mode. Gray scale voltage V3. The second multiplexer 222 outputs the first grayscale voltage V1 or the fourth grayscale voltage V4 in the second mode, and outputs the second grayscale voltage V2 or the third grayscale voltage in the first mode and the third mode Voltage V3. And the third multiplexer 223 outputs the first gray-scale voltage V1 or the fourth gray-scale voltage V4 in the third mode, and outputs the second gray-scale voltage V2 or the third gray-scale voltage in the first mode and the second mode. Gray scale voltage V3. Therefore, the display panel 230 will receive the first grayscale voltage V1 or the fourth grayscale voltage V4 according to the first data line L21 in the first mode to display the first color picture, and in the second mode according to the second data line L22 receives the first grayscale voltage V1 or the fourth grayscale voltage V4 to display the second color picture, and in the third mode, receives the first grayscale voltage V1 or the fourth grayscale voltage V4 according to the third data line L23 to display Tertiary color screen. In this embodiment, the fourth grayscale voltage V4 makes the grayscale displayed by the corresponding pixel bright, and the third grayscale voltage V3 makes the grayscale displayed by the corresponding pixel black.

It is worth mentioning that when the test mode of the test control unit 210 further includes a fourth mode, the display panel 230 can further display a fourth color image. Now continue to use FIG. 2 to illustrate the implementation of the test circuit 202 when it has the fourth mode. First, similar to the above-mentioned embodiment, after the counter 211 receives a control signal S3, it will output a count value according to this signal, and the logic unit 212 will enable the first, second, third or fourth control signal according to this count value. mode, and simultaneously output a color signal corresponding to the first, second, third or fourth mode. Next, when the switch unit 220 is in the fourth mode, it will simultaneously transmit the first grayscale voltage V1 to the first data line L21, the second data line L22 and the third data line L23, and for the operations of the first to third modes Then it is similar to the above embodiment. That is to say, the first multiplexer 221 inside the switch unit 220 outputs the first grayscale voltage V1 in the first mode and the fourth mode according to the color signal, and outputs the first grayscale voltage V1 in the second mode and the third mode. The second grayscale voltage V2. The second multiplexer 222 outputs the first grayscale voltage V1 in the second mode and the fourth mode according to the color signal, and outputs the second grayscale voltage V2 in the first mode and the third mode. The third multiplexer 223 outputs the first grayscale voltage V1 in the third mode and the fourth mode according to the color signal, and outputs the second grayscale voltage V2 in the first mode and the second mode. In addition, considering the polarity conversion, the polarity switching unit 224 inside the switch unit 220 will receive a switching signal SP3, and control the first multiplexer 221, the second multiplexer 221 and the second multiplexer 221 according to the signal and the color signal. The outputs of the multiplexer 222 and the third multiplexer 223 . Therefore, the first multiplexer 221 outputs the first gray-scale voltage V1 or the fourth gray-scale voltage V4 in the first mode and the fourth mode, and outputs the second gray-scale voltage in the second mode and the third mode. V2 or the third gray scale voltage V3. The second multiplexer 222 outputs the first grayscale voltage V1 or the fourth grayscale voltage V4 in the second mode and the fourth mode, and outputs the second grayscale voltage V2 or the fourth grayscale voltage in the first mode and the third mode. The third grayscale voltage V3. The third multiplexer 223 outputs the first gray-scale voltage V1 or the fourth gray-scale voltage V4 in the third mode and the fourth mode, and outputs the second gray-scale voltage V2 in the first mode and the second mode. Or the third grayscale voltage V3.

Therefore, the display panel 230 will receive the first grayscale voltage V1 or the fourth grayscale voltage V4 according to the first data line L21 in the first mode to display the first color picture, and in the second mode according to the second data line L22 receives the first grayscale voltage V1 or the fourth grayscale voltage V4 to display the second color picture, and in the third mode, receives the first grayscale voltage V1 or the fourth grayscale voltage V4 according to the third data line L23 to display Tertiary color screen. In the fourth mode, the display panel 230 receives the first gray-scale voltage V1 or the fourth gray-scale voltage V4 simultaneously according to the data lines L21-L23 to display the fourth color picture. That is to say, the fourth color frame is formed by mixing the first to third color frames. For example, assuming that the first to third colors are red, green and blue respectively, the fourth color is white after mixing.

For a display with color filters, for example, the first data line supplies red pixels, the second data line supplies green pixels, and the third data line supplies blue pixels, for example. Therefore, in the first mode, the displayed picture is red; in the second mode, the displayed picture is green; in the third mode, the displayed picture is blue; in the fourth mode, the displayed picture is white. In each mode, the quality can be judged by checking whether the screen is abnormal. The implementation of each unit in the above-described embodiments will be described below. FIG. 3 shows an implementation of the counter 211 in the four test modes of FIG. 2 . In FIG. 3 , the counter 211 includes an inverter 310 , a first flip-flop 320 and a second flip-flop 330 . Wherein, the inverted output terminal QB1 of the first flip-flop 320 is coupled to its input terminal D1, its inverted clock input terminal CLKB1 is coupled to the output terminal of the inverter 310, and its clock input terminal CLK1 is coupled to the inverter 310 and receives the control signal S3. The inverting output terminal QB2 of the second flip-flop 330 is coupled to its input terminal D2, its inverting clock input terminal CLKB2 is coupled to the output terminal Q1 of the first flip-flop 320, and its clock input terminal CLK2 is coupled to the first trigger The inverting output terminal QB1 of device 320. Therefore, after the control signal S3 is input to the input terminal of the inverter 310, the output terminal Q1 of the first flip-flop 320 and the output terminal Q2 of the second flip-flop 330 are respectively used as the first output terminal and the second output terminal of the counter 210 , the count value shown in the table below can be obtained.

Q2 Q1

0 0

0 1

1 0

1 1

Therefore, the first group (0 0) of the count value (Q2 Q1) can be set as the first mode, the second group (0 1) can be set as the second mode, and the third group (1 0) can be set as the second mode. Three modes, the fourth group (1 1) is set as the fourth mode. However, those skilled in the art should know that the structure of the counter is not limited to the embodiment shown in FIG. 3 , as long as it can generate signals corresponding to these modes, it is in line with the spirit of the present invention.

FIG. 4 shows an implementation of the logic unit 212 in the four test modes of FIG. 2 . In FIG. 4, logic unit 212 includes AND gate 411, AND gate 413, AND gate 415, AND gate 416, and OR gates 421-423. Two input terminals of the AND gate 411 are respectively coupled to the inverting output terminal QB1 of the first flip-flop 320 and the inverting output terminal QB2 of the second flip-flop 330 . Two input terminals of the AND gate 413 are respectively coupled to the output terminal Q1 of the first flip-flop 320 and the inverting output terminal QB2 of the second flip-flop 330 . Two input terminals of the AND gate 415 are respectively coupled to the inverting output terminal QB1 of the first flip-flop 320 and the output terminal Q2 of the second flip-flop 330 . Two input terminals of the AND gate 416 are respectively coupled to the output terminal Q1 of the first flip-flop 320 and the output terminal Q2 of the second flip-flop 330 . The two input terminals of the OR gate 421 are respectively coupled to the output terminals of the AND gates 411 and 416 . The two input terminals of the OR gate 422 are respectively coupled to the output terminals of the AND gates 413 and 416. The two input terminals of the OR gate 423 are respectively coupled to the output terminals of the AND gates 415 and 416 . Then, after the counter 210 outputs a count value, the output terminals of the OR gates 421, 422 and 423 are respectively used as the first output terminal FR, the second output terminal FG and the third output terminal FB of the logic unit 220, and the following can be obtained (The value 100 in the comparison table represents the color signal corresponding to the first mode, the value 010 represents the color signal corresponding to the second mode, and so on).

test mode Q2 Q1 FR FG FB First mode Second mode Third mode Fourth mode 0011 0101 1001 0101 0011

Fig. 5 shows an implementation of the polarity switching unit in Fig. 2 in four test modes. In FIG. 5, the polarity switching unit 224 includes AND gates 501-512 and inverters 521-538. Among them, the AND gates 501-512 and the inverters 521-538 are divided into three groups of similar circuit structures, the AND gates 501-504 and the inverters 521-526 are the first group, and the AND gates 505-508 and the inverters 527-532 are the second group, and AND gates 509-512 and inverters 533-538 are the third group. In the first group of circuit structures, the output terminal of the AND gate 501 is coupled to the input terminal of the inverter 521, and one input terminal thereof receives the switching signal SP3, and the other input terminal thereof is coupled to the first output terminal FR of the logic unit 220 . The output end of the AND gate 502 is coupled to the input end of the inverter 522, and one input end receives the switching signal SP3, and the other input end receives the output from the first output end FR of the logic unit 220 through the inverter 523 Inverted signal. One input terminal of the AND gate 503 receives the inverted signal of the switching signal SP3 through the inverter 524 , and the other input terminal receives the inverted signal output from the first output terminal FR of the logic unit 220 through the inverter 525 . One input terminal of the AND gate 503 receives the inverted signal of the switching signal SP2 through the inverter 526 , and the other input terminal receives the signal output from the first output terminal FR of the logic unit 220 .

In addition, the second group and the third group circuit structure in FIG. 5 are similar to the first group circuit structure in their coupling methods, the only difference is that the received signal is different, and the second group circuit structure is the second circuit structure corresponding to the logic unit. The output terminal FG, and the third group of circuit structures are corresponding to the third output terminal FB of the logic unit, so the coupling method thereof will not be described here.

Following the above, now assume that the output terminals of the inverters 521, 522 and the AND gates 503 and 504 are the output terminals R1-R4 of the polarity switching unit in sequence, and the output terminals of the inverters 527, 528 and the AND gates 507 and 508 The terminals are assumed to be the output terminals G1-G4 of the polarity switching unit in sequence, and the output terminals of the inverters 533, 534 and the AND gates 511 and 512 are assumed to be the output terminals B1-B4 of the polarity switching unit in sequence, so it can be The following table of output values of the polarity switching unit 224 is obtained.

model SP3 FR R1 R2 R3 R4 2, 31, 42, 31, 4 0011 0101 1110 1101 1000 0100

model SP3 FR R1 R2 R3 R4 model SP3 FG G1 G2 G3 G4 1, 32, 41, 3 001 010 111 110 100 010

2, 4 1 1 0 1 0 0 model SP3 FB B1 B2 B3 B4 2, 13, 42, 13, 4 0011 0101 1110 1101 1000 0100

FIG. 6 shows an implementation manner of the first multiplexer 221 , the second multiplexer 222 and the third multiplexer 223 in four test modes in FIG. 2 . In FIG. 6, the first multiplexer 221 includes P-type transistors 601, 602 and N-type transistors 603, 604, and the second multiplexer 222 includes P-type transistors 605, 606 and N-type transistors 607, 608. , the third multiplexer 223 includes P-type transistors 609 , 610 and N-type transistors 611 , 612 . Continuing to refer to FIG. 6, the control terminals of the transistors 601-604 are sequentially coupled to the output terminals R1-R4 of the polarity switching unit 224, and the first terminal of the transistor 601 receives the first grayscale voltage V1, and the first terminal of the transistor 602 receives the For the second grayscale voltage V2, the first terminal of the transistor 603 receives the third grayscale voltage V3, and the first terminal of the transistor 604 receives the fourth grayscale voltage V4. The control terminals of the transistors 605-608 are sequentially coupled to the output terminals G1-G4 of the polarity switching unit 224, and the first terminal of the transistor 605 receives the first gray-scale voltage V1, and the first terminal of the transistor 606 receives the second gray-scale voltage V2, the first terminal of the transistor 607 receives the third grayscale voltage V3, and the first terminal of the transistor 608 receives the fourth grayscale voltage V4.

As mentioned above, the control terminals of the transistors 609-612 are sequentially coupled to the output terminals B1-B4 of the polarity switching unit 224, and the first terminal of the transistor 609 receives the first grayscale voltage V1, and the first terminal of the transistor 610 receives the first grayscale voltage V1. For the second grayscale voltage V2, the first terminal of the transistor 611 receives the third grayscale voltage V3, and the first terminal of the transistor 612 receives the fourth grayscale voltage V4. In addition, the second terminals of the transistors 601-604 are coupled to each other and serve as the output terminal P1 of the first multiplexer 221, and the second terminals of the transistors 605-608 are coupled to each other and serve as the output terminal P1 of the second multiplexer 222. output terminal P2 , and the second terminals of the transistors 609 - 612 are coupled to each other and serve as the output terminal P3 of the third multiplexer 223 . Thus, the following table of output values of each multiplexer can be obtained.

model R1 R2 R3 R4 P1 2, 31, 42, 31, 4 1110 1101 1000 0100 V3V4V2V1

model G1 G2 G3 G4 P2 1, 32, 41, 32, 4 1110 1101 1000 0100 V3V4V2V1 model B1 B2 B3 B4 P3 2, 13, 42, 13, 4 1110 1101 1000 0100 V3V4V2V1

Therefore, in the first mode, the display panel 230 will receive the first grayscale voltage V1 or the fourth grayscale voltage V4 according to the first data line L21 to display the first color picture, and in the second mode according to the second data The line L22 receives the first grayscale voltage V1 or the fourth grayscale voltage V4 to display the second color picture, and in the third mode, receives the first grayscale voltage V1 or the fourth grayscale voltage V4 according to the third data line L23 to display Displays the third color screen. In the fourth mode, the display panel 230 displays the fourth color picture according to the first, second and third data lines L21-L23 simultaneously receiving the first gray-scale voltage V1 or the fourth gray-scale voltage V4.

FIG. 7 shows a structural diagram of a display driver according to another embodiment of the present invention. In FIG. 7 , a display driver 700 includes a test circuit 710 . The test circuit 710 includes a test control unit 711 and a switch unit 712 , wherein the test control unit 711 is coupled to the switch unit 712 . When the display driver 700 is coupled to a display panel, the test control unit 711 receives a control signal S4, and determines the test mode according to this signal, and the switch unit 712 receives the first to fourth gray scale voltages V1-V4, which are based on the test The control unit 711 controls to output the received gray scale voltage to the display panel. For the overall operation of the test circuit 710 , reference may be made to the above-mentioned embodiments, which will not be repeated here.

To sum up, the embodiment of the present invention is to build a test circuit in the driver, so that the driver can use the test circuit to generate test samples and output them to the coupled display panel, and judge the assembly quality by displaying the test samples Advantages and disadvantages, so the test purpose can be achieved without using a timing controller. In addition, during the test process, the test circuit and the display driver of the embodiment of the present invention only need to input control signals and switching signals, so a small number of test pins can be used to achieve the test purpose, so in addition to simplifying the test process and improving the test speed In addition, it can effectively reduce production costs.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and changes without departing from the spirit and scope of the present invention. Modification, so the scope of protection of the present invention should be defined by the patent scope of the present invention.

Claims (36)

1. test circuit, this test circuit is built in the display driver, and in order to test a display panel, this test circuit comprises:

Unit of testing and controlling, it determines test pattern according to a control signal, wherein, this test pattern comprises one first pattern and one second pattern; And

Switch element, it is coupled to this display panel and receives first gray scale voltage and second gray scale voltage, and this switch element is controlled by this unit of testing and controlling;

Wherein, this display panel comprises one first data line and one second data line;

This switch element is selected to allow this first gray scale voltage send this first data line in this first pattern, and allows this second gray scale voltage send this second data line to; And

This switch element is selected to allow this first gray scale voltage send this second data line in this second pattern, and allows this second gray scale voltage send this first data line to.

2. test circuit as claimed in claim 1, wherein, this test pattern more comprises three-mode, and this display panel more comprises the 3rd data line;

This switch element is selected to allow this first gray scale voltage send this first data line in this first pattern, and allows this second gray scale voltage send this second data line and the 3rd data line to;

This switch element is selected to allow this first gray scale voltage send this second data line in this second pattern, and allows this second gray scale voltage send this first data line and the 3rd data line to; And

This switch element is selected to allow this first gray scale voltage send the 3rd data line in this three-mode, and allows this second gray scale voltage send this first data line and this second data line to.

3. test circuit as claimed in claim 2, wherein, this test pattern more comprises four-mode; And

This switch element is selected to allow this first gray scale voltage send this first data line, this second data line and the 3rd data line in this four-mode.

4. test circuit as claimed in claim 1, wherein, this display panel shows one first color picture and one second color picture respectively in this first pattern and this second pattern.

5. test circuit as claimed in claim 2, wherein, this display panel shows one the 3rd color picture at this three-mode.

6. test circuit as claimed in claim 3, wherein, this display panel shows the 4th color picture at this four-mode.

7. test circuit as claimed in claim 1, wherein, this unit of testing and controlling comprises:

Counter, it is according to triggering for generating one count value of this control signal; And

Logical block, it selects to enable this first pattern or this second pattern according to this count value, and exports a color signal.

8. test circuit as claimed in claim 7, wherein, this switch element comprises:

First multiplexer is coupled to this first data line, and it selects this first gray scale voltage of output when this first pattern according to this color signal, and selects this second gray scale voltage of output when this second pattern; And

One second multiplexer is coupled to this second data line, and it selects this first gray scale voltage of output when this second pattern according to this color signal, and selects this second gray scale voltage of output when this first pattern.

9. test circuit as claimed in claim 8, wherein, this switch element more receives the 3rd gray scale voltage and the 4th gray scale voltage.

10. test circuit as claimed in claim 9, wherein, this switch element more comprises:

Polarity switched cell couples this first multiplexer and this second multiplexer, and it controls the output of this first multiplexer and this second multiplexer according to switching signal and this color signal;

Wherein, this first multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this first pattern in response to the control of this polarity switched cell, and selects this second gray scale voltage of output or the 3rd gray scale voltage when this second pattern; And

This second multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this second pattern in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern.

11. test circuit as claimed in claim 2, wherein, this unit of testing and controlling comprises:

Counter, it is according to the triggering for generating count value of this control signal; And

Logical block, it selects to enable this first pattern, this second pattern or this three-mode according to this count value, and exports a color signal.

12. test circuit as claimed in claim 11, wherein, this switch element comprises:

First multiplexer is coupled to this first data line, and it selects this first gray scale voltage of output when this first pattern according to this color signal, and selects this second gray scale voltage of output when this second pattern and this three-mode;

Second multiplexer is coupled to this second data line, and it selects this first gray scale voltage of output when this second pattern according to this color signal, and selects this second gray scale voltage of output when this first pattern and this three-mode; And

The 3rd multiplexer is coupled to the 3rd data line, and it selects this first gray scale voltage of output when this three-mode according to this color signal, and selects this second gray scale voltage of output when this first pattern and this second pattern.

13. test circuit as claimed in claim 12, wherein, this switch element more receives the 3rd gray scale voltage and the 4th gray scale voltage.

14. test circuit as claimed in claim 13, wherein, this switch element more comprises:

Polarity switched cell, couple this first multiplexer, this second multiplexer and the 3rd multiplexer, it controls the output of this first multiplexer, this second multiplexer and the 3rd multiplexer according to a switching signal and this color signal;

Wherein, this first multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this first pattern in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this second pattern and this three-mode;

This second multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this second pattern in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern and this three-mode; And

The 3rd multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this three-mode in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern and this second pattern.

15. test circuit as claimed in claim 3, wherein, this unit of testing and controlling comprises:

Counter, it is according to triggering for generating one count value of this control signal; And

Logical block, it selects to enable this first pattern, this second pattern, this three-mode or this four-mode according to this count value, and exports a color signal.

16. test circuit as claimed in claim 15, wherein, this switch element comprises:

First multiplexer is coupled to this first data line, and it selects this first gray scale voltage of output when this first pattern and this four-mode according to this color signal, and selects this second gray scale voltage of output when this second pattern and this three-mode;

Second multiplexer is coupled to this second data line, and it selects this first gray scale voltage of output when this second pattern and this four-mode according to this color signal, and selects this second gray scale voltage of output when this first pattern and this three-mode; And

The 3rd multiplexer is coupled to the 3rd data line, and it selects this first gray scale voltage of output when this three-mode and this four-mode according to this color signal, and selects this second gray scale voltage of output when this first pattern and this second pattern.

17. test circuit as claimed in claim 16, wherein, this switch element more receives the 3rd gray scale voltage and the 4th gray scale voltage.

18. test circuit as claimed in claim 17, wherein, this switch element more comprises:

Polarity switched cell, couple this first multiplexer, this second multiplexer and the 3rd multiplexer, it controls the output of this first multiplexer, this second multiplexer and the 3rd multiplexer according to a switching signal and this color signal;

Wherein, this first multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this first pattern and this four-mode in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this second pattern and this three-mode;

This second multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this second pattern and this four-mode in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern and this three-mode; And

The 3rd multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this three-mode and this four-mode in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern and this second pattern.

19. a display driver electrically connects with a display panel by many leads, this display driver comprises:

Test circuit comprises:

Unit of testing and controlling, it determines test pattern according to a control signal, wherein, this test pattern comprises one first pattern and one second pattern; And

Switch element, it is coupled to this display panel and receives one first gray scale voltage and one second gray scale voltage, and this switch element is controlled by this unit of testing and controlling;

Wherein, this display panel comprises first data line and second data line;

Wherein, this switch element is selected to allow this first gray scale voltage send this first data line in this first pattern, and allows this second gray scale voltage send this second data line to; And

Wherein, this switch element is selected to allow this first gray scale voltage send this second data line in this second pattern, and allows this second gray scale voltage send this first data line to.

20. display driver as claimed in claim 19, wherein, this test pattern more comprises a three-mode, and this display panel more comprises one the 3rd data line;

This switch element is selected to allow this first gray scale voltage send this first data line in this first pattern, and allows this second gray scale voltage send this second data line and the 3rd data line to;

This switch element is selected to allow this first gray scale voltage send this second data line in this second pattern, and allows this second gray scale voltage send this first data line and the 3rd data line to; And

This switch element is selected to allow this first gray scale voltage send the 3rd data line in this three-mode, and allows this second gray scale voltage send this first data line and this second data line to.

21. display driver as claimed in claim 20, wherein, this test pattern more comprises four-mode; And

This switch element is selected to allow this first gray scale voltage send this first data line, this second data line and the 3rd data line in this four-mode.

22. display driver as claimed in claim 19, wherein, this display panel shows the first color picture and the second color picture respectively in this first pattern and this second pattern.

23. display driver as claimed in claim 20, wherein, this display panel shows the 3rd color picture at this three-mode.

24. display driver as claimed in claim 21, wherein, this display panel shows the 4th color picture at this four-mode.

25. display driver as claimed in claim 19, wherein, this unit of testing and controlling comprises:

Counter, it is according to triggering for generating one count value of this control signal; And

Logical block, it selects to enable this first pattern or this second pattern according to this count value, and the output color signal.

26. display driver as claimed in claim 25, wherein, this switch element comprises:

First multiplexer is coupled to this first data line, and it selects this first gray scale voltage of output when this first pattern according to this color signal, and selects this second gray scale voltage of output when this second pattern; And

Second multiplexer is coupled to this second data line, and it selects this first gray scale voltage of output when this second pattern according to this color signal, and selects this second gray scale voltage of output when this first pattern.

27. display driver as claimed in claim 26, wherein, this switch element more receives the 3rd gray scale voltage and the 4th gray scale voltage.

28. display driver as claimed in claim 27, wherein, this switch element more comprises:

Polarity switched cell couples this first multiplexer and this second multiplexer, and it controls the output of this first multiplexer and this second multiplexer according to switching signal and this color signal;

Wherein, this first multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this first pattern in response to the control of this polarity switched cell, and selects this second gray scale voltage of output or the 3rd gray scale voltage when this second pattern; And

This second multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this second pattern in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern.

29. display driver as claimed in claim 20, wherein, this unit of testing and controlling comprises:

Counter, it is according to triggering for generating one count value of this control signal; And

Logical block, it selects to enable this first pattern, this second pattern or this three-mode according to this count value, and the output color signal.

30. display driver as claimed in claim 29, wherein, this switch element comprises:

First multiplexer is coupled to this first data line, and it selects this first gray scale voltage of output when this first pattern according to this color signal, and selects this second gray scale voltage of output when this second pattern and this three-mode;

Second multiplexer is coupled to this second data line, and it selects this first gray scale voltage of output when this second pattern according to this color signal, and selects this second gray scale voltage of output when this first pattern and this three-mode; And

The 3rd multiplexer is coupled to the 3rd data line, and it selects this first gray scale voltage of output when this three-mode according to this color signal, and selects this second gray scale voltage of output when this first pattern and this second pattern.

31. display driver as claimed in claim 30, wherein, this switch element more receives the 3rd gray scale voltage and the 4th gray scale voltage.

32. display driver as claimed in claim 31, wherein, this switch element more comprises:

Polarity switched cell, couple this first multiplexer, this second multiplexer and the 3rd multiplexer, it controls the output of this first multiplexer, this second multiplexer and the 3rd multiplexer according to a switching signal and this color signal;

Wherein, this first multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this first pattern in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this second pattern and this three-mode;

This second multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this second pattern in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern and this three-mode; And

The 3rd multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this three-mode in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern and this second pattern.

33. display driver as claimed in claim 21, wherein, this unit of testing and controlling comprises:

Counter, it is according to triggering for generating one count value of this control signal; And

Logical block, it selects to enable this first pattern, this second pattern, this three-mode or this four-mode according to this count value, and exports a color signal.

34. display driver as claimed in claim 33, wherein, this switch element comprises:

First multiplexer is coupled to this first data line, and it selects this first gray scale voltage of output when this first pattern and this four-mode according to this color signal, and selects this second gray scale voltage of output when this second pattern and this three-mode;

Second multiplexer is coupled to this second data line, and it selects this first gray scale voltage of output when this second pattern and this four-mode according to this color signal, and selects this second gray scale voltage of output when this first pattern and this three-mode; And

The 3rd multiplexer is coupled to the 3rd data line, and it selects this first gray scale voltage of output when this three-mode and this four-mode according to this color signal, and selects this second gray scale voltage of output when this first pattern and this second pattern.

35. display driver as claimed in claim 34, wherein, this switch element more receives the 3rd gray scale voltage and the 4th gray scale voltage.

36. display driver as claimed in claim 35, wherein, this switch element more comprises:

Polarity switched cell, couple this first multiplexer, this second multiplexer and the 3rd multiplexer, it controls the output of this first multiplexer, this second multiplexer and the 3rd multiplexer according to a switching signal and this color signal;

Wherein, this first multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this first pattern and this four-mode in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this second pattern and this three-mode;

This second multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this second pattern and this four-mode in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern and this three-mode; And

The 3rd multiplexer is selected this first gray scale voltage of output or the 4th gray scale voltage when this three-mode and this four-mode in response to the control of this polarity switched cell, and select this second gray scale voltage of output or the 3rd gray scale voltage when this first pattern and this second pattern.

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