CN100539069C - Shallow trench isolation from manufacture method - Google Patents

Abstract

A kind of shallow trench isolation from manufacture method, comprise: Semiconductor substrate is provided, on described Semiconductor substrate, have the pad oxide and the hard mask layer that form successively, in described Semiconductor substrate, be formed with groove, in described pad oxide and described hard mask layer, have opening with the corresponding position of groove; In described groove He on the described hard mask layer, form dielectric layer, and remove dielectric layer material on the described hard mask layer by flatening process; Dielectric layer in the described groove of etching makes the dielectric layer surface in the described groove reduce with difference in height between the described semiconductor substrate surface, and makes described dielectric layer edge formation projection.The present invention can reduce the degree of depth of shallow trench isolation from the top groove, increases the performance of device.

Description

Manufacturing method of shallow trench isolation

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing shallow trench isolation (Shallow Trench Isolation, STI).

Background technique

With the development of semiconductor manufacturing technology to high-tech nodes, the device-to-device isolation technology in semiconductor integrated circuits has also evolved from the original Local Oxidation of Silicon (LOCOS) to shallow trench isolation. Shallow trench isolation is formed by forming a trench on a semiconductor substrate and filling the trench with a dielectric material. The Chinese patent application document with publication number CN 1649122A discloses a manufacturing method for shallow trench isolation. FIG. 1 to FIG. 5 are schematic cross-sectional views of structures corresponding to each step of the manufacturing method of shallow trench isolation disclosed in the Chinese patent application documents.

As shown in FIG. 1 , a semiconductor substrate 12 is provided, a pad oxide layer 12A is formed on the semiconductor substrate 12, and then a silicon nitride layer is formed on the pad oxide layer 12A as a first hard mask layer 14. A second hard mask layer 14B is formed on the first hard mask layer 14, a photoresist layer 16A is formed on the second hard mask layer 14B, and the photoresist layer 16A is patterned to form a bottom exposed The opening 16B of the second hard mask layer 14B.

As shown in FIG. 2, the second hard mask layer 14B, the first hard mask layer 14 and the pad oxide layer 12A at the bottom of the opening 16B are etched to form an opening 16C, and the bottom of the opening 16C exposes the semiconductor substrate. The surface of the bottom 12.

As shown in FIG. 3, the photoresist layer 16A is removed, the semiconductor substrate 12 at the bottom of the opening 16C is etched, a groove 18 is formed in the semiconductor substrate 12, and a groove 18 is formed on the surface of the groove 18. Pad oxide layer 20.

As shown in FIG. 4 , the oxide layer 22 is filled in the trench 18 , and then the redundant oxide layer 22 on the second hard mask layer 14B and the second hard mask layer 14B are removed by chemical mechanical polishing.

As shown in FIG. 5 , the first hard mask layer 14 is removed by wet etching (such as phosphoric acid), and the pad oxide layer 12A is removed by hydrofluoric acid solution.

However, when the pad oxide layer 12A is removed by the hydrofluoric acid solution in the manufacturing method of the above shallow trench isolation, the hydrofluoric acid solution will also corrode the oxide layer 22, so that the A groove is formed on the top edge, such as the groove 21 shown in FIG. 6 , which causes the device close to the groove 21 to increase leakage current and decrease the threshold voltage when operating in the sub-threshold region, which affects the performance of the device.

Contents of the invention

The invention provides a manufacturing method of the shallow trench isolation, which can reduce the depth of the top edge groove of the formed shallow trench isolation.

A method for manufacturing shallow trench isolation provided by the present invention includes:

A semiconductor substrate is provided having a pad oxide layer and a hard mask layer sequentially formed thereon, a trench is formed in the semiconductor substrate, a pad oxide layer and a hard mask layer are formed There is an opening at a position corresponding to the trench; a dielectric layer is formed in the trench and on the hard mask layer, and the dielectric layer material on the hard mask layer is removed through a planarization process; the etching the The dielectric layer in the groove reduces the height difference between the surface of the dielectric layer in the groove and the surface of the semiconductor substrate, and makes the edge of the dielectric layer form a protrusion.

Optionally, the etching method in the step of etching the dielectric layer in the trench is wet etching or dry etching.

Optionally, the etching method in the step of etching the dielectric layer in the trench is wet etching, and the etching rate of the etching solution for the wet etching on the dielectric layer is higher than that on the hard The etch rate of the mask layer is high.

Optionally, the method for etching the dielectric layer in the trench is wet etching, and the steps of the wet etching are as follows: etching the dielectric layer with an etching solution of a first concentration; and then and etching the dielectric layer with an etching solution of a second concentration.

Optionally, the second concentration is less than the first concentration.

Optionally, the method of etching the dielectric layer in the trench is wet etching, the wet etching is divided into multiple times, and the concentration of the etching solution of the wet etching increases with the number of times And reduce.

Optionally, the etching method in the step of etching the dielectric layer in the trench is wet etching, and the etching solution of the wet etching is hydrofluoric acid solution.

Optionally, the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is 1:200 to 1:50.

Optionally, the wet etching time is 10 to 50 seconds.

Optionally, the method for etching the dielectric layer in the trench is dry etching; before the dry etching, a protective layer is formed on the hard mask layer; and after the dry etching is completed, After etching, the protection layer is removed.

Optionally, the protective layer is photoresist.

Optionally, the dielectric layer is one or a combination of silicon oxide and silicon oxynitride.

Optionally, the method further includes: after the step of etching the dielectric layer in the trench is completed, removing the hard mask layer and the pad oxide layer.

Optionally, the method for removing the hard mask layer is wet etching with a phosphoric acid solution; the method for removing the pad oxide layer is wet etching with a hydrofluoric acid solution.

Compared with the prior art, the present invention has the following advantages:

The present invention uses the step of etching the dielectric layer in the trench. On the one hand, the etching process forms a protrusion on the edge of the dielectric layer surface, and the protrusion can slow down the process of removing the pad oxide layer in the subsequent process. Forming a groove or not forming a groove on the edge of the shallow trench isolation can reduce the leakage current of the device formed in the active region caused by the groove, and prevent the leakage of the device in the active region caused by the groove. Threshold voltage drop; In addition, the etching process reduces the height difference between the surface of the dielectric layer in the trench and the surface of the semiconductor substrate, so that in subsequent processes across the semiconductor substrate and the semiconductor substrate The steps formed by the polysilicon gate on the dielectric layer are reduced due to the height difference, which can be used to form a semiconductor device with a relatively stable threshold voltage and meet the performance requirements of the device.

The etching method may be wet etching, through which the residual oxide on the surface of the hard mask layer can be removed to ensure smooth removal of the hard mask layer.

The etching method can be wet etching, divide the wet etching process into two or more times, reduce the time of each etching, and reduce the etching time as the number of etching times increases. The concentration of the solution can facilitate the control of etching to remove the thickness of the dielectric layer, so as to prevent the surface of the dielectric layer from being lower than the surface of the semiconductor substrate.

The etching can be plasma dry etching, and the polymer formed during the dry etching process can gather at the edge of the surface of the dielectric layer, preventing further etching of the dielectric layer material at the edge by the plasma , thereby forming a protrusion, which can slow down the formation of a groove or not form a groove at the edge of the shallow trench isolation when the pad oxide layer is removed in the subsequent process, and can reduce the damage caused by the groove in the active region. The leakage current of the formed device is prevented, and the decrease of the threshold voltage of the device in the active region caused by the groove is prevented. In addition, the plasma dry etching can reduce the height difference between the surface of the dielectric layer and the surface of the semiconductor substrate, which makes the polysilicon gate across the semiconductor substrate and the dielectric layer in the subsequent process Due to the reduction of the steps formed by the height difference, it is useful to form a semiconductor device with a relatively stable threshold voltage and meet the performance requirements of the device;

Description of drawings

1 to 5 are schematic cross-sectional views of structures corresponding to each step of a manufacturing method of shallow trench isolation in the prior art;

6 is a schematic diagram of groove defects caused by the manufacturing method of shallow trench isolation disclosed in the prior art;

7 is a flow chart of an embodiment of the manufacturing method of shallow trench isolation of the present invention;

8 to 17 are schematic cross-sectional views of structures corresponding to each step of the embodiment of the shallow trench isolation manufacturing method of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 7 is a flow chart of an embodiment of the manufacturing method of the shallow trench isolation of the present invention.

As shown in FIG. 7, step 1, providing a semiconductor substrate (S100); a pad oxide layer and a hard mask layer are sequentially formed on the semiconductor substrate, a trench is formed in the semiconductor substrate, and There are openings in the pad oxide layer and the hard mask layer at positions corresponding to the trenches.

As shown in the cross-sectional schematic diagram of FIG. 8, the semiconductor substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon, and the semiconductor substrate 100 may also be one of silicon-germanium compounds and silicon-gallium compounds. The semiconductor substrate 100 may include an epitaxial layer or a silicon-on-insulator (Silicon On Insulator, SOI) structure.

The surface of the semiconductor substrate 100 is cleaned to remove impurity particles or other pollutants on the surface of the semiconductor substrate 100 . A pad oxide layer 110 is formed on the semiconductor substrate 100. The method for forming the pad oxide layer 110 may be one of high-temperature furnace tube oxidation, rapid thermal oxidation, and in-situ water vapor generation oxidation. The pad oxide Layer 110 has a thickness of approximately 5 to 40 nm. The pad oxide layer 110 is used as an adhesive layer between the hard mask layer formed in subsequent processes and the surface of the semiconductor substrate 100 to increase the bonding between the hard mask layer and the surface of the semiconductor substrate 100 property, and balance the stress between the hard mask layer and the surface of the semiconductor substrate 100 . In another embodiment, the pad oxide layer 110 may also be formed by chemical vapor deposition.

Next, a hard mask layer 120 is formed on the pad oxide layer 110. In this embodiment, the hard mask layer 120 is silicon nitride with a thickness of 50 to 300 nm; the method for forming the hard mask layer 120 It can be chemical vapor deposition. The hard mask layer 120 serves as a hard mask for etching trenches in the semiconductor substrate 100 on the one hand, and as a stop layer for CMP planarization of the dielectric material filled in the trenches on the other hand. In other embodiments, the hard mask layer may be multi-layered.

As shown in the cross-sectional schematic diagram of FIG. 9, a photoresist layer 130 is spin-coated on the hard mask layer 120, and a first opening 140 is formed through an exposure and development process, and the bottom of the first opening 140 exposes the hard mask. the surface of the film layer 120. In other embodiments, before spin-coating the photoresist layer 130, an anti-reflection layer (not shown) may be formed on the hard mask layer 120, and the anti-reflection layer may be an inorganic material, such as Silicon oxynitride, or an organic material; then a photoresist layer 130 is formed on the anti-reflection layer, and exposed and developed to form a first opening 140 .

As shown in the cross-sectional schematic diagram of FIG. 10, the hard mask layer 120 and the pad oxide layer 110 at the bottom of the first opening 140 are etched to form a second opening 150, and the bottom of the second opening 150 exposes the semiconductor substrate. 100's of surface. The etching is anisotropic etching, for example, plasma dry etching, and the etching gas of the plasma dry etching may be CF ₄ .

As shown in a schematic cross-sectional view of FIG. 11 , the semiconductor substrate 100 at the bottom of the second opening 150 is etched to form a trench 160 in the semiconductor substrate 100 . The method of etching the trench 160 is plasma dry etching, and the etching gas selected for the plasma dry etching should make the sidewall of the trench 160 relatively smooth, with less silicon lattice defects, and make the bottom corner of the trench 160 smoother, and the etching gas also makes the sidewall of the trench 160 have a more inclined profile, for example, 70 to 90 degrees. The etching gas used for etching may be Cl ₂ or HBr or a mixed gas of HBr and other gases, such as a mixed gas of HBr, O ₂ and Cl ₂ , or a mixed gas of HBr, NF ₃ and He. The depth of the trench 160 formed by etching is controlled by the etching time.

The etching process to form the trench 160 and the etching process to form the second opening 150 can be performed separately in different etching equipment, or can be performed in situ in the same etching equipment. If performed in situ, the two The etching gas and process parameters of the second etching are different; the in-situ etching can improve the yield. If the process of etching to form the trench 160 and the process of etching to form the second opening 150 are carried out in different etching equipment, it can be ashed by oxygen plasma before etching to form the trench 160 Removing the photoresist layer 130 may also remove the photoresist layer 130 after the etching of the groove 160 is completed; photoresist layer 130 .

As shown in the cross-sectional schematic diagram of FIG. 12 , the surface of the trench 160 is cleaned with a hydrofluoric acid solution, and then a liner layer 180 is formed on the surface of the trench 160 by thermal oxidation. By cleaning the hydrofluoric acid solution, the natural oxide layer formed on the surface of the groove 160 can be removed, which is conducive to the formation of the liner layer 180 with a relatively uniform density, so that the liner layer 180 can be used as a semiconductor substrate. The interfacial layer between 100 and the dielectric material filled in the trench 160 has relatively stable characteristics, increases the adhesion between the two, and reduces the leakage current in the semiconductor substrate 100 when the device is in operation. In addition, the hydrofluoric acid solution cleaning can also remove part of the pad oxide layer 110 on the top edge of the trench 160, so that the pad oxide layer sidewall 170 shrinks slightly toward the bottom of the hard mask layer 120, so that The corners of the top edge of the groove 160 are exposed, and when thermal oxidation is performed to form the substrate layer 180 , the corners of the top edge of the groove 160 can have a relatively smooth profile. On the one hand, the smooth profile can reduce stress accumulation, and on the other hand, it can reduce the influence of carrier accumulation on turn-on characteristics when the device is in operation. The process of forming the liner layer 180 by thermal oxidation can be carried out in a dry oxygen environment at a temperature of 900 to 1200 degrees, and the thickness of the formed liner layer 180 is about 30 to 60 nm.

Step 2, as shown in the flowchart of FIG. 7 , a dielectric layer is formed in the trench and on the hard mask layer, and the material of the dielectric layer on the hard mask layer is removed through a planarization process ( S110 ).

As shown in the cross-sectional diagram of FIG. 13 , a dielectric layer is formed in the trench 160 and on the hard mask layer 120 , and the material of the dielectric layer may be silicon oxide or silicon oxynitride. The dielectric layer in this embodiment is silicon oxide material. The method for forming the material of the dielectric layer may be one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, and high-density plasma chemical vapor deposition. The planarization process is chemical mechanical polishing, through which excess dielectric layer material on the surface of the hard mask layer 120 is removed, and a dielectric layer 190 is formed in the trench 160 .

Since the density and hardness of the dielectric layer 190 are smaller than those of the hard mask layer 120, after the planarization process is completed, the surface 190a of the dielectric layer 190 may be slightly lower than that of the hard mask layer 120. surface (not shown), or part of the surface 190a of the dielectric layer 190 may be slightly lower than the surface of the hard mask layer 120, that is, there may be a depression (not shown) in the surface 190a of the dielectric layer 190 Shows).

Step 3, etching the dielectric layer in the trench, reducing the height difference between the surface of the dielectric layer in the trench and the surface of the semiconductor substrate, and forming a protrusion on the edge of the dielectric layer (S120 ). The method of etching the dielectric layer in the trench may be wet etching or dry etching.

In one of the embodiments, the method of etching the dielectric layer in the trench is wet etching, and the etching rate of the etching solution of the wet etching is higher than that of the hard mask. The etch rate of the film layer is high.

In one of the embodiments, the etching solution for wet etching is a hydrofluoric acid solution, and the volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is 1:200 to 1:50, and the The wet etching time is 10 to 50 seconds. As shown in the cross-sectional schematic diagram of Figure 14, the dielectric layer 190 in the trench 160 is wet-etched by hydrofluoric acid solution, so that the surface 190a of the dielectric layer 190 in the trench 160 is lower than the hard mask The surface 120a of the layer 120, but higher than the surface of the semiconductor substrate 100, that is, the surface 190a of the dielectric layer 190 in the trench 160 and the surface of the semiconductor substrate 100 are formed by wet etching. The height difference between them is reduced, and the wet etching also makes the edge of the surface 190a of the dielectric layer 190 in the trench 160 form a protrusion 190b.

Through wet etching, on the one hand, the height difference between the surface 190a of the dielectric layer 190 in the trench 160 and the surface of the semiconductor substrate 100 is reduced, which makes 100 and the polysilicon gate on the dielectric layer 190 have reduced steps due to the height difference, which can be used to form a semiconductor device with a relatively stable threshold voltage and satisfactory performance; in addition, the wet etching process can be used in the The edge of the surface 190a of the dielectric layer 190 forms a protrusion 190b, and the protrusion 190b can slow down the formation of grooves or no grooves at the edge of the shallow trench isolation when the pad oxide layer 110 is removed in the subsequent process, and can reduce the The leakage current of the device formed in the active region caused by the groove is prevented, and the decrease of the threshold voltage of the device in the active region caused by the groove is prevented. In addition, the wet etching can also remove the residual oxide on the surface 120a of the hard mask layer 120. The source of the residual oxide has two aspects. One is to remove the hard mask layer during planarization. On the other hand, when the liner layer 180 is formed by thermal oxidation, the thermal oxidation process may cause the surface 120a of the hard mask layer 120 to be oxidized. The existence of this residue will prevent the subsequent process of removing the hard mask layer 120 by phosphoric acid etching. The wet etching process in this embodiment can remove the oxide residue on the surface of the hard mask layer 120a, ensuring removal The hard mask layer 120 is performed smoothly.

In another embodiment, the method for etching the dielectric layer in the trench is wet etching, and the steps of the wet etching are as follows: etching the dielectric layer with an etching solution of a first concentration ; Then, etching the dielectric layer with an etching solution of a second concentration; the second concentration is less than the first concentration. Divide the wet etching process for etching the dielectric layer in the trench into two steps, and reduce the etching time of each step. The two steps use the same etching solution, and the second step of etching The solution has a small concentration, which is convenient for controlling the etching to remove the thickness of the dielectric layer, so as to prevent the surface of the dielectric layer from being lower than the surface of the semiconductor substrate.

In another embodiment, the method of etching the dielectric layer in the trench is wet etching, the wet etching is divided into multiple times, and the concentration of the etching solution for the wet etching is As the number of times increases and decreases, the wet etching is divided into multiple times, and as the number of times increases, the concentration of the wet etching solution decreases, which can facilitate the control of etching to remove the thickness of the dielectric layer, to avoid The surface of the dielectric layer is lower than the surface of the semiconductor substrate.

In another embodiment, the method of etching the dielectric layer in the trench may also be dry etching. As shown in FIG. 15 , before performing dry etching, a protection layer 200 is formed on the hard mask layer 120 to avoid etching the hard mask layer 120 when dry etching the dielectric layer 190 . After the dry etching is completed, the protection layer needs to be removed.

In one of the embodiments, the protective layer can be photoresist, and the photoresist can be formed by spin coating, and the photoresist material above the dielectric layer 190 is removed by exposure and development, so that the dielectric The surface 190a of the layer 190 is exposed, and the same mask used for forming the opening 140 can be used in the exposure process. The dry etching adopts plasma etching, and the plasma etching can reduce the height difference between the surface 190a of the dielectric layer 190 and the surface of the semiconductor substrate 100, which makes it possible to straddle the semiconductor substrate 100 in subsequent processes. The steps formed by the polysilicon gate on the substrate 100 and the dielectric layer 190 are reduced due to the height difference, which can be used to form a semiconductor device with a relatively stable threshold voltage and satisfactory performance; in addition, it is formed during the dry etching process. The polymer is gathered on the edge of the surface 190a of the dielectric layer 190, which prevents the further etching of the material of the dielectric layer 190 by the plasma, thereby forming a protrusion 190b, which can be removed in a subsequent process. The pad oxide layer 110 slows down the formation of grooves or no grooves at the edge of the shallow trench isolation, so that the leakage current of the device formed in the active region caused by the grooves can be reduced, and the leakage current caused by the grooves can be prevented. cause a drop in the threshold voltage of the active region of the device.

As shown in FIGS. 16 and 17 , after the step of etching the dielectric layer 190 in the trench 160 is completed, the hard mask layer 120 and the pad oxide layer 110 are removed.

The method for removing the hard mask layer 120 is wet etching with phosphoric acid solution; the method for removing the pad oxide layer 110 is wet etching with hydrofluoric acid solution. When using hydrofluoric acid solution to remove the pad oxide layer 110, the hydrofluoric acid solution also corrodes the dielectric layer 190 at the same time, due to the presence of the raised 190b on the edge of the surface 190a of the dielectric layer 190, it can alleviate The excessive etching of the edge of the surface 190a of the dielectric layer 190 by the hydrofluoric acid prevents grooves or shallow grooves from being formed on the edge of the surface of the dielectric layer 190, thereby reducing the The leakage current of the device formed in the active region is caused, and the decrease of the threshold voltage of the device in the active region caused by the groove is prevented.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the claims of the present invention.

Claims (14)

1, a kind of shallow trench isolation from manufacture method, it is characterized in that, comprising:

Semiconductor substrate is provided, on described Semiconductor substrate, has the pad oxide and the hard mask layer that form successively, in described Semiconductor substrate, be formed with groove, in described pad oxide and described hard mask layer, have opening with the corresponding position of groove;

In described groove, in the described opening and form dielectric layer on the described hard mask layer, and remove dielectric layer material on the described hard mask layer by flatening process;

Dielectric layer in described groove of etching and the described opening makes the dielectric layer surface in described groove and the described opening reduce with difference in height between the described semiconductor substrate surface, and makes described dielectric layer edge formation projection.

2, shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that: the lithographic method in the dielectric layer step in described groove of etching and the described opening is wet etching or dry etching.

3, shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that: the lithographic method in the dielectric layer step in described groove of etching and the described opening is a wet etching, and the etch rate that the etching solution of described wet etching is compared described hard mask layer to the etch rate of described dielectric layer is big.

4, shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that: the method for the dielectric layer in described groove of etching and the described opening is a wet etching, and the step of described wet etching is as follows: the etching solution with first concentration carries out etching to described dielectric layer; Then, the etching solution with second concentration carries out etching to described dielectric layer.

5, shallow trench isolation as claimed in claim 4 from manufacture method, it is characterized in that: described second concentration is less than first concentration.

6, shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that: the method for the dielectric layer in described groove of etching and the described opening is a wet etching, described wet etching is divided into repeatedly and carries out, and the etching solution concentration of described wet etching increases along with number of times and reduces.

7, shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that: the lithographic method in the dielectric layer step in described groove of etching and the described opening is a wet etching, the etching solution of described wet etching is a hydrofluoric acid solution.

8, shallow trench isolation as claimed in claim 7 from manufacture method, it is characterized in that: the volumetric ratio of hydrofluoric acid and water is 1: 200 to 1: 50 in the described hydrofluoric acid solution.

9, shallow trench isolation as claimed in claim 7 from manufacture method, it is characterized in that: the time of described wet etching is 10 to 50 seconds.

10, shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that: the method for the dielectric layer in described groove of etching and the described opening is a dry etching; Before described dry etching, on described hard mask layer, form protective layer; After finishing described dry etching, remove described protective layer.

11, shallow trench isolation as claimed in claim 10 from manufacture method, it is characterized in that: described protective layer is a photoresist.

12, shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that: described dielectric layer is a kind of in silica, the silicon oxynitride or combination.

13, shallow trench isolation as claimed in claim 1 from manufacture method, it is characterized in that this method further comprises: after finishing the dielectric layer step in described groove of etching and the described opening, remove described hard mask layer and pad oxide.

14, shallow trench isolation as claimed in claim 13 from manufacture method, it is characterized in that: the method for removing described hard mask layer is the wet etching of phosphoric acid solution; The method of removing described pad oxide is the wet etching of hydrofluoric acid solution.

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