CN103594413A - A method for manufacturing a shallow trench isolating structure - Google Patents
A method for manufacturing a shallow trench isolating structure Download PDFInfo
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- CN103594413A CN103594413A CN201210288719.0A CN201210288719A CN103594413A CN 103594413 A CN103594413 A CN 103594413A CN 201210288719 A CN201210288719 A CN 201210288719A CN 103594413 A CN103594413 A CN 103594413A
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000002210 silicon-based material Substances 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000137 annealing Methods 0.000 claims abstract description 23
- 239000001301 oxygen Substances 0.000 claims abstract description 21
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 21
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000011049 filling Methods 0.000 claims abstract description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 78
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 239000000377 silicon dioxide Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a method for manufacturing a shallow trench isolating structure. The method comprises: a) providing a semiconductor substrate on which trenches used for filling STI oxide are formed; b) forming silicon material layers on the bottom and the sidewall of the trenches; c) doping oxygen into the silicon material layers; and d) executing an annealing process in the presence of oxygen in order to convert the silicon material layers into STI oxide filled in the trenches. The method is capable of effectively preventing defects such as forming holes in the shallow trench isolating structure or the like so as to further be used for trenches with a filling depth-to-width ratio more than 12 to 1.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of shallow trench isolation from the manufacture method of (STI) structure.
Background technology
Fleet plough groove isolation structure is one of isolation structure the most frequently used in semiconductor technology.Figure 1A-1D shows the cutaway view that adopts traditional handicraft to make the device that in fleet plough groove isolation structure process, each step obtains.First, as shown in Figure 1A, provide Semiconductor substrate 100, in Semiconductor substrate 100, form successively oxide skin(coating) 101 and mask layer 102.On mask layer 102, form the figuratum photoresist layer 103 of tool, the pattern comprising in photoresist layer 103 is used to form fleet plough groove isolation structure.As shown in Figure 1B, the photoresist layer 103 of take carries out etching to mask layer 102, oxide skin(coating) 101 and Semiconductor substrate 100 successively as mask, to form groove 104 in Semiconductor substrate 100.As shown in Figure 1 C, on groove 104 surfaces, form thinner pad oxide layer 105.As shown in Fig. 1 D, in groove 104, fill up sti oxide.Then remove Semiconductor substrate 100 surface material layers in addition and can form fleet plough groove isolation structure.
But along with the continuous shortening of device critical size, the depth-to-width ratio (AR) of the groove that etching forms constantly increases, so just bring very large difficulty to the filling of sti oxide, can in the sti oxide in being filled in groove, form hole.In order to overcome this problem, adopt at present high density plasma oxide and high-aspect-ratio oxide to fill.But, because the depth-to-width ratio of current groove has been increased to 8:1, even if high-aspect-ratio oxide is also difficult to avoid forming hole in the fleet plough groove isolation structure forming subsequently.
Therefore, be badly in need of at present a kind of manufacture method of fleet plough groove isolation structure, to solve the above-mentioned problems in the prior art.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of manufacture method of fleet plough groove isolation structure, comprising: Semiconductor substrate a) is provided, in described Semiconductor substrate, is formed for filling the groove of sti oxide; B) on the bottom surface of described groove and sidewall, form silicon material layer; C) doped with oxygen in described silicon material layer; And d) under oxygen atmosphere, carry out annealing process, so that silicon material layer changes described sti oxide into, be filled in described groove.
Preferably, described a) step comprises: in described Semiconductor substrate, form successively the figuratum photoresist layer of oxide skin(coating), nitride layer and tool; Successively described nitride layer, described oxide skin(coating) and described Semiconductor substrate are carried out to etching, to form described groove.
Preferably, the material of described silicon material layer is polysilicon.
The 0.1-0.5 of the width that preferably, the thickness of described silicon material layer is described groove doubly.
Preferably, described c) step is to realize by carrying out the ion implantation technology of oxygen.
Preferably, the Implantation Energy that described ion implantation technology adopts is 0.5keV to 40keV.
Preferably, the implantation dosage that described ion implantation technology adopts is 1 * 10
5cm
-2to 5 * 10
18cm
-2.
Preferably, in described annealing process, annealing temperature is 800 ℃ to 1100 ℃.
Preferably, in described annealing process, annealing time is 10 seconds to 2 hours.
Preferably, the gas passing in described annealing process comprises oxygen/water steam and nitrogen.
Preferably, the flow of described oxygen/water steam is less than 50sccm, and the flow of described nitrogen is 10sccm-100sccm.
Preferably, at described b) before step, on the bottom surface of described groove and sidewall, form pad oxide layer.
Preferably, the depth-to-width ratio of described groove is greater than 8:1.
Method of the present invention is owing to only filling silicon material layer in a part for groove, and by this silicon material layer being oxidized to form the sti oxide layer that fills up groove.On the one hand, in current technology, the filling capacity of silicon materials is strong higher than the filling capacity of silica; On the other hand, even if formed a small amount of gap in silicon material layer, in follow-up doping and oxidizing process, silicon material layer oxidation forms silica can cause that volume increases, thereby fill up the gap of formation, so the method can be applied to fill depth-to-width ratio and reaches even 12:1 of 8:1() above groove.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1D shows the cutaway view that adopts traditional handicraft to make the device that in fleet plough groove isolation structure process, each step obtains;
Fig. 2 makes the process chart of fleet plough groove isolation structure according to one embodiment of the present invention;
Fig. 3 A-3G is for making the cutaway view of the device that in fleet plough groove isolation structure process, each step obtains according to one embodiment of the present invention.
Embodiment
Next, in connection with accompanying drawing, the present invention is more intactly described, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to know that size and the relative size in ，Ceng He district may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.
Fig. 2 shows according to one embodiment of the present invention and makes semiconductor device technology flow chart, and Fig. 3 A-3G shows the cutaway view of making the device that in semiconductor device technology flow process, each step obtains according to one embodiment of the present invention.Below in conjunction with Fig. 2 and Fig. 3 A-3G, describe manufacture method of the present invention in detail.
Execution step 201, provides Semiconductor substrate, is formed for filling the groove of sti oxide in this Semiconductor substrate.
As shown in Figure 3A, provide Semiconductor substrate 300.Semiconductor substrate 300 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.Although several examples of having described the material that can form Semiconductor substrate 100 at this, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.In addition, Semiconductor substrate 300 can be divided active area, and/or can also be formed with dopant well (not shown) etc. in Semiconductor substrate 300.
The method that is formed for filling the groove of sti oxide in Semiconductor substrate 300 has multiple, and a kind of optimal way is only provided herein.
Continuation, with reference to Fig. 3 A, forms oxide skin(coating) 301 in Semiconductor substrate 300.Oxide skin(coating) 301 can make to utilize thermal oxide growth method to form, and oxide skin(coating) 301 can be that 20 dusts are to the silicon oxide layer of 50 dusts for thickness.This layer of compact structure therefore can be used as protective layer in subsequent etching technique.At oxide skin(coating) 301, forming mask layer 302, the material of mask layer 302 can nitride or other there is the composite bed of laminated construction.The thickness of mask layer 302 can be 800 dust to 2500 dusts.On mask layer 302, can form the figuratum photoresist layer 303 of tool, the figuratum photoresist layer 303 of this tool can be the photoresist forming by spin coating proceeding, then through techniques such as exposure, development, cleanings, forms.The pattern that photoresist layer 303 has is used for being formed for forming the raceway groove of fleet plough groove isolation structure.In addition,, in order to strengthen the absorptivity of photoresist layer, before spin coating photoresist, form again bottom anti-reflection layer etc.
As shown in Figure 3 B, the figuratum photoresist layer 303 of the tool of take carries out etching to mask layer 302 as mask, with by design transfer to mask layer 302.This etch step can be dry etching, and the etching gas adopting can comprise CF
4and CH
2f
2deng fluoro-gas and helium (He), wherein fluoro-gas is mainly used as the gas of reactive ion etching, and helium mainly plays the effect of dilution etching gas.Then, the mask layer 302 of take carries out etching to oxide skin(coating) 301 and Semiconductor substrate 300 as mask, and the etching technics adopting can also be dry etching.Etching gas can comprise CF
4, C
2f
6and CHF
3deng fluoro-gas and argon gas, wherein fluoro-gas is mainly used as the gas of reactive ion etching, and helium mainly plays the effect of dilution etching gas.After above-mentioned etching technics, obtain the groove 304 shown in Fig. 3 B.Because above-mentioned etching technics is by known in the art, therefore no longer describe in detail herein.
Execution step 202 forms silicon material layer on the bottom surface of groove and sidewall.
Preferably, before forming silicon material layer, can on the bottom surface of groove 304 and sidewall, first form pad oxide layer 305, as shown in Figure 3 C.This pad oxide layer 305 can be to adopt thermal oxidation method or sedimentation (such as chemical vapour deposition technique, physical vaporous deposition etc.) to form.The thickness of pad oxide layer 305 can be 4 ~ 10nm.Pad oxide layer 305 can be improved the interfacial characteristics of Semiconductor substrate 300 and the sti oxide layer of filling subsequently.
As shown in Figure 3 D, on the bottom surface of groove 304 and sidewall, form silicon material layer 306.The material of silicon material layer 306 can be polysilicon, monocrystalline silicon or amorphous silicon, can also be silica-rich material etc.Preferably, the material of silicon material layer is polysilicon.The thickness of silicon material layer 306 can for the 0.1-0.5 of the width (as the w being marked in Fig. 3 B) of raceway groove 304 doubly.The width of raceway groove 304 also can be described as the critical size of raceway groove 304.While making silicon change silica into by oxidizing process, the silica of every generation 1nm need to consume the silicon of about 0.44nm, so those skilled in the art can select according to the content of silicon in silicon material layer 306 in above-mentioned scope.
Execution step 203, doped with oxygen in silicon material layer.
Doped with oxygen in silicon material layer, so that the silicon in silicon material layer can fully change silica in subsequent technique.In silicon material layer, the method for doped with oxygen has a variety ofly, is wherein preferably ion implantation technology.By contrast, the step of ion implantation technology is simple, and dopant dose and doping depth are easier to control.As shown in Fig. 3 E, adopt ion implantation technology doped with oxygen in silicon material layer 306, for oxygen is more rested in silicon material layer 306, the Implantation Energy that ion implantation technology adopts can be 0.5keV to 40keV.In practical operation, according to the thickness of formed silicon material layer 306, can within the scope of this, select suitable Implantation Energy.In order to make to have suitable concentration in silicon material layer 306, the implantation dosage that ion implantation technology adopts is 1 * 10
5cm
-2to 5 * 10
18cm
-2.
Execution step 204, carries out annealing process, so that silicon material layer changes sti oxide into, is filled in groove.
Carry out after annealing process, so that the silicon material layer 306 after doping changes sti oxide layer into, be filled in raceway groove.Preferably, in annealing process, annealing temperature can be 800 ℃ to 1100 ℃, and in annealing process, annealing time is 10 seconds to 2 hours.According to the actual (real) thickness of silicon material layer 306, can in above-mentioned scope, select suitable annealing parameter.In order to make silicon material layer 306 be oxidized to fully sti oxide layer 307, preferably, annealing process carries out under oxygen atmosphere.In order to build this oxygen annealing atmosphere, the gas passing in annealing process can comprise oxygen/water steam and nitrogen, and the gas passing into can comprise oxidation and nitrogen or steam and nitrogen.Further preferably, the flow of oxygen/water steam can be less than 50sccm, and the flow of nitrogen can be 10sccm-100sccm.
Finally, the method can also comprise flatening process, to remove more than 301 mask layer 302, photoresist layer 303 and the sti oxide layer 307(of oxide skin(coating) as shown in Fig. 3 G).
Method of the present invention is owing to only filling silicon material layer in a part for groove, and by this silicon material layer being oxidized to form the sti oxide layer that fills up groove.On the one hand, in current technology, the filling capacity of silicon materials is strong higher than the filling capacity of silica; On the other hand, even if formed a small amount of gap in silicon material layer, in follow-up doping and oxidizing process, silicon material layer oxidation forms silica can cause that volume increases, thereby fill up the gap of formation, so the method can be applied to fill depth-to-width ratio and reaches even 12:1 of 8:1() above groove.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for fleet plough groove isolation structure, comprising:
A) provide Semiconductor substrate, in described Semiconductor substrate, be formed for filling the groove of sti oxide;
B) on the bottom surface of described groove and sidewall, form silicon material layer;
C) doped with oxygen in described silicon material layer; And
D) under oxygen atmosphere, carry out annealing process, so that silicon material layer changes described sti oxide into, be filled in described groove.
2. the method for claim 1, is characterized in that, described a) step comprises:
In described Semiconductor substrate, form successively the figuratum photoresist layer of oxide skin(coating), nitride layer and tool;
Successively described nitride layer, described oxide skin(coating) and described Semiconductor substrate are carried out to etching, to form described groove.
3. the method for claim 1, is characterized in that, the material of described silicon material layer is polysilicon.
4. the method for claim 1, is characterized in that, the 0.1-0.5 of the width that the thickness of described silicon material layer is described groove doubly.
5. the method for claim 1, is characterized in that, described c) step is to realize by carrying out the ion implantation technology of oxygen.
6. method as claimed in claim 5, is characterized in that, the Implantation Energy that described ion implantation technology adopts is 0.5keV to 40keV.
7. method as claimed in claim 5, is characterized in that, the implantation dosage that described ion implantation technology adopts is 1 * 10
5cm
-2to 5 * 10
18cm
-2.
8. the method for claim 1, is characterized in that, in described annealing process, annealing temperature is 800 ℃ to 1100 ℃.
9. the method for claim 1, is characterized in that, in described annealing process, annealing time is 10 seconds to 2 hours.
10. the method for claim 1, is characterized in that, the gas passing in described annealing process comprises oxygen/water steam and nitrogen.
11. methods as claimed in claim 10, is characterized in that, the flow of described oxygen/water steam is less than 50sccm, and the flow of described nitrogen is 10sccm-100sccm.
12. the method for claim 1, is characterized in that, at described b) before step, on the bottom surface of described groove and sidewall, form pad oxide layer.
13. the method for claim 1, is characterized in that, the depth-to-width ratio of described groove is greater than 8:1.
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| CN201210288719.0A CN103594413A (en) | 2012-08-14 | 2012-08-14 | A method for manufacturing a shallow trench isolating structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106935542A (en) * | 2015-12-30 | 2017-07-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN109037143A (en) * | 2017-06-08 | 2018-12-18 | 格芯公司 | Semiconductor device including trench isolations |
| CN110223952A (en) * | 2019-06-14 | 2019-09-10 | 武汉新芯集成电路制造有限公司 | The forming method of fleet plough groove isolation structure and the forming method of semiconductor devices |
| CN112768137A (en) * | 2020-12-18 | 2021-05-07 | 安捷利电子科技（苏州）有限公司 | Preparation method of electrode with narrow channel |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106935542A (en) * | 2015-12-30 | 2017-07-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| US10672866B2 (en) | 2015-12-30 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seamless gap fill |
| CN113437023A (en) * | 2015-12-30 | 2021-09-24 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| US11239310B2 (en) | 2015-12-30 | 2022-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seamless gap fill |
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| CN110223952A (en) * | 2019-06-14 | 2019-09-10 | 武汉新芯集成电路制造有限公司 | The forming method of fleet plough groove isolation structure and the forming method of semiconductor devices |
| CN112768137A (en) * | 2020-12-18 | 2021-05-07 | 安捷利电子科技（苏州）有限公司 | Preparation method of electrode with narrow channel |
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Application publication date: 20140219 |