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CN100539054C - 芯片封装结构及其制作方法 - Google Patents

芯片封装结构及其制作方法 Download PDF

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CN100539054C
CN100539054C CNB2007100876716A CN200710087671A CN100539054C CN 100539054 C CN100539054 C CN 100539054C CN B2007100876716 A CNB2007100876716 A CN B2007100876716A CN 200710087671 A CN200710087671 A CN 200710087671A CN 100539054 C CN100539054 C CN 100539054C
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chip
lug boss
those
colloid
bonding wires
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CN101266932A (zh
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乔永超
邱介宏
吴燕毅
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
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BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
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Priority to US11/737,766 priority patent/US20080224277A1/en
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Priority to US12/506,245 priority patent/US8088650B2/en
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Abstract

本发明公开了一种芯片封装结构的制作方法，首先，提供一具有第一凸起部、第二凸起部及多个第三凸起部的金属薄板。之后，将芯片配置于金属薄板上，并形成用以电性连接于芯片与第二凸起部以及第二凸起部与第三凸起部之间的多条焊线。接着，于金属薄板的上下表面形成上胶体及下胶体，此下胶体中具有多个凹部，以暴露出第一凸起部、第二凸起部与三凸起部之间彼此相连的部分。最后，以下胶体为蚀刻掩膜蚀刻此金属薄板，使第一凸起部、第二凸起部以及第三凸起部分别形成导线架的芯片座、汇流架以及引脚。

Description

芯片封装结构及其制作方法
技术领域
本发明是有关于一种芯片封装结构，且特别是有关于一种具有导线架的芯片封装结构。
背景技术
在半导体产业中，集成电路(integrated circuits，IC)的生产主要可分为三个阶段：集成电路的设计(IC design)、集成电路的制作(IC process)及集成电路的封装(IC package)。
在集成电路的制作中，芯片(chip)是经由晶圆(wafer)制作、形成集成电路以及切割晶圆(wafer sawing)等步骤而完成。晶圆具有一有源面(activesurface)，其泛指晶圆具有主动元件(active device)的表面。当晶圆内部的集成电路完成之后，晶圆的有源面还配置有多个焊垫(bonding pad)，以使最终由晶圆切割所形成的芯片可经由这些焊垫而向外电性连接于一承载器(carrier)。承载器例如为一导线架(leadframe)或一封装基板(package substrate)。芯片可以打线接合(wire bonding)或覆晶接合(flip chip bonding)的方式连接至承载器上，使得芯片的这些焊垫可电性连接于承载器的接点，以构成一芯片封装结构。
图1是现有的芯片封装体的上视示意图。图2是图1芯片封装体的剖面示意图。请同时参考图1与图2，为了说明上的方便，图1与图2是透视封装胶体140的示意图，并且仅以虚线描绘出封装胶体140的轮廓。芯片封装体100包括一导线架110、一芯片120、多条第一焊线(bonding wire)130、多条第二焊线132、多条第三焊线134与一封装胶体140。导线架110包括一芯片座(die pad)112、多条内引脚114以及多条汇流架116。内引脚114配置于芯片座112的外围。汇流架116介于芯片座112与内引脚114之间。
芯片120具有彼此相对的一主动表面122以及一背面124。芯片120配置于芯片座112上，并且背面124朝向芯片座112。芯片120具有多个接地接点126与多个非接地接点128，其中这些非接地接点128包括多个电源接点以及多个信号接点。接地接点126与非接地接点128均位于主动表面122上。
第一焊线130将接地接点126电性连接于汇流架116。第二焊线132将汇流架116电性连接于这些内引脚114中的接地引脚。第三焊线134则分别将其余的内引脚114电性连接于对应的第二接点128。封装胶体140将芯片座112、内引脚114、汇流架116、芯片120、第一焊线130、第二焊线132以及第三焊线134包覆于其内。
值得注意的是，由于现有的芯片封装结构100于封装过程乃是使用已经图案化的导线架，此导线架110本身即具有一芯片座(die pad)112、多条内引脚114以及多条汇流架116。然而，在导线架图案化制作过程中必须使用到费用高昂的曝光显影光掩膜，徒然增加额外的导线架成本。
发明内容
本发明提供一种芯片封装结构及其制作方法，以解决现有的芯片封装制程中，直接使用图案化导线架所构成的封装成本较高的问题。因此，本发明使用一金属薄板，于封装过程当中通过蚀刻制程技术，以于金属薄板上形成导线架的芯片座、汇流架以及引脚，如此，将有助于节省芯片封装结构的制作成本。
另外，本发明的蚀刻制程乃是通过具有凹部的下胶体作为蚀刻掩膜，以取代现有曝光显影所需的光掩膜，如此，即可节省下大量的光掩膜费用，进而降低封装成本。
本发明提出一种芯片封装结构的制作方法，其包括下列步骤。首先，提供一金属薄板，此金属薄板具有一上表面以及一下表面。其中，金属薄膜的上表面具有一第一凸起部、一第二凸起部以及多个第三凸起部，此第二凸起部是位于第一凸起部与这些第三凸起部之间，且第一凸起部、第二凸起部以及这些第三凸起部是彼此相连。之后，提供一芯片，此芯片具有一有源面、一背面与多个芯片焊垫。其中，这些芯片焊垫是配置于芯片的有源面上。接下来，将芯片的背面固着于第一凸起部上。之后，形成多条第一焊线以及多条第二焊线，其中这些第一焊线分别连接这些芯片焊垫与第二凸起部，而这些第二焊线分别连接这些第二凸起部与第三凸起部。接着，形成一上胶体以及一下胶体，其中此上胶体包覆住金属薄板的上表面、芯片以及这些第一焊线与第二焊线，而下胶体包覆住金属薄板的下表面，且暴露出第一凸起部、第二凸起部与这些第三凸起部彼此之间相连的部分。最后，以下胶体为一蚀刻掩膜蚀刻此金属薄板，直到第一凸起部、第二凸起部与这些第三凸起部彼此电性绝缘，如此，第一凸起部即形成一芯片座、第二凸起部即形成一汇流架，且这些第三凸起部即形成多个引脚。
在本发明一实施例中，金属薄板为一铜箔。
在本发明一实施例中，这些第一焊线与第二焊线是由打线接合技术形成。
在本发明一实施例中，下胶体包括多个凹部，以暴露出第一凸起部、第二凸起部与这些第三凸起部彼此之间相连的部分。
在本发明一实施例中，此芯片封装结构的制造方法还包括形成一胶体于下胶体的这些凹部内。
此外，本发明另提出一种芯片封装结构，其主要包括一芯片、一导线架、多条第一焊线、多条第二焊线、一上胶体、一第一下胶体以及一第二下胶体。此芯片具有一有源面、一背面与多个芯片焊垫，其中这些芯片焊垫配置于有源面上。导线架具有一上表面以及与其相对应的一下表面，其包括一芯片座、多个引脚以及至少一汇流架，此芯片的背面是固着于芯片座上。这些引脚是环绕此芯片座。此汇流架是位于芯片座与这些引脚之间。多条第一焊线分别连接这些芯片焊垫与此汇流架。多条第二焊线分别连接此汇流架与这些引脚。此上胶体包覆住导线架的上表面、芯片以及第一焊线与第二焊线。第一下胶体包覆住导线架的下表面，其具有多个凹部，以暴露出对应于芯片座与汇流架之间的上胶体、对应于汇流架及这些引脚之间的上胶体，以及对应于相邻的二引脚之间的上胶体。
在本发明一实施例中，此芯片封装结构还包括一第二下胶体，形成于第一下胶体的凹部内。
本发明所揭示的芯片封装结构的制作方法，是先将芯片配置于金属薄板上，再于芯片及金属薄板上形成所需的焊线以及封装胶体。最后，蚀刻掉部分的金属薄板，即可形成导线架的芯片座、汇流架以及内引脚。
为让本发明的上述特征和优点能更明显易懂，下文特举较佳实施例，并配合附图作详细说明如下。
附图说明
图1绘示为现有的芯片封装体的上视示意图。
图2绘示为图1芯片封装体的剖面示意图。
图3A～3F绘示为根据本发明一实施例的一种芯片封装结构的制作流程剖面示意图。
具体实施方式
图3A～3F绘示为根据本发明一实施例的一种芯片封装结构的制作流程剖面示意图。首先，请参考图3A，提供一金属薄板210，其具有一上表面210a以及一下表面210b。此金属薄膜210的上表面210a形成有多个沟槽，以将其区分为一第一凸起部212、一第二凸起部214以及多个第三凸起部216，且第一凸起部212、第二凸起部214以及这些第三凸起部216是彼此相连。其中，第一凸起部212约位于金属薄板210的中央部分，而第二凸起部214是环绕于第一凸起部212的外侧，且这些第三凸起部216是环绕于第二凸起部214外侧。此外，第一凸起部212、第二凸起部214以及多个第三凸起部216分别具有芯片座、汇流架以及引脚的外形，使其经过后续加工后可分别作为导线架中的芯片座、汇流架以及引脚。在此实施例中，金属薄板210可由铜箔所组成。
之后，请参考图3B，提供一芯片220，此芯片220具有一有源面220a、一背面220b以及多个芯片焊垫222，其中，有源面220a是相对于背面220b，且芯片焊垫222是配置于芯片220的有源面220a上。此芯片220的背面220b是固着于金属薄板210的第一凸起部212上。举例而言，芯片220可通过一黏着胶材而固定于第一凸起部212上。
接下来，请参考图3C，形成多条第一焊线230以及多条第二焊线240，其中这些第一焊线230分别连接于芯片焊垫222与第二凸起部214之间，而这些第二焊线240分别连接于第二凸起部214与第三凸起部216之间。而这些第一焊线230与第二焊线240是由打线接合技术所形成。
之后，请参考图3D，于金属薄板210的上表面210a及下表面210b上形成一上胶体250以及一下胶体260。其中，上胶体250包覆住金属薄板210的部分上表面210a、芯片220、第一焊线230以及第二焊线240；而下胶体260包覆住金属薄板210的下表面210b，且其具有多个凹部262，以暴露出金属薄板210上第一凸起部212、第二凸起部214以及第三凸起部216彼此之间相连的部分。此下胶体260的凹部262是通过形成下胶体260时所需的模具280上相对应的凸部282而形成。
最后，请参考图3E，以下胶体260为一蚀刻掩膜蚀刻此金属薄板210的下表面210b，直到第一凸起部212、第二凸起部214与这些第三凸起部216彼此电性绝缘，如此，此第一凸起部212即可作为导线架210’中的芯片座212’、此第二凸起部214即可作为一汇流架214’，而这些第三凸起部216即可作为引脚216’。至此，即大致完成芯片封装结构200的制作流程。
为防止图3E中的芯片座212’、汇流架214’以及引脚216’因暴露于空气中而易发生氧化的问题，请参考图3F所示，可于完成图3E中所示的步骤后，形成一胶体270于下胶体260的凹部262中，以防止图3E的芯片座212’、汇流架214’以及引脚216’因暴露于空气中而发生氧化的问题。
综上所述，本发明提出一种全新的芯片封装结构的制作方法，首先，提供一具有第一凸起部、第二凸起部及多个第三凸起部的金属薄板。之后，将芯片配置于金属薄板上，并形成用以电性连接芯片与第二凸起部以及第二凸起部与第三凸起部之间的多条焊线。接着，于金属薄板的上下表面上形成上胶体及下胶体，此下胶体中具有多个凹部，以暴露出第一凸起部、第二凸起部与三凸起部之间彼此相连的部分。最后，以下胶体为蚀刻掩膜蚀刻此金属薄板，使第一凸起部、第二凸起部以及第三凸起部分别形成为导线架的芯片座、汇流架以及引脚。
本发明所揭示的芯片封装结构的制作方法有别于现有的以导线架作为承载器的芯片封装制程之处在于：现有的芯片封装制程是直接以现成的图案化导线架进行芯片的封装，而本发明的芯片封装结构是先将芯片配置于金属薄板上，再形成所需的焊线以及封装胶体，最后，再蚀刻掉部分的金属薄板，以形成导线架的芯片座、汇流架以及内引脚。由于本发明所提供的芯片封装结构的制作方法是使用一金属薄板，于封装过程当中通过蚀刻制程技术，以于金属薄板上形成导线架的芯片座、汇流架以及引脚，如此，将可节省其制作成本，以解决现有技术中因直接使用图案化导线架而造成封装成本较高的问题。
另外，本发明蚀刻制程乃是通过具有凹部的下胶体当作蚀刻掩膜，以通过具有凹部的下胶体取代现有曝光显影所需的光掩膜，进而节省大量的光掩膜费用，以达到降低封装成本的目的。
虽然本发明已以较佳实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许更动与润饰，因此本发明的保护范围当以权利要求所界定的为准。

Claims (7)

1.一种芯片封装结构的制作方法，包括：
提供一金属薄板，具有一上表面以及一下表面，其中该金属薄膜的该上表面具有一第一凸起部、一第二凸起部以及多个第三凸起部，该第二凸起部是位于该第一凸起部与该些第三凸起部之间，且该第一凸起部、该第二凸起部以及该些第三凸起部是彼此相连；
提供一芯片，该芯片具有一有源面、一背面与多个芯片焊垫，其中该些芯片焊垫配置于该有源面上；
将该芯片的该背面固着于该第一凸起部上；
形成多条第一焊线以及多条第二焊线，其中该些第一焊线是分别连接该些芯片焊垫与该些第二凸起部，而该些第二焊线是分别连接该第二凸起部与该些第三凸起部；
形成一上胶体以及一下胶体，其中该上胶体是包覆住该金属薄板的该上表面、该芯片以及该些第一焊线与该些第二焊线，该下胶体是包覆住该金属薄板的该下表面，且暴露出该第一凸起部、该第二凸起部与该些第三凸起部彼此之间相连的部分；以及
以该下胶体为一蚀刻掩膜蚀刻该金属薄板，直到该第一凸起部、该第二凸起部与该些第三凸起部彼此电性绝缘，如此，该第一凸起部即形成一芯片座、该第二凸起部即形成一汇流架，且该些第三凸起部即形成多个引脚。
2.如权利要求1所述的芯片封装结构的制作方法，其特征在于，该金属薄板为一铜箔。
3.如权利要求1所述的芯片封装结构的制作方法，其特征在于，该些第一焊线与该些第二焊线是由打线接合技术形成。
4.如权利要求1所述的芯片封装结构的制作方法，其特征在于，该下胶体包括多个凹部，以暴露出该第一凸起部、该第二凸起部与该些第三凸起部彼此之间相连的部分。
5.如权利要求4所述的芯片封装结构的制造方法，其特征在于，还包括形成一胶体于该下胶体的该些凹部内。
6.一种芯片封装结构，包括：
一芯片，具有一有源面、一背面与多个芯片焊垫，其中该些芯片焊垫配置于该有源面上；
一导线架，具有一上表面以及与其相对应的一下表面，该导线架包括：
一芯片座，该芯片的该背面是固着于该芯片座上；
多个引脚，环绕该芯片座；以及
至少一汇流架，位于该芯片座与该些引脚之间；
多条第一焊线，分别连接该些芯片焊垫与该汇流架；
多条第二焊线，分别连接该汇流架与该些引脚；
一上胶体，包覆住该导线架的该上表面、该芯片以及该些第一焊线与该些第二焊线；以及
一第一下胶体，包覆住该导线架的该下表面，其中该第一下胶体具有多个凹部，以暴露出对应于该芯片座与该汇流架之间的该上胶体、对应于该汇流架及该些引脚之间的该上胶体，以及对应于相邻的二该引脚之间的该上胶体。
7.如权利要求6所述的芯片封装结构，其特征在于，还包括一第二下胶体，形成于该第一下胶体的该些凹部内。
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