CN-9509009 22166twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構，且特別是有關於 一種具有導線架的晶片封裝結構。 【先前技術】 在半導體產業中，積體電路（integrated circuits，1C) 的生產主要可分為三個階段：積體電路的設計（IC design)、積體電路的製作（ic process)及積體電路的封 裝（IC package )。 在積體電路的製作中，晶片（chip)是經由晶圓（wafer) 製作、形成積體電路以及切割晶圓（wafer sawing)等步驟 而元成。晶圓具有一主動面（active surface )，其泛指晶 圓之具有主動元件（active device)的表面。當晶圓内部之 積體電路完成之後，晶圓之主動面更配置有多個焊墊 (bonding pad)，以使最終由晶圓切割所形成的晶片可經 =這些焊墊而向外電性連接於一承載器（earrier)。承載 窃例如為-導線架（leadframe)或一封裝基板（喊哪 =b，rate)。晶片可以打線接合（^心副㈣）或覆晶接 合（mpchipb()nding)的方式連接至承載器上使得 ίΪΪ焊财紐連接於之接點，崎成一晶片封 的上視示意圖。圖2是圖1 同時參考圖1與圖2，為了 圖1是習知之晶片封裝體 晶片封裝體的剖面示意圖。請 1334182 CN-9509009 22166twf.doc/n 說明上的万便’ Hi興圖2是透視封裝膠體14 並且僅以虛線描繪出封裝膠體刚的輪 的不意圖’ 包括一導線架110、一晶片】 邱曰曰片封裴體100 wire) 130、多條第二焊線 132 線（bonding 裝膠體140。導線架110包括一曰’、一坪線134與一封 條内引腳114以及多條匿济起了座（diepad) 112、多BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a chip package structure, and more particularly to a chip package structure having a lead frame. [Prior Art] In the semiconductor industry, the production of integrated circuits (1C) can be mainly divided into three stages: IC design, integrated circuit (ic process), and integrated circuits. Circuit package (IC package). In the fabrication of an integrated circuit, a chip is formed by a process of fabricating, forming an integrated circuit, and wafer sawing. The wafer has an active surface, which generally refers to the surface of the crystal having an active device. After the integrated circuit inside the wafer is completed, the active surface of the wafer is further provided with a plurality of bonding pads, so that the wafer formed by the wafer cutting can be electrically connected to the outside through the pads. On an armor. The bearer is, for example, a leadframe or a package substrate (where =b, rate). The wafer can be connected to the carrier by wire bonding (^ core (4)) or flip chip bonding (mpchipb () nding) so that the solder joint is connected to the contact, and the top view of the wafer is sealed. FIG. 2 is a cross-sectional view of a conventional chip package chip package in FIG. 1 for reference to FIG. 1 and FIG. Please, 1334182 CN-9509009 22166twf.doc/n Description on the stool 'Hi Xing Figure 2 is the perspective encapsulation colloid 14 and only the dotted line of the encapsulation colloid is not intended to include a lead frame 110, a wafer] Qiu The cymbal sealing body 100 wire) 130, a plurality of second welding wire 132 wires (bonding assembly colloid 140. The lead frame 110 includes a 曰', a flat line 134 and an inner pin 114 and a plurality of occlusions Block (diepad) 112, more
片座112之外圍。匯流架Ή腳114配置於晶 之間。 6介於晶片座⑴與内引腳114 曰曰片2具有彼此;f目對的—絲 124。晶片12〇配置於晶片座112上，並且背面=朝口 片座m^12G具有多個接地接點126 = 接點m，其中這些非接地接點128包括多個電源 及多個訊號接點。接地接點126與非接地接點128位 主動表面122上。 、The periphery of the block 112. The busbar foot 114 is disposed between the crystals. 6 between the wafer holder (1) and the inner lead 114. The cymbal 2 has a wire 124 that is opposite to each other. The wafer 12 is disposed on the wafer holder 112, and the back side facing the chip holder m^12G has a plurality of ground contacts 126 = contacts m, wherein the non-ground contacts 128 include a plurality of power sources and a plurality of signal contacts. Ground contact 126 and non-ground contact 128 are on active surface 122. ,
第一焊線130將接地接點126電性連接於匯流架 116。第二焊線132將匯流架116電性連接於這些内引卿 114中的接地引腳。第三焊線134則分別將其餘的内弓丨卿 114電性連接於對應的第^一接點128。封裝膠體14〇將晶片 座112、内引腳114、匯流架116、晶片12〇、第一焊線13〇、 第二焊線132以及第三焊線134包覆於其内。 值得注意的是，由於習知的晶片封裴結構1〇〇於封事 過程乃是使用已經圖案化的導線架，此導線架110本身^ 具有一晶片座（diepad) 112、多條内引腳114以及多條匯 流架116。然而，在導線架圖案化製作過程中必須使用到 6 I3M182 CN-9509009 22166twf.doc/n 費用”的曝光顯影光罩，徒然增加額外的導線架成本。 【發明内容】 本發明提供一種晶片封裝結構及其製作方法，以解決 封二中’ Μ使用圖案化導線架所構成之 BU的問題。因此，本發明使用—金屬 ===製程技術，以於金屬薄板上形成導 製::r及引腳’如此’將有助於節省晶 你」外’本發明之侧製程乃是藉由具有凹部之下膠體 遮罩旦以取代習知曝光顯影所需之光單，如此， °印省下大量的光罩費用，進而降低封襄成本。 作方述問題’本發明提出一種晶片封装結構之製 -上#面=括下列步驟。首先，提供—金屬薄板，具有 -凸ίΓΓ表面，財金屬薄歡上㈣具有—第 ，起。卩、-紅凸起部以及多個第三凸起部第 第疋=於第-凸起部與第三凸起部之間，且第—凸起 ^凸，三凸起部是彼此相連。接下來，提二— 晶片焊i配置動面、—背面與多個晶片焊塾，其中 一於主動面上。然後，將晶片之背面固著於第 其中= 接Λ，二成接多條第一焊線以及多條第二焊線， ίίΠΐ接第二凸起部與第三凸起部。再來，形t 上膠體，其中上賴是包覆住金㈣板之上 ^ 7 1334182 CN-9509009 22166twf.doc/n ^-谭線與第二焊線。之後，於下表面上形成—餘刻罩 •幕’以暴露出第—凸起部、第二凸起部以及第三凸起部彼 此相連之處。最後，餘刻金屬薄板，直到第一凸起部 二凸起部與第三凸起部彼此電性絕緣，如此，第一 .即形成一晶片座、第二凸起部即形成-匯流架，且第三^ 起部即形成多個引腳。 * 在本發明之:實施例中，上述晶片封裝結構的製作方 • 法’於姓刻金屬薄板之步驟後’更包括形成-下膠體，下 膠體填充於晶片座、匯流架以及引腳之間。 在本發明之-實施财，上述下紐與⑽罩幕為共 平面。 八 在本發明之-實施例巾，上述下㈣更包覆姓刻罩 幕。 在本發明之一實施例中，上述晶片封裝結構的製作方 法，於蝕刻金屬薄板之步驟後，更包括移除蝕刻罩幕，之 後再形成下膠體。 瞻在本發明之-實施例中’上述金屬薄板為一銅猪。 在本發明之一實施例中，上述第一焊線與第二焊線是 由打線接合技術形成。 • 在本發明之一實施例中，上述蝕刻罩幕為一圖案化之 . 光阻層或是一圖案化之焊罩層。 在本發明之一實施例中，上述第一凸起部、第二凸起 部及第二凸起部其中之一或其組合為沉置設計。 本發明另提出一種晶片封裝結構，包括一晶片、一導 8 1334182 CN-9509009 22166twf.doc/n 線架、多條第一焊線、多條第二焊線、—上膠體、一第一 下膠體以及-第二下膠體。晶片具有一主動面、一背面與 多個晶片焊墊，其中晶片焊墊配置於主動面上。導線架具 有一上表面以及與其相對應之一下表面，其 '二 一晶片座、多個引腳以及至少一匯流架，其中晶片^背面 是固著於晶片座上。多個引腳環繞晶片座。^架位於晶 片座與引腳之間。第一焊線分別連接晶片焊墊與匯流架，The first bonding wire 130 electrically connects the grounding contact 126 to the bus bar 116. The second bonding wire 132 electrically connects the bus bar 116 to the ground pins of the inner leads 114. The third bonding wire 134 electrically connects the remaining inner bows 114 to the corresponding first contacts 128, respectively. The encapsulant 14 包覆 encloses the wafer holder 112, the inner leads 114, the busbar 116, the wafer 12A, the first bonding wire 13, the second bonding wire 132, and the third bonding wire 134 therein. It is worth noting that since the conventional wafer package structure 1 uses a patterned lead frame, the lead frame 110 itself has a die pad 112 and a plurality of inner leads. 114 and a plurality of bus bars 116. However, in the lead frame patterning process, an exposure developing mask of 6 I3M182 CN-9509009 22166 twf.doc/n must be used, which in turn increases the cost of the additional lead frame. [Invention] The present invention provides a chip package structure. And a manufacturing method thereof to solve the problem of using the BU formed by the patterned lead frame in the second package. Therefore, the present invention uses the metal=== process technology to form a guide on the metal thin plate::r and The foot 'so' will help to save the crystal. The outer side of the invention is replaced by a colloidal mask under the recess to replace the light sheet required for conventional exposure and development. The cost of the reticle, which in turn reduces the cost of sealing. The present invention proposes a system for manufacturing a chip package structure. First of all, to provide - a thin metal plate with a convex surface, the metal metal thin (4) has - the first. The 卩, - red raised portion and the plurality of third raised portions are 之间 = between the first raised portion and the third raised portion, and the first raised portion is convex, and the three raised portions are connected to each other. Next, the second soldering i is configured with a moving surface, a back surface and a plurality of wafer pads, one of which is on the active surface. Then, the back surface of the wafer is fixed to the first=the junction, the second is connected to the plurality of first bonding wires and the plurality of second bonding wires, and the second convex portion and the third convex portion are connected. Then, the shape of the upper colloid, wherein the upper layer is covered on the gold (four) plate ^ 7 1334182 CN-9509009 22166twf.doc / n ^ - Tan line and the second wire. Thereafter, a reticle cover is formed on the lower surface to expose the first projection, the second projection, and the third projection to each other. Finally, the metal thin plate is left until the first convex portion and the third convex portion are electrically insulated from each other, so that the first one forms a wafer holder and the second convex portion forms a bus bar. And a plurality of pins are formed in the third portion. In the embodiment of the present invention, the method for fabricating the above-mentioned chip package structure is to include a forming-down colloid after the step of engraving the metal thin plate, and the lower colloid is filled between the wafer holder, the bus bar and the pins. . In the present invention, the above-mentioned lower and (10) masks are coplanar. Eight In the embodiment of the present invention, the above (4) is further covered with a mask. In an embodiment of the present invention, the method for fabricating the chip package structure further includes removing the etching mask after the step of etching the metal thin plate, and then forming a lower colloid. In the embodiment of the present invention, the above metal sheet is a copper pig. In an embodiment of the invention, the first bonding wire and the second bonding wire are formed by a wire bonding technique. • In one embodiment of the invention, the etch mask is patterned. The photoresist layer or a patterned solder mask layer. In an embodiment of the invention, one of the first raised portion, the second raised portion and the second raised portion or a combination thereof is a sinking design. The invention further provides a chip package structure, comprising a wafer, a lead 8 1334182 CN-9509009 22166twf.doc/n wire frame, a plurality of first bonding wires, a plurality of second bonding wires, an upper colloid, a first lower Colloid and - second lower colloid. The wafer has an active surface, a back surface and a plurality of wafer pads, wherein the wafer pads are disposed on the active surface. The lead frame has an upper surface and a lower surface corresponding thereto, and a 'two wafer holder, a plurality of leads and at least one bus bar, wherein the back surface of the wafer is fixed to the wafer holder. A plurality of pins surround the wafer holder. The ^ is located between the wafer holder and the pin. The first bonding wires are respectively connected to the wafer pads and the bus bars,
而第二焊線分別連接匯流架與引腳。上膠體包覆住導線架 之上表面、晶片以及第一焊線與第二焊線。 、/、 在本發明之一實施例中，上述晶片封裝結構 钱刻罩幕’位於導線架之下表面。 在本發明之一實施例中，i述晶片封裝結 下膠體，填充於晶片座、匯流架以及引腳之間。 在本發明之一實施例中，上述晶片封裝結構，苴中下 膠體更包覆蝕刻罩幕。 八 更包含 更包括 且暴露 在本發明之一實施例中，上述晶片封裴結構 一姓刻罩幕，位於匯流架及引腳之下表面。 在本發明之一實施例中，上述晶片封裝結構 一下膠體’填充於晶片座、匯流架以及引腳之間 出晶片座之下表面。 一在本發明之一實施例中，上述晶片封裝結構，更包含 一姓刻軍幕，位於晶片座及匯流架之下表面。 一在本發明之一實施例中，上述晶片封裝結構，更包括 一下膠體，填充於晶片座、匯流架以及引腳之間，且暴露 9 13.34182 CN-9509009 22166twf.doc/n 出引腳之下表面。 在本發明之—實施例中，上述晶片封裝結 一蝕刻罩幕，位於匯流架之下表面。 。，更包含 在本發明之一實施例中， 一下膠體，填充於晶片座、匯 出晶片座及引腳之下表面。The second bonding wires are respectively connected to the bus bar and the pins. The upper body covers the upper surface of the lead frame, the wafer, and the first bonding wire and the second bonding wire. In one embodiment of the invention, the wafer encapsulation structure is located on the lower surface of the lead frame. In one embodiment of the invention, the wafer package is encapsulated under the wafer holder, the busbar, and the pins. In an embodiment of the invention, in the above chip package structure, the middle and lower colloids are further coated with an etching mask. VIII More Including and Exposed to an embodiment of the present invention, the above-mentioned wafer package structure is a mask, located on the bus bar and the lower surface of the pin. In one embodiment of the invention, the chip package structure is filled with a lower body of a lower surface of the wafer holder between the wafer holder, the bus bar, and the pins. In one embodiment of the invention, the chip package structure further includes a surnamed military screen located on the lower surface of the wafer holder and the bus bar. In one embodiment of the present invention, the chip package structure further includes a lower colloid, which is filled between the wafer holder, the bus bar, and the lead, and is exposed to the underside of the 13.34182 CN-9509009 22166twf.doc/n pin. surface. In an embodiment of the invention, the wafer package has an etch mask located on a lower surface of the bus bar. . Further included in an embodiment of the invention, the lower colloid is filled in the wafer holder, the outlet wafer holder, and the lower surface of the lead.
上述晶片封骏結構， 流架以及弓丨腳之間， 上述晶片封裝結構， 流架以及引腳之間， 更包括 且暴露 更包含 且包覆 在本發明之一實施例中， 一下膠體’填充於晶片座、匯 導線架之下表面。 在本發明之-實施例中，上述匯流架 其中之一或其組合可為沉置設計。 曰片从及引腳 本發明所揭露之晶片封裝結構的製作方法 片配置於金屬薄板上’再於晶片及金屬薄板上形兩晶 焊線以及封裝膠體。最後，_掉部分的金屬薄板，^ 开>成導線架之晶片座、匯流架以及引腳。 °The above-mentioned wafer sealing structure, between the flow frame and the bow and the foot, the above-mentioned chip package structure, the flow frame and the pins, and the like are further included and exposed and encapsulated in an embodiment of the present invention, the lower colloid 'filled On the wafer holder, the lower surface of the lead frame. In an embodiment of the invention, one or a combination of the above-described busbars may be a sinking design.从片从 and pin The method for fabricating the chip package structure disclosed in the present invention is that the sheet is disposed on a metal thin plate, and then the two crystal bonding wires and the encapsulant are formed on the wafer and the metal thin plate. Finally, the part of the metal sheet is turned off, and the wafer holder, the busbar, and the leads of the lead frame are formed. °
為讓本發明之上述特徵和優點能更明顯易懂，下 舉較佳實關’舰合觸圖式，作詳細說明如下。、 【實施方式】 圖3Α〜3G繪不為根據本發明第一實施例的—種晶片 封裝結構之製作流程剖面示意圖。首先，請參考圖3α，提 金屬薄板210 ’其具有相對設置的一上表面21〇a以及 下表面210b。金屬薄板21〇上形成有多個凹陷218，以 將上表面210a區分成一第一凸起部212、一第二凸起部214 1^4182 CN-9509009 22166twf.doc/n 以及多個第三凸起部216。第二凸起部2i4位於第一凸 ‘ =212的外側’而第三凸起部216則位於第二凸起部2 的外侧，且第—凸起部扣、第二凸起部214以Γ第三L 起部216彼此相連接。此外，第一凸起部212、第二⑽ •部214以及多個第三凸起部216分別具有晶片座、匯流 ，=:=:^_後續加工後可分別作為導線架 • 及引腳。在此實施例中，金屬薄板 =來’請參考圖3B’提供一晶片22〇，晶片22〇且 ==20:、：背面22%以及多個晶片焊塾222,其 ==:面：=:，-配 ^隻上然後，將晶片220之背面22〇b固著 於第一凸起料2上，固著的方式例如是以-紫外線固化 膠體或熱固化勝體將晶片22〇點著於第一凸起^ ^上。 -焊圖3c，形成多條第一焊線230及多條第 _ 第—焊線23G分別電性連接於晶片焊墊 3d部214與第三凸起部216之間。上述第 、‘’ 以及第一焊線24〇可由打線接合方式形成。 • 再來，請參考圖3D，形成一上膠體250，其中上膜體 • ^金屬薄請之上表面、，^^ 弟一知線230以及第二焊線24〇。 ^ ，請參考圖3E ’在金屬薄板別之下表面鹰 ^ 刻罩幕270，其中蝕刻罩幕270可為—圖案化之 CN-9509009 22166twf.doc/n 光阻層或是-目案化之料 第一凸起部212、第二凸击暴路出金屬薄板21〇之 此相連的部分。 。卩14 M及第三凸起部216彼 起部ίί、’ ，，薄板210，直到第-凸 缘，如此，第& j214與第三凸起部216彼此電性絕In order to make the above-mentioned features and advantages of the present invention more apparent and easy to understand, the following is a better example of the ship-to-eye contact pattern, which is described in detail below. [Embodiment] Figs. 3A to 3G are schematic cross-sectional views showing a manufacturing process of a wafer package structure according to a first embodiment of the present invention. First, referring to Fig. 3α, the metal thin plate 210' has an upper surface 21a and a lower surface 210b which are disposed opposite each other. A plurality of recesses 218 are formed on the metal thin plate 21 to divide the upper surface 210a into a first convex portion 212, a second convex portion 214 1^4182, CN-9509009 22166twf.doc/n, and a plurality of third convex portions. Starting portion 216. The second raised portion 2i4 is located outside the first convex '=212' and the third raised portion 216 is located outside the second raised portion 2, and the first raised portion buckle and the second raised portion 214 are The third L starting portions 216 are connected to each other. In addition, the first raised portion 212, the second (10) portion 214, and the plurality of third raised portions 216 respectively have a wafer holder and a confluent flow, and =:=:^_ can be used as a lead frame and a lead respectively after subsequent processing. In this embodiment, the metal foil = 'Please refer to FIG. 3B' to provide a wafer 22, wafer 22 and == 20:, 22% back and a plurality of wafer pads 222, which ==: face: = Then, the back surface 22〇b of the wafer 220 is fixed on the first bump 2, and the wafer 22 is affixed by, for example, an ultraviolet curing colloid or a heat curing body. On the first protrusion ^ ^. The plurality of first bonding wires 230 and the plurality of first bonding wires 23G are electrically connected between the die pad 3d portion 214 and the third bump portion 216, respectively. The above first, ‘’ and first bonding wires 24〇 may be formed by wire bonding. • Referring again to FIG. 3D, an upper body 250 is formed, in which the upper film body is placed on the upper surface of the metal film, and the second wire bond wire 230 is formed. ^, please refer to FIG. 3E 'the underside of the metal sheet is etched by the mask 270, wherein the etching mask 270 can be - patterned CN-9509009 22166twf.doc/n photoresist layer or - visualization The first raised portion 212 and the second protruding portion of the metal sheet 21 are connected to each other. . The 卩14 M and the third raised portion 216 are opposite to each other, and the thin plate 210 is up to the first flange. Thus, the & j214 and the third raised portion 216 are electrically connected to each other.
Lt，此；=212即可作為導線架训，… =几L 部214即可作為-匯流架214,，而這 :口：=216即可作為引腳216，。至此即大致完成 日曰片封裝結構200之製作流程。 為防止晶片座212，、匯流架214，以及引腳216，因暴露 於空氣中而易發生氧化的問題，請參考圖犯所示，可形 成-下膠體260 ’下膠體26G填充於晶片座212,、匯流架 214’以及引腳216’之間’其中下膠體施與钱刻罩幕27〇 為共平面。 下膠體260除了以上述方式配置以外，本領域的技術 人員亦可以其他方式配置’本發明並不對此加以限制。圖 4繪示為根據本發明另一實施例的一種晶片封裝結構之剖 面示意圖。請參照圖4’在本實施例中，晶片封裝結構3〇〇 之下膠體360不僅填充於晶片座212,、匯流架214,以及弓丨 腳216’之間，更包覆下表面210b以及蝕刻罩幕270。 圖5繪示為根據本發明又一實施例的一種晶片封襄結 構之剖面示意圖。請參照圖5，在製作晶片封裝結構4〇〇 時，於餘刻金屬薄板210之步驟之後’亦可先移除餘刻罩 幕270，之後再形成下膠體460，並使下膠體460包覆下表 12 1334182 CN-9509009 22l66twf.d〇c/n 面210b。移除蝕刻罩幕27〇的方法例如為使用有機溶劑溶 解姓刻罩幕270以將钱刻罩幕270去除。 _弟二實施例_ 圖6繪示為根據本發明第二實施例的一種晶片封裝結 構之剖面示意圖。需先說明的是’在第二實施例與第一實 施例中’相同或相似的元件標號代表相同或相似的元件， 且第二實施例與第一實施例大致相同。以下將針對兩實施 例不同之處詳加說明，相同之處便不再贅述。 請參照圖6,第二實施例與第一實施例不同之處在 於：在晶片封裝結構500中，金屬薄板510之第二凸起部 514為沉置設計。也就是說，第二凸起部514的上表面51加 較第一凸起部212以及第三凸起部216的上表面51〇a低。 在金屬薄板510形成導線架510,，而第一凸起部212、第 二凸起部514以及第三凸起部216形成晶片座212,、匯流 架514’以及引腳216’後，會使匯流架514’為沉置設計，如 此可達成更佳之模流平衡。除此之外，本領域的技術人員 亦可使晶片座212’或引腳216,為沉置設計，又或者是使晶 片座212’、匯流架514’以及引腳216,其中任意兩者之組^ 為沉置設計，本發明並不對此加以限制。 第三實施例 圖7繪示為根據本發明第三實施例的一種晶片封裝结 構之剖面示意圖。需先說明的是，在第二實施例與第—實 施例中’相同或相似的元件標號代表相同或相似的元件， 且第二實施例與第一實施例大致相同。以下將針對兩實施 13 13.34182 CN-9509009 22166twf.doc/n 例不同之處詳加說明，相同之處便不再贅述_。 請參照圖7，第三實施例與第一實施例不同之處在 於，在晶片封裝結構600之導線架610,中，晶片座612, 的厚度大於匯流架214’的厚度以及引腳216,的厚度，而晶 片座612’、匯流架214’以及引腳216,的上表面210a仍維 持在同一平面。在完成晶片封裝結構6〇〇基本製作流程 後，移除掉位於晶片座612,之下表面610b上之蝕刻罩幕 270，使晶片座612’之下表面61〇b直接與外界接觸，以有 效地提昇晶片封農結構600的散熱效率 另外，亦可使蝕刻罩幕與下膠體暴露出引腳乏下表 面。圖8繪示為根據本發明再一實施例的一種晶片封裝結 構之剖面示意圖。請參照圖8，在晶片封裝結構7〇〇之導 線架710’中，蝕刻罩幕27〇與下膠體26〇暴露出引腳716, 的下表面710b。如此，可將晶片封裝結構7〇〇應用於無引 腳封裝結構中，例如將晶片封裝結構700應用於四方扁'平 無引腳封I結構。除此之外，本領域的技術人貞亦可使姓 也罩幕與下膠縣露料線架其他部分之下表面，例如可 使侧罩幕與下膠體同時暴露出引腳之下表面以及晶片座 .之下表面，本發明並不對此加以限制。 綜上所述，本發明提出一種全新的晶片封裝結構之製. :::凸:ί ’提供一具有第一凸起部、第二凸起部及多 二，。卩之金屬薄板。之後，將晶片配置於金屬薄板 ⑽ί形成用以電性連接晶片與第二凸起部以及第二凸起 第二凸起部之間的多條焊線。接著，於金屬薄板之上 14 1334182 CN-9509009 22166twf.doc/n 下表面上形成上膠體。然後，在下表面上形成一餘刻罩幕， 此餘刻罩幕暴露出第一凸起部、第二凸起部與三凸起部之 間彼，相連的部分。最後，钱刻此金屬薄板，使第一凸起 部、第二凸起部以及第三凸起部分別形成為導線架 座、匯流架以及引腳。 、Μ 本發明所揭露之晶片封裝結構的製作方法有別 知之以導線架作為承載H的晶4封裝製程之處在於知 ^曰片封^程是直接以現成的_化導絲進行晶片之 2❿發明之晶#封裝結構是先將W =的之焊線以及封裝膠體，最後，再 :二!2 形成導線架之晶片座、匯流架以及引 一金料板提供之晶#封裝結構的製作方法是使用 屬薄程當中藉由闕製程技術，以於金 將可節省線架之晶片座、匯流架以及引腳，如此， 化導線架:造成=成術中因直接使用圖案 沉置設計，以達中之—或疋其中任意兩者之組合為 片封裝結構巾，^㈣之_流平衡。糾，在本發明之晶 表面，以提高刻罩幕與下膠體暴露出晶片座之下 刻罩幕與結構之散熱效^再者，亦可使钱 應用於無⑽封裝結構卜 封裝結構 雖然本發明已以較佳實施例揭露如上，然其並非用以 15 CN-9509009 22166twf.d〇c/1 限定本發明’任何所屬技術領域中具 脫離本發明之精姊翻Θ，當 ^ :本發明之保護範圍當視後附之申請:==者 【圖式簡單說明】 習知之晶片封裝體的上視示意圖。 緣不為圖1晶片封裝體的剖面示意圖。 封上I0繪示為根據本發明之-實施例的-種晶片 封裝結構之製作流程剖面示意圖。 稷曰日片 圖4繪示為根據本蘇 構之剖面示意圖。㈣—實施觸—種晶片封襄結 實施例的一種晶片封裝結 圖5繪示為根據本發明又 構之剖面示意圖。 構之據本發明第二實施_一種晶片封裝結 構之根據本發明第三實施例的-種晶片封裝結 根據本發明再-實施_-種晶片封“ 【主要元件符號說明】 100 ·晶片封裝體 110 :導線架 1334182 CN-9509009 22166twf.doc/n 112 :晶片座 114 :内引腳 116 :匯流架 120 :晶片 130 :第一焊線 132 :第二焊線 • 134 :第三焊線 140 :封裝膠體 鲁 200、300、400、500、600、700 :晶片封裝結構 210、510 :金屬薄板 210’、510’、610’、710’ ：導線架 210a、510a :上表面 210b、610b、710b :下表面 212 :第一凸起部 212’、612’ ：晶片座 214、514 :第二凸起部 • 214’、514’ ：匯流架 216 :第三凸起部 216’、716’ ：引腳 218 :凹陷 220 :晶片 220a :主動面 220b :背面 222 :晶片接墊 17 1334182 CN-9509009 22166twf.doc/n 230 :第一焊線 240 :第二焊線 250 :上膠體 260、360、460 :下膠體 262 :凹部 270 :蝕刻罩幕Lt, this; = 212 can be used as a wire train, ... = a few L parts 214 can be used as - bus 214, and this: port: = 216 can be used as pin 216. At this point, the production process of the enamel package structure 200 is substantially completed. In order to prevent the wafer holder 212, the bus bar 214, and the pin 216 from being oxidized due to exposure to the air, please refer to the figure, and the lower colloid 260' can be formed on the wafer holder 212. , between the bus bar 214' and the pin 216' 'where the lower colloid is applied to the money mask 27 is coplanar. The colloid 260 may be configured in other ways in addition to being configured in the above-described manner. The present invention is not limited thereto. 4 is a cross-sectional view showing a chip package structure in accordance with another embodiment of the present invention. Referring to FIG. 4', in the embodiment, the wafer 360 is not only filled in the wafer holder 212, the bus bar 214, and the bow pin 216', but also covers the lower surface 210b and is etched. Cover 270. FIG. 5 is a cross-sectional view showing a wafer sealing structure according to still another embodiment of the present invention. Referring to FIG. 5, when the chip package structure 4 is fabricated, after the step of refining the metal thin plate 210, the residual mask 270 may be removed first, then the lower colloid 460 is formed, and the lower colloid 460 is covered. Table 12 1334182 CN-9509009 22l66twf.d〇c/n Face 210b. The method of removing the etching mask 27 is, for example, to dissolve the surname mask 270 using an organic solvent to remove the money mask 270. Embodiment 2 FIG. 6 is a cross-sectional view showing a wafer package structure according to a second embodiment of the present invention. It is to be noted that the same or similar element numbers as in the second embodiment and the first embodiment represent the same or similar elements, and the second embodiment is substantially the same as the first embodiment. The differences between the two embodiments will be explained in detail below, and the same points will not be described again. Referring to FIG. 6, the second embodiment is different from the first embodiment in that, in the chip package structure 500, the second raised portion 514 of the thin metal plate 510 is in a sinking design. That is, the upper surface 51 of the second boss portion 514 is lower than the upper surface 51A of the first boss portion 212 and the third boss portion 216. The lead frame 510 is formed on the metal thin plate 510, and the first convex portion 212, the second convex portion 514 and the third convex portion 216 form the wafer holder 212, the bus bar 514' and the pin 216', which may cause The busbar 514' is designed for placement so that a better mold flow balance can be achieved. In addition, those skilled in the art can also design the wafer holder 212' or the pin 216 as a sink, or the wafer holder 212', the bus bar 514', and the pin 216, either of which The group ^ is designed for sinking, and the invention is not limited thereto. THIRD EMBODIMENT Fig. 7 is a cross-sectional view showing a wafer package structure in accordance with a third embodiment of the present invention. It is to be noted that the same or similar elements as in the second embodiment and the embodiment denote the same or similar elements, and the second embodiment is substantially the same as the first embodiment. In the following, the differences between the two implementations 13 13.34182 CN-9509009 22166twf.doc/n will be explained in detail, and the same points will not be repeated. Referring to FIG. 7, the third embodiment is different from the first embodiment in that, in the lead frame 610 of the chip package structure 600, the thickness of the wafer holder 612 is greater than the thickness of the bus bar 214' and the pin 216. The thickness, while the upper surface 210a of the wafer holder 612', the busbar 214', and the pins 216, remains in the same plane. After the basic fabrication process of the chip package structure 6 is completed, the etching mask 270 on the lower surface 610b of the wafer holder 612 is removed, so that the lower surface 61〇b of the wafer holder 612' is directly in contact with the outside to effectively The heat dissipation efficiency of the wafer sealing structure 600 can be increased. In addition, the etching mask and the lower colloid can be exposed to the exposed surface of the lead. FIG. 8 is a cross-sectional view showing a wafer package structure according to still another embodiment of the present invention. Referring to FIG. 8, in the lead frame 710' of the chip package structure 7, the etching mask 27 and the lower body 26 are exposed to expose the lower surface 710b of the pin 716. Thus, the chip package structure 7 can be applied to a leadless package structure, for example, the wafer package structure 700 can be applied to a quad flat [no-lead package I structure. In addition, the skilled person in the art can also make the surname also cover the lower surface of other parts of the strip line of the rubber strip, for example, the side mask and the lower colloid can simultaneously expose the lower surface of the lead and The lower surface of the wafer holder is not limited by the present invention. In summary, the present invention proposes a novel chip package structure. The ::: convex: ί ' provides a first raised portion, a second raised portion and a plurality. A thin metal sheet. Thereafter, the wafer is disposed on the metal thin plate (10) to form a plurality of bonding wires for electrically connecting the wafer with the second raised portion and the second raised second raised portion. Next, an upper colloid is formed on the lower surface of the metal sheet 14 1334182 CN-9509009 22166twf.doc/n. Then, a residual mask is formed on the lower surface, and the remaining mask exposes a portion where the first convex portion, the second convex portion and the three convex portions are connected. Finally, the metal sheet is engraved such that the first raised portion, the second raised portion, and the third raised portion are formed as lead frame holders, bus bars, and pins, respectively. The method for fabricating the chip package structure disclosed in the present invention is that the lead frame is used as the crystal 4 package process for carrying H. The process of the chip package is to directly perform the wafer with the ready-made wire. The invention of the crystal # package structure is to first W = the wire and the encapsulation, and finally: two! 2 to form the wafer holder of the lead frame, the bus frame and the gold plate provided by the crystal # package structure manufacturing method It is the use of the 薄 process technology in the thin-film process, so that the gold will save the wafer holder, the busbar and the lead of the wire frame. Thus, the lead frame is caused by the direct use of the pattern sinking design. Among them - or a combination of any two of them is a sheet package structure towel, ^ (4) _ flow balance. Correction, in the crystal surface of the present invention, to improve the heat dissipation effect of the mask and the structure under the wafer holder under the wafer cover, and the money can be applied to the (10) package structure, although the package structure is The invention has been disclosed in the preferred embodiments as above, but it is not intended to limit the invention in any of the technical fields of the invention, which is not limited to 15 CN-9509009 22166 twf.d〇c/1. The scope of protection is attached to the application: == [Simplified illustration] A schematic view of a conventional chip package. The edge is not a schematic cross-sectional view of the chip package of FIG. The sealing I0 is a schematic cross-sectional view showing the manufacturing process of the wafer package structure according to the embodiment of the present invention.稷曰日片 Figure 4 is a schematic cross-sectional view of the present invention. (4) - Implementation of a touch wafer package junction A wafer package junction of an embodiment Fig. 5 is a cross-sectional view showing a structure according to the present invention. According to a second embodiment of the present invention, a chip package structure according to a third embodiment of the present invention is further embodied in accordance with the present invention. 110: lead frame 1343182 CN-9509009 22166twf.doc/n 112: wafer holder 114: inner lead 116: bus bar 120: wafer 130: first bonding wire 132: second bonding wire • 134: third bonding wire 140: Package colloids 200, 300, 400, 500, 600, 700: chip package structures 210, 510: metal sheets 210', 510', 610', 710': lead frames 210a, 510a: upper surfaces 210b, 610b, 710b: Lower surface 212: first raised portion 212', 612': wafer holder 214, 514: second raised portion 214', 514': bus bar 216: third raised portion 216', 716': pin 218: recess 220: wafer 220a: active surface 220b: back surface 222: wafer pad 17 1334182 CN-9509009 22166twf.doc/n 230: first bonding wire 240: second bonding wire 250: upper colloids 260, 360, 460: Glue 262: recess 270: etching mask