CN100523824C - Detection circuit layout and manufacturing method of liquid crystal display panel - Google Patents

Abstract

A detection circuit layout is suitable for grouping detection panel units, wherein each panel unit has a plurality of first signal lines and second signal lines. The detection circuit layout includes a multiplexer and a detection pad. The multiplexer is electrically connected to at least one of the first signal line and the second signal line of the panel units, and the detection pad is electrically connected to the multiplexer, and the multiplexer is suitable for selectively connecting the detection pad to the first or second signal line of a group of panel units.

Description

Detecting circuit layout and manufacturing method of liquid crystal display panel

technical field

The invention relates to a detection technology of a panel, and in particular to a detection circuit layout of a panel and a manufacturing method of a liquid crystal display panel.

Background technique

The rapid progress of the multimedia society is mostly due to the rapid progress of semiconductor devices or display devices. As far as displays are concerned, liquid crystal displays (LCDs) with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market.

FIG. 1 is a three-dimensional exploded schematic diagram of a known active matrix LCD panel (active matrix LCD panel, AM-LCD panel). Referring to FIG. 1 , an active array liquid crystal display panel 100 includes an active element array substrate 110 , a liquid crystal layer 120 and a color filter (color filter, CF) 130 . Wherein, the color filter 130 is located above the active device array substrate 110 , and the liquid crystal layer 120 is disposed between the active device array substrate 110 and the color filter 130 . The active element array substrate 110 is provided with a plurality of active elements 112 arranged in an array and a pixel electrode (pixel electrode) 114 corresponding to each active element 112 , and these active elements 112 are used as switching elements of pixel units. Moreover, in order to drive the active device 112 in individual pixel units, a specific pixel is usually selected through a scan line 116 and a data line 118, and an appropriate operating voltage for the pixel is provided to display the corresponding pixel. screen.

FIG. 2 is a schematic diagram of a detection circuit layout of a known panel unit. Please refer to FIG. 2. The manufacturing process of the active matrix liquid crystal display panel 100 in FIG. 1 is to first assemble a large active element array substrate and a large color filter to seal the liquid crystal layer in between, and then form multiple array arrangements. The panel unit 200. Afterwards, a cutting process is performed to form a plurality of active matrix liquid crystal display panels 100 shown in FIG. 1 .

The electrical detection method of the known panel unit 200 is to connect the scan wiring and data wiring of each panel unit 200 in series with the scanning wiring and data wiring of other panel units 200 through a shorting bar (shorting bar) 140 respectively. together, and electrically connect the shorting bar 140 to the pad 210 . Afterwards, a probe (not shown in the figure) is pressed on the pad 210 to input a signal to the scanning wiring of each panel unit 200 through the probe, so as to turn on the active device 112 in FIG. 1 . Then, the detection signal is transmitted to the data wiring in each panel unit 200 through the probe, so that each panel unit 200 displays a picture according to the detection signal. At this time, relevant personnel can judge whether these panel units 200 are qualified products according to the screens displayed by the panel units 200 .

In the manufacturing process of small-sized display panels, one glass substrate can be used to form tens or hundreds of panel units. As shown in FIG. 2 , if these panel units 200 of a large number are to be electrically tested simultaneously, these panel units 200 must be maintained in a charged state, and the probes pressed on the contact pads 300 (Fig. (not shown in ) transmits the detection signal to each panel unit 200 . That is to say, during the detection process, the active components (not shown) in these panel units 200 are all turned on, and the active components in all panel units 200 are not turned off until all the panel units 200 are tested.

Although in the above detection method, it is only necessary to manufacture a set of probes and press them on the pads 210 to complete the detection of all the panel units 200 . However, if the active element is turned on for a long time, the characteristics of the active element will change, so that it cannot work normally.

For this reason, the known technology proposes another detection method to solve the above-mentioned problems. FIG. 3 is a schematic diagram of a detection circuit layout of another known panel unit. Referring to FIG. 3 , in this detection method, the panel units 200 are divided into multiple groups, and each group of panel units 200 is electrically connected to its corresponding pad 300 . Therefore, when testing the panel units 200, it is only necessary to charge a certain group of panel units 200 to be tested, and press the probes (not shown) to the pads 300 corresponding to the group of panel units 200 Then, the detection signal can be transmitted to the group of panel units 200 . Moreover, after the detection of the group of panel units 200 is completed, the active components in the group of panel units 200 can be turned off. In other words, this detection method can shorten the time that the active element is in the on state.

However, since this detection method can only detect one group of panel units at a time, each time a group of panel units is tested, the probes need to be moved to the pads corresponding to another group of panel units, and each time the probe is moved The needle needs to be aligned again so that the probe can actually press down on the pad. When the number of panel units is large, it takes a long detection time to complete the detection of all the panel units. Although the number of probe sets can be increased to simultaneously inspect multiple groups of panel units, thereby shortening the inspection time, the relative inspection cost also needs to be increased.

Contents of the invention

The object of the present invention is to provide a detection circuit layout, which can shorten the time required for individually testing a single panel unit or a single group of panel units.

Another object of the present invention is to provide a method for manufacturing a liquid crystal display panel, which can shorten the time required for the lighting test of the same batch of liquid crystal display panels.

To achieve the above or other objectives, the present invention proposes a detection circuit layout, which is suitable for testing a single panel unit or a single group, wherein each panel unit has a plurality of first signal lines and a plurality of second signal lines. The detection circuit layout includes a first multiplexer (MUX) and a first detection pad. Wherein, the first multiplexer is electrically connected to the first signal lines of these panel units, and the first detection pad is electrically connected to the first multiplexer, and the first multiplexer is suitable for The first detection pad is selectively connected to the first signal line of a group of panel units.

In an embodiment of the present invention, the above-mentioned first signal line is, for example, a scanline, and the second signal line is, for example, a data line.

In an embodiment of the present invention, the above-mentioned detection circuit layout further includes a plurality of first short-circuit bars, which are electrically connected to the above-mentioned first multiplexer, and each first short-circuit bar is connected in series with its Part or all of the first signal lines of a corresponding group of panel units. For example, these first shorting bars include a plurality of first odd shorting bars and a plurality of first even shorting bars, and each first odd shorting bar is an odd number of first signal lines connected in series to a group of panel units, and Each of the first even-numbered shorting bars is an even-numbered first signal line connected in series with a group of panel units.

In an embodiment of the present invention, the above detection circuit layout further includes a plurality of electrostatic discharge (electrostatic discharge, ESD) protection components, which are respectively electrically connected to the corresponding first shorting bar and the first signal of the group of panel units. between lines.

In an embodiment of the present invention, the above-mentioned first multiplexer includes a plurality of first control transistors, the drains of these first control transistors are respectively electrically connected to the first detection pads, and each first control transistor The sources of the transistors are respectively electrically connected to the first signal lines of a corresponding group of panel units.

In an embodiment of the present invention, the above detection circuit layout further includes a first refresh signal supply unit, which is electrically connected to the first multiplexer. Moreover, the above-mentioned first multiplexer further includes a plurality of first refresh transistors, and the source of each first refresh transistor is electrically connected between the source of the corresponding first control transistor and the first signal line, The drains of these first refresh transistors are respectively electrically connected to the above-mentioned first refresh signal supply unit.

In an embodiment of the present invention, the above detection circuit layout further includes a second multiplexer and a second detection pad, electrically connected to the second signal lines of these panel units, and the second detection pad is electrically The second multiplexer is connected to the second multiplexer, and the second multiplexer is suitable for selectively conducting the second detection pad with the second signal line of a group of panel units.

In an embodiment of the present invention, the above-mentioned detection circuit layout further includes a plurality of second short-circuit bars, which are electrically connected to the above-mentioned second multiplexer, and each second short-circuit bar is connected in series to its Part or all of the second signal lines of a corresponding group of panel units. For example, these second short-circuit bars include a plurality of second odd-number short-circuit bars and a plurality of second even-number short-circuit bars, and each second odd-number short-circuit bars are odd-number second signal lines connected in series to a group of panel units, and each The second even-numbered shorting bars are even-numbered second signal lines connected in series to a group of panel units.

In an embodiment of the present invention, the above detection circuit layout further includes a plurality of electrostatic discharge (electrostatic discharge, ESD) protection components, which are respectively electrically connected to the corresponding second shorting bar and the second signal of the group of panel units. between lines.

In an embodiment of the present invention, the above-mentioned second multiplexer includes a plurality of second control transistors, the drains of these second control transistors are respectively electrically connected to the second detection pads, and each second control transistor The sources of the transistors are respectively electrically connected to the second signal lines of a corresponding group of panel units.

In an embodiment of the present invention, the above detection circuit layout further includes a second refresh signal supply unit, which is electrically connected to the above second multiplexer. Moreover, the above-mentioned second multiplexer further includes a plurality of second refresh transistors, and the source of each second refresh transistor is electrically connected between the source of the corresponding second control transistor and the second signal line, The drains of the second refresh transistors are respectively electrically connected to the above-mentioned second refresh signal supply unit.

The present invention also proposes a method for manufacturing a liquid crystal display panel, which comprises first forming a liquid crystal layer on a first substrate, then providing a second substrate, and then assembling the first substrate and the second substrate so that the liquid crystal layer is sealed on the first substrate. Multiple groups of panel units are formed between the substrate and the second substrate. Afterwards, the above-mentioned detection circuit layout is formed, and then the lighting signal is input to the detection circuit layout, so as to perform a lighting test on these panel units. After the test is completed, the assembled first substrate and the second substrate are cut to form a plurality of liquid crystal display panels.

In an embodiment of the present invention, the method for forming the liquid crystal layer includes one drop fill (ODF).

In one embodiment of the present invention, before forming the above-mentioned liquid crystal layer, it also includes forming a sealant on the first substrate to surround a plurality of liquid crystal injection regions on the first substrate, and the subsequently formed liquid crystal layer is located at the These liquid crystals are injected into the region. In addition, the method for assembling the first substrate and the second substrate is, for example, to press the first substrate and the second substrate first, and then cure the sealant. Wherein, the method of curing the sealant is, for example, thermal curing or ultraviolet curing.

The detection circuit layout of the present invention is to use a multiplexer to selectively conduct some panel units with the detection pads, so as to group and detect panel units, so that all panels can be completed without moving the probe during the detection process. unit detection.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with accompanying drawings.

Description of drawings

FIG. 1 is a three-dimensional schematic diagram of a conventional active matrix liquid crystal display panel.

FIG. 2 is a schematic diagram of a detection circuit layout of a known panel unit.

FIG. 3 is a schematic diagram of a detection circuit layout of another known panel unit.

FIG. 4 is a schematic diagram of the detection circuit layout in the first embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of the multiplexer 510 in FIG. 4 .

FIG. 6 is a schematic diagram of the detection circuit layout in the second embodiment of the present invention.

Fig. 7 is a schematic diagram of the detection circuit layout in the third embodiment of the present invention.

FIG. 8 is a schematic circuit diagram of the multiplexer 710 in FIG. 7 .

9A to 9C are schematic top views of the manufacturing process of the liquid crystal display panel in an embodiment of the present invention.

Description of main component marking

100: active array liquid crystal display panel

110: active element array substrate

112: Active components

114: pixel electrode

116: scan line

118: data line

120, 620: liquid crystal layer

130: color filter

140, 150, 540, 540o, 540e: shorting bar

200, 502: panel unit

210, 220, 300: Pads

500, 700: detection line layout

504a: the first signal line

504b: second signal line

512, 712: control transistor

514, 714: Transistor

520, 720: detection pad

530, 730: select signal pad

550: Electrostatic discharge protection components

560, 760: refresh signal supply unit

610: first substrate

614: frame glue

616: Liquid crystal injection area

630: second substrate

A ₁ , A ₂ , ..., A _n-1 , A _n : Groups of panel units

D1, D2, D1’, D2’: drain

G1, G2, G1’, D2’: gate

IS, IS': detection signal

RS: refresh signal

SS, SS’: select signal

S1, S2, S1’, S2’: source

Detailed ways

FIG. 4 is a schematic diagram of the detection circuit layout in the first embodiment of the present invention. Please refer to FIG. 4, the detection circuit layout 500 of the present invention is used to detect a plurality of panel units 502, wherein these panel units 502 respectively have a plurality of first signal lines 504a and second signal lines 504b, and the panel unit 502 That is, the detection signal input from the detection circuit layout 500 is received through the first signal line 504a and the second signal line 504b. In this embodiment, the first signal line 504a is, for example, a scan line, and the second signal line 504b is, for example, a data line.

Please continue to refer to FIG. 4 , the detection circuit layout 500 includes a multiplexer 510 and a detection pad 520 . Wherein, the detection pad 520 is electrically connected to the multiplexer 510 and used for receiving a detection signal for detecting the panel unit 502 . The multiplexer 510 is connected between the detection pad 520 and the first signal line 504a of the panel unit 502 to selectively conduct the detection pad 520 and the first signal line 502 of a certain group of panel units 502 to be detected. The signal line 504 a is used to transmit the detection signal from the detection pad 520 to the group of panel units 502 through the first signal line 504 a. In addition, the selection signal SS for controlling the multiplexer 510 is transmitted to the multiplexer 510 through the selection signal pad 530 electrically connected to the multiplexer 510 .

It is worth mentioning that the first signal lines 504a of each group of panel units 502 are connected in series through short-circuit bars 540, and the multiplexer 510 is connected with the first signal lines of the panel units 502 through these short-circuit bars 540. The signal line 504a is electrically connected. In this way, the signal output by the multiplexer 510 can be simultaneously transmitted to all the panel units 502 of the same group through the shorting bar 540 . Wherein, these shorting bars 540 include odd numbered shorting bars 540o and even numbered shorting bars 540e. The signal lines 504a are short-circuited to each other through the even-numbered short-circuit bars 540e. Certainly, the present invention does not limit that the first signal lines 504a of the even number and the first signal lines 504a of the odd number must be short-circuited to each other. There are other ways to short-circuit the first signal lines 504a in groups.

In addition, an electrostatic discharge protection component 550 may be provided between each shorting bar 540o or shorting bar 540e and the first signal line 504a connected thereto, which is used to provide a dissipation path for the static charge in the panel unit 502 to avoid Electrostatic breakdown occurs in the panel unit 502 .

The electronic components inside the multiplexer 510 will be described with examples below, so as to further describe the working principle of the multiplexer 510 in detail.

FIG. 5 is a schematic circuit diagram of the multiplexer 510 in FIG. 4 . Referring to FIG. 5 , the multiplexer 510 includes, for example, a control transistor 512 . Wherein, the drains D1 of the control transistors 512 are respectively electrically connected to the detection pads 520 , and the sources S1 thereof are respectively electrically connected to the first signal lines 504 a of the corresponding group of panel units 502 .

Please refer to FIG. 4 and FIG. 5 at the same time. In this embodiment, the panel unit 502 in FIG. 4 is divided into groups such as A ₁ , A _{2 ,} . _. . Since the first signal line 504a of this embodiment is a scanning line, and the multiplexer 510 is used to selectively conduct the detection pad 520 and the first signal line 504a of each group of panel units 502, so in FIG. 4 The panel units 502 in the same row are divided into the same group.

It can be known from the above that if the panel unit 502 of group _A1 is to be detected, a group of probes (not shown in the figure) can be pressed on the detection pad 520 and the selection signal pad 530, so that the probes can respectively The detection signal IS and the selection signal SS are transmitted to the detection circuit layout 500 by an external circuit. The multiplexer 510 applies a voltage to the gate G1 of the control transistor 512 electrically connected to the _A1 group panel unit 502 according to the selection signal SS, and then turns on the control transistor 512 . In this way, the detection signal IS can be transmitted from the detection pad 520 through the drain D1, the source S1 and the first signal line 504a of the control transistor 512 to the A1 group panel unit 502 to be detected. Here, since the first signal line 504a of this embodiment is a scanning line, after the detection signal IS is transmitted to the panel unit 502 of group _A1 , each pixel of the panel unit 502 of this group will be turned on. To the data lines of all panel units 502 in group A1, relevant personnel can judge whether the panel units 502 in group _A1 are qualified products according to the working conditions of each panel unit 502.

In particular, the multiplexer 510 of this embodiment may further include a plurality of refresh transistors 514, wherein the source S2 of each refresh transistor 514 is electrically connected to the source S1 of the corresponding control transistor 512 and the first signal line 504a, and the drain D2 is electrically connected to a refresh signal supply unit 560 . After detecting the panel unit 502 of group _A1 , if the detection of the next group of panel unit 502 is to be performed, the control transistor 512 connected to group _A1 can be turned off, and the refresh transistor 514 can be turned on, so that the refresh signal is supplied to the unit The refresh signal (refresh signal) RS output by 560 is sequentially transmitted to the panel unit 502 of group A1 through _{the drain D2 and source S2 of the refresh transistor 514, and then the detection signal in the panel unit 502 of group A1 is} refreshed (refresh) .

Based on the above, after refreshing the detection signals in the panel units 502 of group _A1 , the refresh transistors 514 corresponding to group _A1 can be turned off, and then the detection of other panel units 502 is performed in the same way. It is particularly worth mentioning that, during the detection process of the next group of panel units 502, there is no need to move the probes that are pressed on the detection pads 520, as long as the multiplexer 510 is used to select the control transistor 512 to be turned on. .

It can be seen that, in the process of detecting the _A1 group panel unit 502, since the detection signal will not be transmitted to other group panel units 502, it is not necessary to turn on the active components in the other group panel units 502, only the A1 group being detected The active components in _one group of panel units 502 need to be in an open state. In other words, the detection circuit layout 500 of the present invention can perform group detection on the panel units 502, so as to shorten the time that the active components in each panel unit 502 are in the on state, thereby preventing the active components in the panel unit 502 from being in the open state for a long time. damage.

It should be mentioned that although the multiplexer in the above embodiment is used to selectively connect the detection pads and the scan lines of the panel unit, those skilled in the art should know that the detection circuit layout 500 The provided multiplexer 510 can also be used to selectively connect the detection pad 520 with the data line (that is, the second signal line 504 b ) of the panel unit 502 , as shown in FIG. 6 . Moreover, the detection circuit layout of the present invention can also use two multiplexers to selectively connect the detection pads and the scan lines and data lines of the panel units, so as to individually detect each panel unit. Examples will be given below to illustrate it.

Fig. 7 is a schematic diagram of the detection circuit layout in the third embodiment of the present invention. Referring to FIG. 7 , the components constituting the detection circuit layout 700 include a multiplexer 710 and a detection pad 720 in addition to the multiplexer 510 and the detection pad 520 in the foregoing embodiments. In this embodiment, these panel units 502 are arranged in a determinant matrix. Wherein, the multiplexer 510 is used to selectively conduct the detection pad 520 and the first signal line 504a (scanning line) of a certain row (column) panel unit 502, and the multiplexer 710 is used to The detection pad 720 is selectively connected to the second signal line 504 b (data line) of a row of panel units 502 . Moreover, as shown in FIG. 8 , the electronic components inside the multiplexer 710 are substantially the same as the electronic components inside the multiplexer 510, which also includes a control transistor 712 and an electrical connection with the refresh signal supply unit 760. refresh transistor 714 .

Please refer to FIG. 5 , FIG. 7 and FIG. 8 at the same time. In this embodiment, the detection circuit layout 700 can be used to detect a single panel unit 502 . For example, if it is desired to detect the panel unit 502 located in the first row and the first column, the probes (not shown in the figure) are pressed to touch the detection pad 520 , the selection signal pad 530 , the detection pad 720 and The selection signal pad 730 is used to transmit the detection signals IS, IS′ and the selection signals SS, SS′ respectively from the external circuit to the detection circuit layout 700 through the probes.

Based on the above, the multiplexer 510 applies a voltage to the gate G1 of the control transistor 512 electrically connected to the first row of panel units 502 according to the selection signal SS, and then turns on the control transistor 512 . In this way, the detection signal IS can be transmitted from the detection pad 520 to the panel unit 502 in the first column through the drain D1, the source S1 of the control transistor 512 and the first signal line 504a in sequence. On the other hand, the multiplexer 710 applies a voltage to the gate G1' of the control transistor 712 electrically connected to the panel unit 502 in the first column according to the selection signal SS', and then turns on the control transistor 712. In this way, the detection signal IS' can be transmitted from the detection pad 720 to the panel unit 502 in the first row through the drain D1', the source S1' of the control transistor 712, and the second signal line 504b in sequence.

Here, since the first signal line 504a in this embodiment is a scanning line, after the detection signal IS is transmitted to the panel unit 502 in the first row, each pixel in the panel unit 502 in this row will be turned on. However, since this embodiment transmits the detection signal IS' to the panel unit 502 in the first column, only the panel unit 502 in the first row and the first column can display images according to the detection signal IS'. At this time, relevant personnel can judge whether it is a qualified product according to the picture displayed on the panel unit 502 .

As can be seen from the above, the detection circuit layout of the present invention utilizes a multiplexer to connect the panel units to be detected and the detection pads, so as to group or individually detect the panel units. Therefore, the detection of all panel units can be completed without moving the probe during the detection process.

In the manufacturing process of the liquid crystal display panel, if the detection circuit layout of the present invention is used in conjunction with the liquid crystal drop injection manufacturing process, the process time can be greatly shortened. The manufacturing process of this liquid crystal display panel will be described below.

9A to 9C are schematic top views of the manufacturing process of the liquid crystal display panel in an embodiment of the present invention. Referring to FIG. 9A , firstly, a liquid crystal layer 620 is formed on a first substrate 610 . Wherein, on the first substrate 610, for example, a plurality of active elements (not shown in the figure), pixel electrodes (not shown in the figure) and sealant 614 arranged in an array have been formed, and the sealant 614 is the first A substrate 610 surrounds a plurality of liquid crystal injection regions 616 . The liquid crystal layer 620 is formed in these liquid crystal injection regions 616 by means of drop injection.

Referring to FIG. 9B , a second substrate 630 is then provided and disposed above the first substrate 610 . Wherein, the second substrate 630 is, for example, a color filter. Afterwards, the second substrate 630 is assembled with the first substrate 610 so that the liquid crystal layer 620 is sealed between the first substrate 610 , the sealant 614 and the second substrate 630 to form multiple sets of panel units 502 . Moreover, the method of assembling the first substrate 610 and the second substrate 630 is, for example, to apply force to press the first substrate 610 and the second substrate 630 first, and then to cure the sealant 614, so that the first substrate 610 and the second substrate 630 are secure. bonded to each other. In this embodiment, the frame glue 614 may be heat-curable glue or ultraviolet light-curable glue. In other words, in this embodiment, for example, the sealant 614 is cured by heat curing or ultraviolet light curing.

After the panel unit 502 is formed, the detection circuit layout shown in FIG. 4 , FIG. 6 or FIG. 7 is then formed, and a lighting signal is input to the detection circuit layout, so as to perform lighting tests on these panel units 502 in groups. Wherein, during the lighting test process, the working conditions of each component of the detection circuit layout and the panel unit 502 are as described above, and will not be repeated here.

Referring to FIG. 9C, after the lighting test of all panel units 502 is completed, a cutting process can be performed to cut the assembled first substrate 610 and second substrate 630 of FIG. 9B into a plurality of liquid crystal display panels. 600 , and the subsequent manufacturing process of these liquid crystal display panels 600 is well known to those skilled in the art, and will not be repeated here.

In summary, the present invention has the following characteristics:

1. The detection circuit layout of the present invention uses a multiplexer to select a single or multiple panel units to be detected, so in the process of using the detection circuit layout of the present invention to detect panel units, it is not necessary to move the pressing contact The detection of all panel units can be completed by detecting the probes on the pads. Therefore, using the detection circuit layout of the present invention can effectively shorten the time spent in the detection process, thereby reducing the time cost. Moreover, if the detection circuit layout of the present invention is used, only one set of probes can be used in the detection process to complete the detection of all panel units. In other words, using the detection circuit layout of the present invention can save the cost of manufacturing probes.

2. In the process of using the detection circuit layout of the present invention to detect panel units, only the active components in the panel unit being detected are in the on state, and the active components in the other panel units can be in the off state. That is to say, the detection circuit layout of the present invention can be used to detect multiple panel units in groups, so as to shorten the time that the active elements in the panel units are in the on state, thereby prolonging the service life of the active elements.

3. In the manufacturing process of the liquid crystal display panel of the present invention, a lighting test is performed on a plurality of panel units before cutting, and then a cutting manufacturing process is performed to form a plurality of liquid crystal display panels. Compared with the conventional method of first cutting a large substrate into multiple display panels and then performing a lighting test, the present invention can simultaneously perform a lighting test on multiple panel units, thereby greatly shortening the time required for lighting the same batch of liquid crystal display panels. The time it takes to test.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (18)

1. A detection circuit layout, suitable for detecting at least one of a plurality of panel units, and each of the panel units has a plurality of first signal lines and a plurality of second signal lines, characterized in that the detection circuit layout includes : a first multiplexer, electrically connected to the above-mentioned first signal lines of the above-mentioned panel units; The first detection pad is electrically connected to the first multiplexer, wherein the first multiplexer is suitable for selectively combining the first detection pad with the above-mentioned first signals of a group of panel units wire conduction; and A plurality of first short-circuit bars electrically connected to the first multiplexer, and the above-mentioned first short-circuit bars are connected in series with at least a part of the first signal lines of a corresponding group of panel units; Wherein the first multiplexer includes a plurality of first control transistors, the drains of the first control transistors are respectively electrically connected to the first detection pad, and the sources of each of the first control transistors are respectively The first signal lines are electrically connected to the above-mentioned first signal lines of a corresponding group of panel units. 2. The detection circuit layout according to claim 1, characterized in that the first short-circuit bars include a plurality of first odd-number short-circuit bars and a plurality of first even-number short-circuit bars, and each of the first odd-number short-circuit bars is connected in series It corresponds to odd numbered first signal lines of a group of panel units, and each of the first even numbered shorting bars is connected in series with even numbered first signal lines of the group of panel units. 3. The detection circuit layout according to claim 1, further comprising a plurality of electrostatic discharge protection components electrically connected between the corresponding first shorting bars and part of the first signal lines of the group of panel units respectively . 4. The detection circuit layout according to claim 1, further comprising a first refresh signal supply unit electrically connected to the first multiplexer. 5. The detection circuit layout according to claim 4, wherein the first multiplexer further comprises a plurality of first refresh transistors, and the sources of each of the first refresh transistors are electrically connected to the corresponding Between the source of the first control transistor and the first signal lines, the drains of the first refresh transistors are respectively electrically connected to the refresh signal supply unit. 6. The detection circuit layout according to claim 1, further comprising: A second multiplexer electrically connected to the second signal lines of the panel units; and The second detection pad is electrically connected to the second multiplexer, wherein the second multiplexer is suitable for selectively combining the second detection pad with the above-mentioned second signals of a group of panel units The line conducts. 7. The detection circuit layout according to claim 6, further comprising a plurality of second short-circuit bars electrically connected to the second multiplexer, and the above-mentioned second short-circuit bars are respectively connected in series Corresponding to at least a part of the second signal wires of a group of panel units. 8. The detection circuit layout according to claim 7, wherein the second short-circuit bars include a plurality of second odd-number short-circuit bars and a plurality of second even-number short-circuit bars, and each of the second odd-number short-circuit bars is connected in series It corresponds to odd numbered second signal lines of a group of panel units, and each of the second even numbered shorting bars is connected in series with even numbered second signal lines of the group of panel units. 9 . The detection circuit layout according to claim 7 , further comprising a plurality of electrostatic discharge protection components electrically connected between the corresponding second shorting bars and part of the second signal lines of the group of panel units. 10. The detection circuit layout according to claim 6, wherein the second multiplexer comprises a plurality of second control transistors, and the drains of the second control transistors are electrically connected to the second detection circuit respectively. pads, and the sources of the second control transistors are respectively electrically connected to the above-mentioned second signal lines of a corresponding group of panel units. 11. The detection circuit layout according to claim 10, further comprising a second refresh signal supply unit electrically connected to the second multiplexer. 12. The detection circuit layout according to claim 11, wherein the second multiplexer further comprises a plurality of second refresh transistors, and the source of each second refresh transistor is electrically connected to the corresponding Between the source of the second control transistor and the above-mentioned second signal lines, and the drains of the above-mentioned second refresh transistors are respectively electrically connected to the refresh signal supply unit. 13. The detection circuit layout according to claim 1, wherein the first signal lines are scan lines, and the second signal lines are data lines. 14. A method for manufacturing a liquid crystal display panel, characterized by comprising: forming a liquid crystal layer on the first substrate; providing a second substrate disposed above the first substrate; Assembling the first substrate and the second substrate so that the liquid crystal layer is sealed between the first substrate and the second substrate to form multiple sets of panel units; forming the detection circuit layout of claim 1; input lighting signals to the detection circuit layout, so as to perform lighting tests on the above-mentioned panel units; and The assembled first substrate and the second substrate are cut to form a plurality of liquid crystal display panels. 15. The method for manufacturing a liquid crystal display panel according to claim 14, wherein the method for forming the liquid crystal layer includes drop injection. 16. The method for manufacturing a liquid crystal display panel according to claim 14, further comprising forming a sealant on the first substrate before forming the liquid crystal layer, so as to enclose a plurality of liquid crystals on the first substrate injection regions, and the subsequently formed liquid crystal layer is located in these liquid crystal injection regions. 17. The method of manufacturing a liquid crystal display panel according to claim 16, wherein the method for assembling the first substrate and the second substrate comprises: pressing the first substrate and the second substrate; and Curing the sealant. 18 . The method for manufacturing a liquid crystal display panel according to claim 17 , wherein the method of curing the sealant includes thermal curing or ultraviolet curing.

Images