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CN100492906C - D flip-flop with reset and/or set function based on conditional precharge structure - Google Patents

D flip-flop with reset and/or set function based on conditional precharge structure Download PDF

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Publication number
CN100492906C
CN100492906C CNB2005100119365A CN200510011936A CN100492906C CN 100492906 C CN100492906 C CN 100492906C CN B2005100119365 A CNB2005100119365 A CN B2005100119365A CN 200510011936 A CN200510011936 A CN 200510011936A CN 100492906 C CN100492906 C CN 100492906C
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transistor
gate
tube
source
nmos transistor
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CN1697319A (en
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杨华中
魏鼎力
乔飞
汪蕙
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Tsinghua University
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Tsinghua University
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Abstract

Characters of the invention are as following: besides structure of sensitive amplifier is adopted in latch in first stage, pull-up and pull-down are carried out for two complemental output ends by using two pieces of P tubes and two pieces of N tubes at power source end and complemental output ends respectively. Control signals pulled-up and pulled-down are set and reset signals. Two pieces of phase latches in single clock with identical circuit parameter are adopted in latch in second stage. Potential retention unit structured from two inverters connected at headers is added between output ends of two pieces of phase latches. Comparing prior art, the invention saves energy 20% under same testing condition. Moreover, the invention possesses features of simple structure, small area of circuit, good characteristics of circuit time delay, setup time and metastable state time.

Description

Band resets and/or set function and based on the d type flip flop of condition presetting construction
Technical field
Band reset-set function is based on the low-power consumption flip-flop circuit design with reset-set function of condition presetting construction based on the direct applied technical field of the d type flip flop of condition presetting construction.The circuit that proposes is that a class is applicable to low amplitude of oscillation clock signal networks technology and Low-Power CMOS flip-flop circuit unit that need the reset-set end.
Background technology
Along with the progress of CMOS integrated circuit fabrication process, the scale and the complexity of integrated circuit increase day by day, and power consumption of integrated circuit and heat dissipation problem more and more obtain the attention from industrial quarters and academia.Based on present integrated circuit (IC) design style, in the large scale digital Circuits System, the ratio that the energy of clock network consumption accounts for the total power consumption of entire circuit remains high always; Wherein, under the circuit working state, (trigger: energy Flip-Flop) becomes the important source of clock network energy consumption again in clock interconnection gauze and sequence circuit unit in consumption, and the power consumption ratio of the two has ever-increasing trend (to see document David E.Duarte, N.Vjjaykrishnan, and Mary Jane Irwin, " A Clock Power Model to Evaluate Impact of Architecturaland Technology Optimizations ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.10, no.6, pp.844-855, December 2002.).
Simultaneously in the design of large scale integrated circuit, commonly used to the trigger that has the asynchronous reset set function, set makes output Q high level exactly and Qb should be low level mutually; Reset is exactly to make output Q low level and Qb should be high level mutually; Asynchronous reset set just no matter the edge of clock whether arrive, when reset terminal RN is low level, circuit reset; When set end SN is low level, circuit set.When reset terminal and set end were low level simultaneously, SN worked, circuit set.After SN or RN were inoperative, circuit state overturn with clock.This class trigger usually runs in asynchronous sequential circuit, and its power consumption and delay performance receive publicity further in integrated circuit fields.
CMOS power consumption of integrated circuit source mainly contains dynamic power consumption, quiescent dissipation, short circuit current power consumption and leakage current power consumption.Wherein dynamic power consumption accounts for major part.Under certain circuit performance constraint, the dynamic power consumption P of CMOS integrated circuit node DynamicIt is this node load capacitor C L, supply voltage V DDVoltage swing V with this node SwingFunction, that is:
P Dynamic＝C LV DDV Swingfα (1)
Wherein, f is the operating frequency of circuit, and α is the signal activity.From formula (1), as seen, reduce α, C L, V DDAnd V SwingAll can reduce the dynamic power consumption of circuit.Be different from the data-signal gauze, the clock cable netting gear has the characteristics of big interconnection line parasitic capacitance and high signal activity, by reducing the voltage signal amplitude of oscillation V of clock signal gauze SwingCan be at the energy that guarantees to reduce under the condition of circuit performance to consume on the clock interconnection line.The flip-flop circuit unit is widely used in integrated circuit (IC) design, wherein also is no lack of the use of the flip-flop circuit of band set-reset.Be band R-S flip-flop circuit unit schematic diagram as shown in Figure 1.Be illustrated in figure 2 as the flip-flop circuit unit basic circuit structure that is widely used in the traditional band reset-set end in the digital circuit standard cell lib design, wherein the A module realize z=! The b logic function. here with complementary output in the Verisilicon 0.15 μ m technology digital standard cell library, the flip-flop circuit unit F FDSRHD1X that rising edge triggers is that the example explanation (is seen document " SPICE Model of 0.15umGeneric (1.5V/3.3V) 1P7M Process " Document number:GSMC_L015S7G0_SPI_V1.3; " VeriSilicon GSMC 0.15 μ m High-Density Standard Cell Library Databook ").The main feature of sort circuit structure is that circuit structure is fairly simple, its set-reset signal adds by transforming inverter, independently be not difficult to utilization in the inverter structure, and be not suitable for the design of low-clock signal excursion clock network system, because clock signal upset each time all can cause the upset of circuit internal clocking buffer, circuit power consumption is bigger simultaneously.H.Kawaguchi propose a kind of flip-flop circuit RCSFF that can adopt low-voltage amplitude of oscillation clock signal to drive (see document H.Kawaguchi and T.Sakurai: " AReduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction " ', IEEE JOURNAL OFSOLID-STATE CIRCUITS, VOL.33, NO.5, MAY 1998, PP.807-811.), but the problem of sort circuit is when clock signal low level each time, extra energy consumption can be caused to the precharge of circuit internal node in the capital.On the basis of RCSFF circuit, the flip-flop circuit SAFF_CP that Y.Zhang proposes a kind of low-voltage amplitude of oscillation clock signal driving of condition presetting construction (sees document Y.Zhang, H.Yang, and H.Wang, " Low clock-swing conditional-prechargeflip-flop for more than 30% power reduction; " Electron.Lett., vol.36, no.9, pp.785-786, Apr.2000.), as shown in Figure 3.The maximum characteristics of this flip-flop circuit are can be operated under the low-voltage oscillation amplitude driving conditional except keeping; Simultaneously, if the flip-flop circuit input remains unchanged when the clock signal low level, circuit can be to its internal node precharge between the clock signal low period.The employing of this technology greatly reduces the power consumption of flip-flop circuit itself.But, the problem that the SAFF_CP circuit exists is, because the output latch circuit has adopted cross-couplings NAND2 (NAND2: two input NAND gate) structure, can cause time-delay of flip-flop circuit output rising edge and trailing edge time-delay extremely asymmetric, bring potential problem for the use of circuit unit.
For flip flop design based on the band set-reset function of SAFF structure, Vojin G.Oklobdziia mentions a kind of structure (document " CIRCUIT IMPLEMENTATION TECHNIQUES FOR THEMAGNETIC READ/WRITE CHANNELS " Final Report 1998-99 for MICRO Project 98-112) that has scan function end and asynchronous reset end, as shown in Figure 4.This structural circuit more complicated, only provided the way that the first order resets, do not consider the priority design when reset-set occurs simultaneously, lack design different second level reset-sets, can not simple application in SAFF_CP trigger structure shown in Figure 3.
Summary of the invention
The objective of the invention is on the flip-flop circuit that the low-voltage amplitude of oscillation clock signal of existing condition presetting construction drives is the basis of SAFF_CP circuit, to make certain improvement, propose a kind of trigger structure that has asynchronous set reset function end based on condition presetting construction.Two complementary output end signal upset time-delay is symmetry comparatively, and static time-delay has some improvement, and compares traditional digital standard unit and can save power consumption more than 20%, and set-reset speed is very fast, and the priority of set is higher than and resets, as shown in Figure 6.
The invention is characterized in: described d type flip flop contains:
First order latch, this latch contains:
The 1st " or " logical circuit, contain 1NMOS pipe and 2NMOS pipe that its substrate interconnects back ground connection, be designated as MN1 pipe and MN2 pipe respectively, the source electrode of described 1NMOS pipe connects clock signal clk, and grid meets the 2nd intermediate data signal DB; The source electrode of described 2NMOS pipe and grid all meet the 1st input data signal D, and the 1st input data signal D and described the 2nd intermediate data signal DB are anti-phase;
The 2nd " or " logical circuit, contain 3NMOS pipe and 4NMOS pipe that its substrate interconnects back ground connection, be designated as MN3 pipe and MN4 pipe respectively, the source electrode of described 3NMOS pipe connects clock signal clk, and grid meets described the 1st input data signal D; The source electrode of described 4NMOS pipe and grid all meet the 2nd intermediate data signal DB;
The 1st PMOS pipe is designated as the MP1 pipe, and the grid of this pipe links to each other with the drain electrode of 2NMOS pipe with described 1NMOS pipe simultaneously, and substrate meets supply voltage V DD
The 4th PMOS pipe is designated as the MP4 pipe, and the grid of this pipe links to each other with the drain electrode of 4NMOS pipe with described 3NMOS pipe simultaneously, and substrate meets supply voltage V DD
The 5th PMOS pipe is designated as the MP15 pipe, and the drain electrode of this pipe links to each other with the source electrode of described 1PMOS pipe simultaneously, and grid meets the centre anti-phase set control signal S that input asserts signal SN forms behind inverter, and the substrate of this pipe and source electrode meet supply voltage V DD
The 6th PMOS pipe, be designated as the MP16 pipe, the drain electrode of this pipe links to each other with the source electrode of described 4PMOS pipe simultaneously, and grid meets middle inverted reset control signal R, this centre inverted reset control signal R is obtained after NOR gate by centre anti-phase set control signal S and input reset signal RN, and the substrate of described 6PMOS pipe and source electrode meet supply voltage V DD
The 3rd PMOS pipe is designated as the MP3 pipe, the described supply voltage V that the substrate of this pipe is connected with source electrode DD
The 2nd PMOS pipe is designated as the MP2 pipe, the described supply voltage V that the substrate of this pipe is connected with source electrode DD
The 5th NMOS pipe is designated as the MN5 pipe, and the source electrode of this pipe is connected to described 1PMOS pipe, the drain electrode of 3PMOS pipe and the grid of 2PMOS pipe simultaneously, constitutes the 3rd intermediate node SALATCH_N; The substrate ground connection of this 5NMOS pipe;
The 6th NMOS pipe, be designated as the MN6 pipe, grid and the described 2PMOS that the source electrode of this pipe is connected to described 3PMOS pipe, 5NMOS pipe simultaneously manages, the drain electrode of 4PMOS pipe, form the 4th intermediate node SALATCH_P, the grid of this 6NMOS pipe meets the 3rd intermediate node SALATCH_N, and substrate ground connection;
The 10th NMOS pipe is designated as the MN17 pipe, and the source electrode of this pipe meets described the 4th intermediate node SALATCH_P, and inverted reset control signal R in the middle of grid connects, substrate are then the back ground connection that links to each other with drain electrode;
The 11st NMOS pipe is designated as the MN18 pipe, and the source electrode of this pipe meets described the 3rd intermediate node SALATCH_N, and anti-phase set control signal S in the middle of grid connects, substrate are then the back ground connection that links to each other with drain electrode;
The 7th NMOS pipe is designated as the MN7 pipe, and the drain electrode of this pipe links to each other with the drain electrode of described 5NMOS pipe, and substrate ground connection;
The 8th NMOS pipe is designated as the MN8 pipe, and the drain electrode of this pipe links to each other with the drain electrode of described 6NMOS pipe, and substrate ground connection;
An inverter is designated as XIVG1, the input of this inverter with meet described the 1st input data signal D after described 7NMOS tube grid links to each other, and the output of this inverter provides the 2nd intermediate data signal DB for the grid of described 8NMOS pipe;
The 9th NMOS pipe is designated as the MN9 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 7NMOS pipe, 8NMOS pipe simultaneously, and grid connects clock signal clk, and substrate ground connection;
Second level latch, this latch is made of two single clock phase latch with identical electrical parameter, and described second level latch contains:
The 1st single clock phase latch, contain:
111PMOS pipe is designated as the XOUT1.MI pipe, the source electrode of this pipe with meet supply voltage V after substrate links to each other DD, and grid meets described the 4th intermediate node SALATCH_P;
The 112NMOS pipe is designated as the XOUT1.M2 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 111PMOS pipe, and grid meets described the 4th intermediate node SALATCH_P;
The 113NMOS pipe is designated as the XOUT1.M3 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 112NMOS pipe, and grid connects clock signal clk;
The 28NMOS pipe is designated as the MN28 pipe, anti-phase set control signal S in the middle of the grid of this pipe connects, and substrate ground connection after the substrate with described 112NMOS pipe, 113NMOS pipe links to each other, the grounded drain of this pipe;
The 2nd single clock phase latch, contain:
121PMOS pipe is designated as the XOUT2.M1 pipe, the source electrode of this pipe with meet supply voltage V after substrate links to each other DD, and grid meets described the 3rd intermediate node SALATCH_N;
The 122NMOS pipe is designated as the XOUT2.M2 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 121PMOS pipe, and grid meets described the 3rd intermediate node SALATCH_N;
The 123NMOS pipe is designated as the XOUT1.M3 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 122NMOS pipe, and grid connects clock signal clk;
The 27NMOS pipe is designated as the MN27 pipe, inverted reset control signal R in the middle of the grid of this pipe connects, and substrate ground connection after the substrate with described 122NMOS pipe, 123NMOS pipe links to each other, the grounded drain of this pipe;
The current potential holding unit, contain the 4th inverter and the 5th inverter, be designated as XIVG4 and XIVG5 respectively, the input of described the 4th inverter XIVG4 connects the drain electrode of described 111PMOS pipe and the source electrode of 28NMOS pipe after the output with the 5th inverter XIVG5 links to each other, form the 5th intermediate node QI; The output of described the 4th inverter XIVG4 connects the drain electrode of described 121PMOS pipe and the source electrode of 27NMOS pipe after the input with the 5th inverter XIVG5 links to each other, form the 6th intermediate node QNI;
The 2nd output inverter and the 3rd output inverter are designated as XIVG2 and XIVG3 respectively, and the input of described the 3rd inverter XIVG3 links to each other with described the 6th intermediate node QNI, and output is the 2nd output signal Qb; The input of described the 2nd inverter XIVG2 links to each other with described the 5th intermediate node QI, and output is the 1st output signal Q.
A kind of with set function and based on the d type flip flop of condition presetting construction, it is characterized in that described d type flip flop contains:
First order latch, this latch contains:
The 1st " or " logical circuit, contain 1NMOS pipe and 2NMOS pipe that its substrate interconnects back ground connection, be designated as MN1 pipe and MN2 pipe respectively, the source electrode of described 1NMOS pipe connects clock signal clk, and grid meets the 2nd intermediate data signal DB; The source electrode of described 2NMOS pipe and grid all meet the 1st input data signal D, and the 1st input data signal D and described the 2nd intermediate data signal DB are anti-phase;
The 2nd " or " logical circuit, contain 3NMOS pipe and 4NMOS pipe that its substrate interconnects back ground connection, be designated as MN3 pipe and MN4 pipe respectively, the source electrode of described 3NMOS pipe connects clock signal clk, and grid meets described the 1st input data signal D; The source electrode of described 4NMOS pipe and grid all meet the 2nd intermediate data signal DB;
The 1st PMOS pipe is designated as the MP1 pipe, and the grid of this pipe links to each other with the drain electrode of 2NMOS pipe with described 1NMOS pipe simultaneously, and substrate meets supply voltage V DD
The 4th PMOS pipe is designated as the MP4 pipe, and the grid of this pipe links to each other with the drain electrode of 4NMOS pipe with described 3NMOS pipe simultaneously, and substrate meets supply voltage V DD
The 5th PMOS pipe is designated as the MP15 pipe, and the drain electrode of this pipe links to each other with the source electrode of described 1NMOS pipe simultaneously, and grid meets the centre anti-phase set control signal S that input asserts signal SN forms behind inverter, and the substrate of this pipe and source electrode meet supply voltage V DD
The 3rd PMOS pipe is designated as the MP3 pipe, the described supply voltage V that the substrate of this pipe is connected with source electrode DD
The 2nd PMOS pipe is designated as the MP2 pipe, the described supply voltage V that the substrate of this pipe is connected with source electrode DD
The 5th NMOS pipe is designated as the MN5 pipe, and the source electrode of this pipe is connected to described 1PMOS pipe, the drain electrode of 3PMOS pipe and the grid of 2PMOS pipe simultaneously, constitutes the 3rd intermediate node SALATCH_N; The substrate ground connection of this 5NMOS pipe;
The 6th NMOS pipe, be designated as the MN6 pipe, grid and the described 2PMOS that the source electrode of this pipe is connected to described 3PMOS pipe, 5NMOS pipe simultaneously manages, the drain electrode of 4PMOS pipe, form the 4th intermediate node SALATCH_P, the grid of this 6NMOS pipe meets the 3rd intermediate node SALATCH_N, and substrate ground connection;
The 18NMOS pipe that drop-down the 3rd intermediate node SALATCH_N uses is designated as the MN18 pipe, and the source electrode of this pipe meets described the 3rd intermediate node SALATCH_N, and anti-phase set control signal S in the middle of grid connects, substrate are then the back ground connection that links to each other with drain electrode;
On draw the 18PMOS pipe that the 4th intermediate node SALATCH_P uses, be designated as the MP18 pipe, the source electrode of this pipe meets described the 4th intermediate node SALATCH_P, grid meets input asserts signal SN, substrate then with described supply voltage VDD after drain electrode links to each other;
The 7th NMOS pipe is designated as the MN7 pipe, and the drain electrode of this pipe links to each other with the drain electrode of described 5NMOS pipe, and substrate ground connection;
The 8th NMOS pipe is designated as the MN8 pipe, and the drain electrode of this pipe links to each other with the drain electrode of described 6NMOS pipe, and substrate ground connection;
An inverter is designated as XIVG1, the input of this inverter with meet described the 1st input data signal D after described 7NMOS tube grid links to each other, and the output of this inverter provides the 2nd intermediate data signal DB for the grid of described 8NMOS pipe;
The 9th NMOS pipe is designated as the MN9 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 7NMOS pipe, 8NMOS pipe simultaneously, and grid connects clock signal clk, and substrate ground connection;
Second level latch, this latch is made of two single clock phase latch with identical electrical parameter, and described second level latch contains:
The 1st single clock phase latch, contain:
111PMOS pipe is designated as the XOUT1.M1 pipe, the source electrode of this pipe with meet supply voltage V after substrate links to each other DD, and grid meets described the 4th intermediate node SALATCH_P;
The 112NMOS pipe is designated as the XOUT1.M2 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 111PMOS pipe, and grid meets described the 4th intermediate node SALATCH_P;
The 113NMOS pipe is designated as the XOUT1.M3 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 112NMOS pipe, and grid connects clock signal clk;
The 28NMOS pipe is designated as the MN28 pipe, anti-phase set control signal (S) in the middle of the grid of this pipe connects, and substrate ground connection after the substrate with described 112NMOS pipe, 113NMOS pipe links to each other, the grounded drain of this pipe;
The 2nd single clock phase latch, contain:
121PMOS pipe is designated as the XOUT2.M1 pipe, the source electrode of this pipe with meet supply voltage V after substrate links to each other DD, and grid meets described the 3rd intermediate node SALATCH_N;
The 122NMOS pipe is designated as the XOUT2.M2 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 121PMOS pipe, and grid meets described the 3rd intermediate node SALATCH_N, this pipe substrate ground connection;
The 123NMOS pipe is designated as the XOUT1.M3 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 122NMOS pipe, and grid connects clock signal clk, this pipe substrate ground connection;
The current potential holding unit, contain the 4th inverter and the 5th inverter, be designated as XIVG4 and XIVG5 respectively, the input of described the 4th inverter XIVG4 connects the drain electrode of described 111PMOS pipe and the source electrode of 28NMOS pipe after the output with the 5th inverter XIVG5 links to each other, form the 5th intermediate node QI; The output of described the 4th inverter XIVG4 connects the drain electrode of described 121PMOS pipe after the input with the 5th inverter XIVG5 links to each other, form the 6th intermediate node QNI;
The 2nd output inverter and the 3rd output inverter are designated as XIVG2 and XIVG3 respectively, and the input of described the 3rd inverter XIVG3 links to each other with described the 6th intermediate node QNI, and output is the 2nd output signal Qb; The input of described the 2nd inverter XIVG2 links to each other with described the 5th intermediate node QI, and output is the 1st output signal Q.
A kind of with reset function and based on the d type flip flop of condition presetting construction, it is characterized in that described d type flip flop contains:
First order latch, this latch contains:
The 1st " or " logical circuit, contain 1NMOS pipe and 2NMOS pipe that its substrate interconnects back ground connection, be designated as MN1 pipe and MN2 pipe respectively, the source electrode of described 1NMOS pipe connects clock signal clk, and grid meets the 2nd intermediate data signal DB; The source electrode of described 2NMOS pipe and grid all meet the 1st input data signal D, and the 1st input data signal D and described the 2nd intermediate data signal DB are anti-phase;
The 2nd " or " logical circuit, contain 3NMOS pipe and 4NMOS pipe that its substrate interconnects back ground connection, be designated as MN3 pipe and MN4 pipe respectively, the source electrode of described 3NMOS pipe connects clock signal clk, and grid meets described the 1st input data signal D; The source electrode of described 4NMOS pipe and grid all meet the 2nd intermediate data signal DB;
The 1st PMOS pipe is designated as the MP1 pipe, and the grid of this pipe links to each other with the drain electrode of 2NMOS pipe with described 1NMOS pipe simultaneously, and substrate meets supply voltage V DD
The 4th PMOS pipe is designated as the MP4 pipe, and the grid of this pipe links to each other with the drain electrode of 4NMOS pipe with described 3NMOS pipe simultaneously, and substrate meets supply voltage V DD
The 6th PMOS pipe is designated as the MP16 pipe, and the drain electrode of this pipe links to each other with the source electrode of described 4NMOS pipe simultaneously, and grid meets the middle inverted reset control signal R that input reset signal RN forms behind inverter, and the substrate of this pipe and source electrode meet supply voltage V DD
The 3rd PMOS pipe is designated as the MP3 pipe, the described supply voltage V that the substrate of this pipe is connected with source electrode DD
The 2nd PMOS pipe is designated as the MP2 pipe, the described supply voltage V that the substrate of this pipe is connected with source electrode DD
The 5th NMOS pipe is designated as the MN5 pipe, and the source electrode of this pipe is connected to described 1PMOS pipe, the drain electrode of 3PMOS pipe and the grid of 2PMOS pipe simultaneously, constitutes the 3rd intermediate node SALATCH_N; The substrate ground connection of this 5NMOS pipe;
The 6th NMOS pipe, be designated as the MN6 pipe, grid and the described 2PMOS that the source electrode of this pipe is connected to described 3PMOS pipe, 5NMOS pipe simultaneously manages, the drain electrode of 4PMOS pipe, form the 4th intermediate node SALATCH_P, the grid of this 6NMOS pipe meets the 3rd intermediate node SALATCH_N, and substrate ground connection;
The 17NMOS pipe that drop-down the 4th intermediate node SALATCH_P uses is designated as the MN17 pipe, and the source electrode of this pipe meets described the 4th intermediate node SALATCH_P, and inverted reset control signal R in the middle of grid connects, substrate are then the back ground connection that links to each other with drain electrode;
On draw the 17PMOS pipe that the 3rd intermediate node SALATCH_N uses, be designated as the MP17 pipe, the source electrode of this pipe meets described the 3rd intermediate node SALATCH_N, grid meets input reset signal RN, substrate then with described supply voltage V after drain electrode links to each other DD
The 7th NMOS pipe is designated as the MN7 pipe, and the drain electrode of this pipe links to each other with the drain electrode of described 5NMOS pipe, and substrate ground connection;
The 8th NMOS pipe is designated as the MN8 pipe, and the drain electrode of this pipe links to each other with the drain electrode of described 6NMOS pipe, and substrate ground connection;
An inverter is designated as XIVG1, the input of this inverter with meet described the 1st input data signal D after described 7NMOS tube grid links to each other, and the output of this inverter provides the 2nd intermediate data signal DB for the grid of described 8NMOS pipe;
The 9th NMOS pipe is designated as the MN9 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 7NMOS pipe, 8NMOS pipe simultaneously, and grid connects clock signal clk, and substrate ground connection;
Second level latch, this latch is made of two single clock phase latch with identical electrical parameter, and described second level latch contains:
The 1st single clock phase latch, contain:
111PMOS pipe is designated as the XOUT1.M1 pipe, the source electrode of this pipe with meet supply voltage V after substrate links to each other DD, and grid meets described the 4th intermediate node SALATCH_P;
The 112NMOS pipe is designated as the XOUT1.M2 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 111PMOS pipe, and grid meets described the 4th intermediate node SALATCH_P;
The 113NMOS pipe is designated as the XOUT1.M3 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 112NMOS pipe, and grid connects clock signal clk;
The 2nd single clock phase latch, contain:
121PMOS pipe is designated as the XOUT2.M1 pipe, the source electrode of this pipe with meet supply voltage V after substrate links to each other DD, and grid meets described the 3rd intermediate node SALATCH_N;
The 122NMOS pipe is designated as the XOUT2.M2 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 121PMOS pipe, and grid meets described the 3rd intermediate node SALATCH_N;
The 123NMOS pipe is designated as the XOUT1.M3 pipe, and the source electrode of this pipe links to each other with the drain electrode of described 122NMOS pipe, and grid connects clock signal clk;
The 27NMOS pipe is designated as the MN27 pipe, inverted reset control signal R in the middle of the grid of this pipe connects, and substrate ground connection after the substrate with described 122NMOS pipe, 123NMOS pipe links to each other, the grounded drain of this pipe;
The current potential holding unit, contain the 4th inverter and the 5th inverter, be designated as XIVG4 and XIVG5 respectively, the input of described the 4th inverter XIVG4 connects the drain electrode of described 111PMOS pipe after the output with the 5th inverter XIVG5 links to each other, and forms the 5th intermediate node QI; The output of described the 4th inverter XIVG4 connects the drain electrode of described 121PMOS pipe and the source electrode of 27NMOS pipe after the input with the 5th inverter XIVG5 links to each other, form the 6th intermediate node QNI;
The 2nd output inverter and the 3rd output inverter are designated as XIVG2 and XIVG3 respectively, and the input of described the 3rd inverter XIVG3 links to each other with described the 6th intermediate node QNI, and output is the 2nd output signal Qb; The input of described the 2nd inverter XIVG2 links to each other with described the 5th intermediate node QI, and output is the 1st output signal Q.
The invention has the beneficial effects as follows: with traditional digital standard unit triggers device circuit FFDSRHD1X relatively, the FFDSRHD1X_SCB_FCS trigger that the present invention proposes can be saved and is higher than 20% power consumption under identical test condition.And the structure of circuit obtains simplifying, and circuit area is less, the circuit delay characteristic, and settling time and metastable state time response are also better.The circuit engineering that is proposed is suitable as the digital circuit standard cell and is applied in the low power consumption integrated circuit design very much.
Description of drawings
Fig. 1. the flip-flop circuit cell schematics, D is the data-signal input, and CLK is a clock signal input terminal, and Q and Qb are the complementary signal output;
The flip-flop circuit unit F FDSRHD1X circuit structure diagram that complementary output and rising edge trigger in Fig. 2 .VeriSilicon 0.15um technology digital standard cell library;
Fig. 3 .SAFF_CP flip-flop circuit structure chart;
Fig. 4. have the circuit structure diagram of scanning test function end and asynchronous reset functionality end in the time of based on the SAFF structure;
Fig. 5. asynchronous set reset flip-flop circuit structure diagram of the present invention.
Fig. 6. FFDSRHD1X_SCB_FCS flip-flop circuit structure chart of the present invention.
Fig. 7. only with the FFDSHD1X_SCB_FCS flip-flop circuit structure chart of asynchronous set end.
Fig. 8. only with the FFDRHD1X_SCB_FCS flip-flop circuit structure chart of asynchronous reset end.
Embodiment
The technical scheme that the present invention solves its technical problem is: the present invention proposes the band reset-set end trigger FFDSRHD1X_SCB_FCS based on condition presetting construction, as shown in Figure 6.Circuit shown in Figure 5 is the blank of Fig. 6.The FFDSRHD1X_SCB_FCS trigger has the advantages that to adopt the condition presetting technology to reduce the power consumption of flip-flop circuit own, has simultaneously and can carry out set, the function that resets.Basic structure is a condition presetting trigger among Fig. 5, its operation principle is as follows: at first use four metal-oxide-semiconductors to the CLK signal, the D signal carries out preliminary treatment, mainly be CLK " or (OR) " D, CLK " or (OR) " DB, again these two signals are added to the grid that draws driving tube on two, first order latch are carried out preliminary filling by them; First order latch center is by MP2, MP3, and MN5, MN6 constitutes sensitive amplifier structure.There is positive feedback in this structure, is again a kind of difference input structure, complementary input, and existing very strong noise robustness can improve the sensitivity to input signal again, and its bistable characteristic is convenient to preserve data simultaneously.The complementary output end of first order latch is connected respectively to two independently and have on the single clock phase latch of same circuits parameter, three step responses for fear of single clock phase latch output node QI, QNI, between QI and QNI, added holder, it is made of two end to end inverters, even when CLK was static low level, partial current potential also can be determined and be maintained.Even there is leakage current the second level like this, also can not have influence on the change of circuit state.
When CLK is high level, two driving tube grids of the first order all are high potentials, the P pipe ends, the D signal can't change the state of node SALATCH_P, SALATCH_N, when CLK is low level, D and DB are added to two driving tube grids, at this moment overturn as if the D signal, will be to node SALATCH_P, SALATCH_N carries out preliminary filling, original node SALATCH_P, SALATCH_N should be one high and one low, but since this moment the MN9 pipe under clock control, block, the first order can't be discharged, so two node SALATCH_P, SALATCH_N is filled into high potential.At this moment partial discharge loop also disconnects, so two high states of the first order can not have influence on the state of second level holder, circuit output still keeps.This moment, preliminary filling was finished.Next interim when the clock rising edge, the MN9 pipe is opened, circuit discharging node SALATCH_P, and SALATCH_N translates into correct current potential.Also opened owing to second level discharge loop simultaneously, SALATCH_P, SALATCH_N drives QI, and the d type flip flop function is finished in the QNI upset one time.When the D signal remains unchanged, though clock along arrival, can be to SALATCH_P yet, SALATCH_N two nodes carry out precharge, internal node can not carry out unnecessary upset with the clock signal, thereby has reduced power consumption.
The adding of aaset bit reset signal, as shown in Figure 5.In the first order latch of circuit, with two P pipes, two N pipes draw with drop-down on SALATCH_N carries out SALATCH_P respectively.The control signal of these pipes is respectively S, R, RN, SN, and wherein S is that input signal SN obtains through inverter, and R then is the nondisjunction of RN and S.This mainly is owing to when set, reset signal arrive simultaneously, circuit set.Have only as asserts signal SN inoperative (high level), and Rn is when being low level that above-mentioned R is only high level, thereby drives the SALATCH_P discharge.Notice simultaneously by RN drive on to draw the drain electrode of P pipe be not directly to meet VDD, but influenced by S, only when S is low level, draw on this to be only success.The priority that such design has not only embodied set, resetted, and avoided above-mentioned four pipes formation DC channel to cause excessive power consumption.Yet design and imperfect must consider that in set when resetting input signal is blocked, not so two-phase conflict will cause big electric current like this.Specific practice is exactly to drive P pipes (MP1, MP4) top at two of the first order respectively to be connected in series a P pipe, by S and R control, assurance set, when resetting driving is blocked.Utilize the characteristics of this circuit, only need block the MP1 branch road during set, only need block the MP4 branch road when resetting, and then simplify logic control.For second level circuit, utilize the structure of itself, when the set of the first order, reset finish after, can realize drawing to node QI or QNI easily, therefore only need on node QI and QNI, add simply two drop-down N pipes, get final product by S, R control.So just obtain shown in Figure 5 resetting, the processing of set.
Further analyze, after two driving tubes of the first order (MP1, MP4) branch road blocks, utilize MP2, MP3, MN5, MN6 constitutes sense amplifier, and a need carry out drop-down to one of SALATCH_P or SALATCH_N, and another node is translated into high potential naturally.Therefore can remove MP17 among Fig. 5, MP18 two pipes, obtain the structure of Fig. 6.Certainly the second level fully also can utilize the positive feedback effect of holder and needn't manage drop-downly with N, but set like this, reset speed are slowly and stable inadequately, so do not adopt.When SN, RN were high level, all these additional pipes were all inoperative, and circuit is as the d type flip flop operate as normal.
Also there is the metastable state effect for flip-flop circuit, when input data signal D when saltus step takes place very nearby in the distance rising edge clock signal, can cause that the time-delay from clock signal clk to output Q or Qb increases greatly, the settling time of definition flip-flop circuit and the time-delay sum of increase are the metastable state time, and the time-delay sum of circuit is total time-delay of circuit under metastable state time and the general situation.For general SAFF_CP flip-flop circuit, characteristic settling time of circuit is subjected to the restriction of first order latch precharge time.And removed the NMOS pipe that is connected in the SAFF_CP circuit between MN2 and the MN3 in the FFDSRHD1X_SCB_FCS trigger, precharge load capacitance greatly reduces, and charging process is finished in assurance than faster.Simulation result by circuit can find that the trigger FFDSRHD1X_SCB_FCS that the present invention proposes has more superior settling time and metastable state time performance.
Essential features of the present invention is: at first, the condition presetting control circuit that the flip-flop circuit employing is controlled by input data signal D is finished the condition presetting process to the circuit internal node, has reduced the power consumption of trigger itself.The condition presetting process of first order latch cooperates second level latch, guarantees that circuit is a low level and during not to node precharge at CLK, and the complementary output end of trigger is can the inhibit signal level constant.The output node of first order latch is connected respectively to two independently and have on the single clock phase latch of same circuits parameter, and this method of attachment can guarantee the complementary output end Q and the Q of FFDSRHD1X_SCB_FCS trigger bCan realize the rising edge time-delay and the trailing edge time-delay of symmetry.With respect to the SAFF_CP flip-flop circuit, removed the NMOS pipe that is connected in the SAFF_CP circuit between MN2 and the MN3 in the FFDSRHD1X_SCB_FCS trigger, precharge load capacitance greatly reduces, can improve characteristic settling time of circuit greatly, circuit structure is simpler simultaneously, has reduced by an extra high-voltage power supply line V We1l(to PMOS pipe MP1, MP2 provides substrate biasing, V WellV DD), help using and designing of circuit more.Have again and between second level circuit QI and QNI, inserted two end to end inverters, avoid single clock phase latch output node QI, three step responses of QNI as the current potential holding unit.At last, the FFDSRHD1X_SCB_FCS trigger is directly left behind on logical metal-oxide-semiconductor on two-stage node SALATCH_P, SALATCH_N, QI, the QNI and is drawn in horizontal reset, set.Wherein utilize positive feedback dexterously, and the characteristics of two-stage circuit, the trombone slide of leaving behind on the part omitted.And to reset, set carried out the arrangement on the circuit prior level.
For FFDSRHD1X_SCB_FCS trigger more proposed by the invention performance characteristics with respect to traditional flip-flop circuit FFDSRHD1X, we adopt Versilicon 1.5-V0.15 μ m technology, use circuit simulation tools HSPICE that two kinds of circuit structures have been carried out the emulation comparative analysis.
Table 1 is depicted as two kinds of flip-flop circuit dynamic power consumption data relatively.Clock signal input CLK is 100MHz in the emulation of circuit dynamic power consumption, and 50% duty ratio square-wave signal (0V-1.5V).Data-signal input D is 20MHz, and 50% duty ratio square-wave signal (0V-1.5V).Input signal change-over time is 0.104ns.Flip-flop circuit output termination 20fF capacitive load.Q Loaded wherein, Qb Empty represent Q output termination 20fF capacitive load, its complementary output end Qb zero load (promptly not connecing load).Qb Loaded, Q Empty represent Qb output termination 20fF capacitive load, and the zero load of Q output.The dynamic power consumption data unit is microwatt (μ W).
Table 1 trigger dynamic power consumption relatively
Q Loaded，Qb Empty(μW) Qb Loaded，Q Empty(μW)
FFDSRHD1X 6.401 6.410
FFDSRHD1X_SCB_FCS 4.810 4.810
Save the power consumption ratio 24.9％ 25.0％
Table 2 is depicted as the comparison of two kinds of flip-flop circuit delay performances.The definition mode of delay performance is as follows: when the upset of input data D signal during far away in advance in the hopping edge of CLK, CLK is not subjected to the influence of metastable state effect to the time-delay of output Q, this time-delay is called static time delay, and 105% of static time delay is defined as time-delay (Delay).When CLK when the time-delay of output Q equals Delay (be static time delay 105%), the upset of input data D signal is with respect to being defined as pre-set time of the hopping edge of CLK the metastable state cycle (Tmp); Metastable state cycle and this moment time-delay and be defined as total time-delay (being Total Delay=Tmp+Delay).
Two kinds of flip-flop circuits adopt identical circuit arrangement, and input signal change-over time is 0.05ns, and complementary output end Q and Qb load are 0.02pF.Asynchronous set end, reset terminal are the 1.5V DC level, and promptly circuit working is under flip-flop states.RISE and FALL represent output signal rising edge and output signal trailing edge respectively; Tmp, Delay and Total Delay are the data targets of Q output under above-mentioned definition.Delay data unit is nanosecond (ns).
Table 2 trigger Total Delay relatively
Table 3 is that two kinds of structure trigger chip areas compare.Wherein in the rule of layout design, its width is fixed, and length is necessary for the integral multiple of 0.56 μ m.The unit of length is a micron (μ m).The unit of area is square micron (μ m 2).
Table 3 trigger chip area relatively
Width (μ m) Length (μ m) Area (μ m 2)
FFDSRHD1X 4.32 13.44 13.44*4.32
FFDSRHD1X_SCB_FCS 4.32 15.12 15.12*4.32
By above-mentioned data more as can be seen, structure of testing trigger of the present invention is compared with the corresponding construction of traditional digital standard unit, it has bigger advantage on power consumption, the performance of static time-delay also has greatly improved simultaneously, and TotalDelay and chip area are suitable substantially.Advantage with these performances makes it be well suited for being applied in the low power consumption digital large scale integrated circuit.
In this structural series,, following two kinds of triggers are arranged then if circuit only considers to be provided with position end or reset terminal.
1.FFDSHD1X_SCB_FCS be this serial d type flip flop that only has set function, as shown in Figure 7.Its basic principle is consistent with FFDSRHD1X_SCB_FCS, for set is rapid, has kept the MP18 pipe.Has the unit F FDSHD1X comparative result of identical function shown in table 11, table 12 and table 13 in the power consumption of its circuit, time-delay and area performance and the Verisilicon1.5-V0.15 μ m technology digital standard cell library.Test condition is the 1.5V DC level for the SN input signal, and other conditions are identical with the test condition of FFDSRHD1X_SCB_FCS.
Table 11 trigger dynamic power consumption relatively
Q Loaded，Qb Qb Loaded，Q
Empty(μW) Empty(μW)
FFDSHD1X 6.072 6.080
FFDSHD1X_SCB_FC_S 4.485 4.501
Save the power consumption ratio 26.1％ 26.0％
Table 12 trigger Total Delay relatively
Table 13 trigger chip area relatively
Width (μ m) Length (μ m) Area (μ m 2)
FFDSHD1X 4.32 10.64 10.64*4.32
FFDSHD1X_SCB_FCS 4.32 12.32 12.32*4.32
2.FFDRHD1X_SCB_FCS be this serial d type flip flop that only has reset function, as shown in Figure 8.Its basic principle is consistent with FFDSRHD1X_SCB_FCS, in order to reset rapidly, has kept the MP17 pipe.Has the unit F FDRHD1X comparative result of identical function shown in table 21, table 22 and table 23 in the power consumption of its circuit, time-delay and area performance and the Verisilicon1.5-V0.15 μ m technology digital standard cell library.Test condition is the 1.5V DC level for the RN input signal, and other conditions are identical with the test condition of FFDSRHD1X_SCB_FCS.
Table 21 trigger dynamic power consumption relatively
Q Loaded，Qb Empty(μW) Qb Loaded，Q Empty(μW)
FFDRHD1X 6.825 6.849
FFDRHD1X_SCB_FCS 4.506 4.505
Save the power consumption ratio 34.0％ 34.2％
Table 22 trigger Total Delay relatively
The hopping edge RISE FALL
Tmp Delay Total Delay Tmp Delay Total Delay
FFDRHD1X 49 347 396 102 338 440
FFDRHD1X_SCB_FCS 213 198 411 144 280 424
Table 23 trigger chip area relatively
Width (μ m) Length (μ m) Area (μ m 2)
FFDRHD1X 4.32 12.32 12.32*4.32
FFDRHD1X_SCB_FCS 4.32 12.32 12.32*4.32

Claims (3)

1、带复位和置位功能且基于条件预充结构的D触发器，其特征在于所述D触发器含有：1. A D flip-flop with reset and setting functions based on a conditional precharge structure, characterized in that the D flip-flop contains: 第一级锁存器，该锁存器含有：The first level of latches, which contain: 第1“或”逻辑电路，含有其衬底相互连接后接地的第1NMOS管(MN1)和第2NMOS管(MN2)，所述第1NMOS管的源极接时钟信号(CLK)，栅极接第2中间数据信号(DB)；所述第2NMOS管的源极和栅极都接第1输入数据信号(D)，该第1输入数据信号(D)和所述第2中间数据信号(DB)反相；The first "or" logic circuit includes a first NMOS transistor (MN1) and a second NMOS transistor (MN2) whose substrates are connected to each other and then grounded. The source of the first NMOS transistor is connected to the clock signal (CLK), and the gate is connected to the first NMOS transistor. 2 intermediate data signals (DB); the source and gate of the second NMOS transistor are both connected to the first input data signal (D), the first input data signal (D) and the second intermediate data signal (DB) inversion; 第2“或”逻辑电路，含有其衬底相互连接后接地的第3NMOS管(MN3)和第4NMOS管(MN4)所述第3NMOS管的源极接时钟信号(CLK)，栅极接所述第1输入数据信号(D)；所述第4NMOS管的源极和栅极都接第2中间数据信号(DB)；The 2nd "or" logic circuit includes the 3rd NMOS transistor (MN3) and the 4th NMOS transistor (MN4) whose substrates are connected to each other and then grounded. The source of the 3rd NMOS transistor is connected to the clock signal (CLK), and the gate is connected to the The first input data signal (D); the source and gate of the fourth NMOS transistor are connected to the second intermediate data signal (DB); 第1 PMOS管(MP1)，该管的栅极同时和所述第1NMOS管和第2NMOS管的漏极相连，而衬底接电源电压VDD；The first PMOS transistor (MP1), the gate of which is connected to the drains of the first NMOS transistor and the second NMOS transistor at the same time, and the substrate is connected to the power supply voltage V DD ; 第4 PMOS管(MP4)，该管的栅极同时和所述第3NMOS管和第4NMOS管的漏极相连，而衬底接电源电压VDD；The fourth PMOS transistor (MP4), the gate of which is connected to the drains of the third NMOS transistor and the fourth NMOS transistor at the same time, and the substrate is connected to the power supply voltage V DD ; 第5 PMOS管(MP15)，该管的漏极同时和所述第1PMOS管的源极相连，而栅极接输入置位信号(SN)经反相器后形成的中间反相置位控制信号(S)，该管的衬底和源极接电源电压VDD；The fifth PMOS transistor (MP15), the drain of this transistor is connected to the source of the first PMOS transistor at the same time, and the gate is connected to the intermediate inverting set control signal formed by the input set signal (SN) through the inverter (S), the substrate and source of the tube are connected to the power supply voltage V DD ; 第6 PMOS管(MP16)，该管的漏极同时和所述第4PMOS管的源极相连，而栅极接中间反相复位控制信号(R)，该中间反相复位控制信号(R)由中间反相置位控制信号(S)和输入复位信号(RN)经或非门后得到的，所述第6PMOS管的衬底和源极接电源电压VDD；The sixth PMOS transistor (MP16), the drain of the transistor is connected to the source of the fourth PMOS transistor at the same time, and the gate is connected to the intermediate inverted reset control signal (R), and the intermediate inverted reset control signal (R) is controlled by The intermediate inverting set control signal (S) and the input reset signal (RN) are obtained after passing through the NOR gate, and the substrate and the source of the 6th PMOS transistor are connected to the power supply voltage V DD ; 第3 PMOS管(MP3)，该管的衬底和源极连接的所述电源电压VDD；The 3rd PMOS tube (MP3), the substrate and the source of the tube are connected to the power supply voltage V DD ; 第2 PMOS管(MP2)，该管的衬底和源极连接的所述电源电压VDD；The second PMOS transistor (MP2), the substrate and the source of the transistor are connected to the power supply voltage V DD ; 第5 NMOS管(MN5)，该管的源极同时连接到所述第1PMOS管、第3PMOS管的漏极以及第2PMOS管的栅极，构成第3中间节点(SALATCH_N)；该第5NMOS管的衬底接地；The 5th NMOS tube (MN5), the source of this tube is connected to the drain of the 1st PMOS tube, the 3rd PMOS tube and the gate of the 2nd PMOS tube at the same time, forming the 3rd intermediate node (SALATCH_N); the 5th NMOS tube Substrate grounding; 第6 NMOS管(MN6)，该管的源极同时连接到所述第3PMOS管、第5NMOS管的栅极以及所述第2PMOS管、第4PMOS管的漏极，形成第4中间节点(SALATCH_P)，该第6NMOS管的栅极接第3中间节点(SALATCH_N)，而衬底接地；The 6th NMOS tube (MN6), the source of this tube is connected to the gate of the 3rd PMOS tube, the 5th NMOS tube and the drain of the 2nd PMOS tube and the 4th PMOS tube at the same time, forming the 4th intermediate node (SALATCH_P) , the gate of the sixth NMOS transistor is connected to the third intermediate node (SALATCH_N), and the substrate is grounded; 第10 NMOS管(MN17)，该管的源极接所述第4中间节点(SALATCH_P)，栅极接中间反相复位控制信号(R)，而衬底则在和漏极相连后接地；The 10th NMOS transistor (MN17), the source of the transistor is connected to the fourth intermediate node (SALATCH_P), the gate is connected to the intermediate inverting reset control signal (R), and the substrate is grounded after being connected to the drain; 第11 NMOS管(MN18)，该管的源极接所述第3中间节点(SALATCH_N)，栅极接中间反相置位控制信号(S)，而衬底则在和漏极相连后接地；The 11th NMOS transistor (MN18), the source of the transistor is connected to the third intermediate node (SALATCH_N), the gate is connected to the intermediate inverting set control signal (S), and the substrate is grounded after being connected to the drain; 第7 NMOS管(MN7)，该管的漏极和所述第5NMOS管的漏极相连，而衬底接地；The 7th NMOS tube (MN7), the drain of the tube is connected to the drain of the 5th NMOS tube, and the substrate is grounded; 第8 NMOS管(MN8)，该管的漏极和所述第6NMOS管的漏极相连，而衬底接地；The 8th NMOS tube (MN8), the drain of the tube is connected to the drain of the 6th NMOS tube, and the substrate is grounded; 一个反相器(XIVG1)，该反相器的输入端在和所述第7NMOS管栅极相连后接所述第1输入数据信号(D)，而该反相器的输出端为所述第8NMOS管的栅极提供第2中间数据信号(DB)；An inverter (XIVG1), the input terminal of the inverter is connected to the first input data signal (D) after being connected to the gate of the 7th NMOS transistor, and the output terminal of the inverter is the first The gate of the 8NMOS transistor provides the second intermediate data signal (DB); 第9 NMOS管(MN9)，该管的源极同时与所述第7NMOS管、第8NMOS管的漏极相连，栅极接时钟信号(CLK)，而衬底接地；The 9th NMOS tube (MN9), the source of this tube is connected to the drain of the 7th NMOS tube and the 8th NMOS tube at the same time, the gate is connected to the clock signal (CLK), and the substrate is grounded; 第二级锁存器，该锁存器由两个具有相同电器参数的单时钟相位锁存器构成，所述第二级锁存器含有：The second-level latch, which is composed of two single-clock phase latches with the same electrical parameters, the second-level latch contains: 第1个单时钟相位锁存器，含有：1st single clock phase latch with: 第111PMOS管(XOUT1.M1)，该管的源极和衬底相连后接电源电压VDD，而栅极接所述第4中间节点(SALATCH_P)；The 111th PMOS transistor (XOUT1.M1), the source of the transistor is connected to the substrate and then connected to the power supply voltage V DD , and the gate is connected to the fourth intermediate node (SALATCH_P); 第112NMOS管(XOUT1.M2)，该管的源极和所述第111PMOS管的漏极相连，而栅极接所述第4中间节点(SALATCH_P)；The 112th NMOS transistor (XOUT1.M2), the source of which is connected to the drain of the 111th PMOS transistor, and the gate is connected to the fourth intermediate node (SALATCH_P); 第113NMOS管(XOUT1.M3)管，该管的源极和所述第112NMOS管的漏极相连，而栅极接时钟信号(CLK)；The 113th NMOS transistor (XOUT1.M3), the source of which is connected to the drain of the 112th NMOS transistor, and the gate is connected to the clock signal (CLK); 第28NMOS管(MN28)，该管的栅极接中间反相置位控制信号(S)，而衬底在与所述第112NMOS管、第113NMOS管的衬底相连后接地，该管的漏极接地；The 28th NMOS transistor (MN28), the gate of the transistor is connected to the intermediate inverting set control signal (S), and the substrate is grounded after being connected to the substrate of the 112th NMOS transistor and the 113th NMOS transistor, and the drain of the transistor grounding; 第2个单时钟相位锁存器，含有：A second single clock phase latch containing: 第121PMOS管(XOUT2.M1)，该管的源极和衬底相连后接电源电压VDD，而栅极接所述第3中间节点(SALATCH_N)；The 121st PMOS transistor (XOUT2.M1), the source of the transistor is connected to the substrate and then connected to the power supply voltage V DD , and the gate is connected to the third intermediate node (SALATCH_N); 第122NMOS管(XOUT2.M2)，该管的源极和所述第121PMOS管的漏极相连，而栅极接所述第3中间节点(SALATCH_N)；The 122nd NMOS transistor (XOUT2.M2), the source of which is connected to the drain of the 121st PMOS transistor, and the gate is connected to the third intermediate node (SALATCH_N); 第123NMOS管(XOUT1.M3)，该管的源极和所述第122NMOS管的漏极相连，而栅极接时钟信号(CLK)；The 123rd NMOS transistor (XOUT1.M3), the source of which is connected to the drain of the 122nd NMOS transistor, and the gate is connected to the clock signal (CLK); 第27NMOS管(MN27)，该管的栅极接中间反相复位控制信号(R)，而衬底在与所述第122NMOS管、第123NMOS管的衬底相连后接地，该管的漏极接地；The 27th NMOS transistor (MN27), the gate of the transistor is connected to the intermediate inverting reset control signal (R), and the substrate is grounded after being connected to the substrate of the 122nd NMOS transistor and the 123rd NMOS transistor, and the drain of the transistor is grounded ; 电位保持单元，含有第4反相器(XIVG4)和第5反相器(XIVG5)，所述第4反相器(XIVG4)的输入端在和第5反相器(XIVG5)的输出端相连后接所述第111PMOS管的漏极以及第28NMOS管的源极，形成第5中间节点(QI)；所述第4反相器(XIVG4)的输出端在和第5反相器(XIVG5)的输入端相连后接所述第121PMOS管的漏极以及第27NMOS管的源极，形成第6中间节点(QNI)；The potential holding unit includes the fourth inverter (XIVG4) and the fifth inverter (XIVG5), the input end of the fourth inverter (XIVG4) is connected to the output end of the fifth inverter (XIVG5) The drain of the 111th PMOS transistor and the source of the 28th NMOS transistor are connected to form the 5th intermediate node (QI); the output terminal of the 4th inverter (XIVG4) is connected with the 5th inverter (XIVG5) The input terminal of the 121st PMOS transistor is connected and then connected to the drain of the 121st PMOS transistor and the source of the 27th NMOS transistor to form the 6th intermediate node (QNI); 第2输出反相器(XIVG2)和第3输出反相器(XIVG3)，所述第3反相器(XIVG3)的输入端和所述第6中间节点(QNI)相连，而输出端为第2输出信号(Qb)；所述第2反相器(XIVG2)的输入端和所述第5中间节点(QI)相连，而输出端为第1输出信号(Q)。The second output inverter (XIVG2) and the third output inverter (XIVG3), the input end of the third inverter (XIVG3) is connected to the sixth intermediate node (QNI), and the output end is the first 2 output signal (Qb); the input end of the second inverter (XIVG2) is connected to the fifth intermediate node (QI), and the output end is the first output signal (Q). 2、带置位功能且基于条件预充结构的D触发器，其特征在于所述D触发器含有：2. A D flip-flop with a setting function and based on a conditional precharge structure, characterized in that the D flip-flop contains: 第一级锁存器，该锁存器含有：The first level of latches, which contain: 第1“或”逻辑电路，含有其衬底相互连接后接地的第1NMOS管(MN1)和第2NMOS管(MN2)，所述第1NMOS管的源极接时钟信号(CLK)，栅极接第2中间数据信号(DB)；所述第2NMOS管的源极和栅极都接第1输入数据信号(D)，该第1输入数据信号(D)和所述第2中间数据信号(DB)反相；The first "or" logic circuit includes a first NMOS transistor (MN1) and a second NMOS transistor (MN2) whose substrates are connected to each other and then grounded. The source of the first NMOS transistor is connected to the clock signal (CLK), and the gate is connected to the first NMOS transistor. 2 intermediate data signals (DB); the source and gate of the second NMOS transistor are both connected to the first input data signal (D), the first input data signal (D) and the second intermediate data signal (DB) inversion; 第2“或”逻辑电路，含有其衬底相互连接后接地的第3NMOS管(MN3)和第4NMOS管(MN4)，所述第3NMOS管的源极接时钟信号(CLK)，栅极接所述第1输入数据信号(D)；所述第4NMOS管的源极和栅极都接第2中间数据信号(DB)；The 2nd "or" logic circuit includes the 3rd NMOS transistor (MN3) and the 4th NMOS transistor (MN4) whose substrates are connected to each other and grounded, the source of the 3rd NMOS transistor is connected to the clock signal (CLK), and the gate is connected to the The first input data signal (D); the source and gate of the fourth NMOS transistor are connected to the second intermediate data signal (DB); 第1 PMOS管(MP1)，该管的栅极同时和所述第1NMOS管和第2NMOS管的漏极相连，而衬底接电源电压VDD；The first PMOS transistor (MP1), the gate of which is connected to the drains of the first NMOS transistor and the second NMOS transistor at the same time, and the substrate is connected to the power supply voltage V DD ; 第4 PMOS管(MP4)，该管的栅极同时和所述第3NMOS管和第4NMOS管的漏极相连，而衬底接电源电压VDD；The fourth PMOS transistor (MP4), the gate of which is connected to the drains of the third NMOS transistor and the fourth NMOS transistor at the same time, and the substrate is connected to the power supply voltage V DD ; 第5 PMOS管(MP15)，该管的漏极同时和所述第1NMOS管的源极相连，而栅极接输入置位信号(SN)经反相器后形成的中间反相置位控制信号(S)，该管的衬底和源极接电源电压VDD；The fifth PMOS transistor (MP15), the drain of the transistor is connected to the source of the first NMOS transistor at the same time, and the gate is connected to the intermediate inverting set control signal formed by the input set signal (SN) through the inverter (S), the substrate and source of the tube are connected to the power supply voltage V DD ; 第3 PMOS管(MP3)，该管的衬底和源极连接的所述电源电压VDD；The 3rd PMOS tube (MP3), the substrate and the source of the tube are connected to the power supply voltage V DD ; 第2 PMOS管(MP2)，该管的衬底和源极连接的所述电源电压VDD；The second PMOS transistor (MP2), the substrate and the source of the transistor are connected to the power supply voltage V DD ; 第5 NMOS管(MN5)，该管的源极同时连接到所述第1PMOS管、第3PMOS管的漏极以及第2PMOS管的栅极，构成第3中间节点(SALATCH_N)；该第5NMOS管的衬底接地；The 5th NMOS tube (MN5), the source of this tube is connected to the drain of the 1st PMOS tube, the 3rd PMOS tube and the gate of the 2nd PMOS tube at the same time, forming the 3rd intermediate node (SALATCH_N); the 5th NMOS tube Substrate grounding; 第6 NMOS管(MN6)，该管的源极同时连接到所述第3PMOS管、第5NMOS管的栅极以及所述第2PMOS管、第4PMOS管的漏极，形成第4中间节点(SALATCH_P)，该第6NMOS管的栅极接第3中间节点(SALATCH_N)，而衬底接地；The 6th NMOS tube (MN6), the source of this tube is connected to the gate of the 3rd PMOS tube, the 5th NMOS tube and the drain of the 2nd PMOS tube and the 4th PMOS tube at the same time, forming the 4th intermediate node (SALATCH_P) , the gate of the sixth NMOS transistor is connected to the third intermediate node (SALATCH_N), and the substrate is grounded; 下拉第3中间节点(SALATCH_N)用的第18NMOS管(MN18)，该管的源极接所述第3中间节点(SALATCH_N)，栅极接中间反相置位控制信号(S)，而衬底则在和漏极相连后接地；Pull down the 18th NMOS transistor (MN18) for the third intermediate node (SALATCH_N), the source of the transistor is connected to the third intermediate node (SALATCH_N), the gate is connected to the intermediate inverting set control signal (S), and the substrate Then it is grounded after being connected to the drain; 上拉第4中间节点(SALATCH_P)用的第18PMOS管(MP18)，该管的源极接所述第4中间节点(SALATCH_P)，栅极接输入置位信号SN，而衬底则在和漏极相连后所述电源电压VDD；Pull up the 18th PMOS transistor (MP18) for the fourth intermediate node (SALATCH_P), the source of the transistor is connected to the fourth intermediate node (SALATCH_P), the gate is connected to the input set signal SN, and the substrate is connected to the drain After the poles are connected, the power supply voltage V DD ; 第7 NMOS管(MN7)，该管的漏极和所述第5NMOS管的漏极相连，而衬底接地；The 7th NMOS tube (MN7), the drain of the tube is connected to the drain of the 5th NMOS tube, and the substrate is grounded; 第8 NMOS管(MN8)，该管的漏极和所述第6NMOS管的漏极相连，而衬底接地；The 8th NMOS tube (MN8), the drain of the tube is connected to the drain of the 6th NMOS tube, and the substrate is grounded; 一个反相器(XIVG1)，该反相器的输入端在和所述第7NMOS管栅极相连后接所述第1输入数据信号(D)，而该反相器的输出端为所述第8NMOS管的栅极提供第2中间数据信号(DB)；An inverter (XIVG1), the input terminal of the inverter is connected to the first input data signal (D) after being connected to the gate of the 7th NMOS transistor, and the output terminal of the inverter is the first The gate of the 8NMOS transistor provides the second intermediate data signal (DB); 第9 NMOS管(MN9)，该管的源极同时与所述第7NMOS管、第8NMOS管的漏极相连，栅极接时钟信号(CLK)，而衬底接地；The 9th NMOS tube (MN9), the source of this tube is connected to the drains of the 7th NMOS tube and the 8th NMOS tube at the same time, the gate is connected to the clock signal (CLK), and the substrate is grounded; 第二级锁存器，该锁存器由两个具有相同电器参数的单时钟相位锁存器构成，所述第二级锁存器含有：The second-level latch, which is composed of two single-clock phase latches with the same electrical parameters, the second-level latch contains: 第1个单时钟相位锁存器，含有：1st single clock phase latch with: 第111PMOS管(XOUT1.M1)，该管的源极和衬底相连后接电源电压VDD，而栅极接所述第4中间节点(SALATCH_P)；The 111th PMOS transistor (XOUT1.M1), the source of the transistor is connected to the substrate and then connected to the power supply voltage V DD , and the gate is connected to the fourth intermediate node (SALATCH_P); 第112NMOS管(XOUT1.M2)，该管的源极和所述第111PMOS管的漏极相连，而栅极接所述第4中间节点(SALATCH_P)；The 112th NMOS transistor (XOUT1.M2), the source of which is connected to the drain of the 111th PMOS transistor, and the gate is connected to the fourth intermediate node (SALATCH_P); 第113NMOS管(XOUT1.M3)，该管的源极和所述第112NMOS管的漏极相连，而栅极接时钟信号(CLK)；The 113th NMOS transistor (XOUT1.M3), the source of which is connected to the drain of the 112th NMOS transistor, and the gate is connected to the clock signal (CLK); 第28NMOS管(MN28)，该管的栅极接中间反相置位控制信号(S)，而衬底在与所述第112NMOS管、第113NMOS管的衬底相连后接地，该管的漏极接地；The 28th NMOS transistor (MN28), the gate of the transistor is connected to the intermediate inverting set control signal (S), and the substrate is grounded after being connected to the substrate of the 112th NMOS transistor and the 113th NMOS transistor, and the drain of the transistor grounding; 第2个单时钟相位锁存器，含有：A second single clock phase latch containing: 第121PMOS管(XOUT2.M1)，该管的源极和衬底相连后接电源电压VDD，而栅极接所述第3中间节点(SALATCH_N)；The 121st PMOS transistor (XOUT2.M1), the source of the transistor is connected to the substrate and then connected to the power supply voltage V DD , and the gate is connected to the third intermediate node (SALATCH_N); 第122NMOS管(XOUT2.M2)，该管的源极和所述第121PMOS管的漏极相连，而栅极接所述第3中间节点(SALATCH_N)，该管衬底接地；The 122nd NMOS transistor (XOUT2.M2), the source of the transistor is connected to the drain of the 121st PMOS transistor, the gate is connected to the third intermediate node (SALATCH_N), and the substrate of the transistor is grounded; 第123NMOS管(XOUT1.M3)，该管的源极和所述第122NMOS管的漏极相连，而栅极接时钟信号(CLK)，该管衬底接地；The 123rd NMOS transistor (XOUT1.M3), the source of the transistor is connected to the drain of the 122nd NMOS transistor, the gate is connected to the clock signal (CLK), and the substrate of the transistor is grounded; 电位保持单元，含有第4反相器(XIVG4)和第5反相器(XIVG5)，所述第4反相器(XIVG4)的输入端在和第5反相器(XIVG5)的输出端相连后接所述第111PMOS管的漏极以及第28NMOS管的源极，形成第5中间节点(QI)；所述第4反相器(XIVG4)的输出端在和第5反相器(XIVG5)的输入端相连后接所述第121PMOS管的漏极，形成第6中间节点(QNI)；The potential holding unit includes the fourth inverter (XIVG4) and the fifth inverter (XIVG5), the input end of the fourth inverter (XIVG4) is connected to the output end of the fifth inverter (XIVG5) The drain of the 111th PMOS transistor and the source of the 28th NMOS transistor are connected to form the 5th intermediate node (QI); the output terminal of the 4th inverter (XIVG4) is connected with the 5th inverter (XIVG5) The input end of the input terminal is connected and then connected to the drain of the 121st PMOS transistor to form the 6th intermediate node (QNI); 第2输出反相器(XIVG2)和第3输出反相器(XIVG3)，所述第3反相器(XIVG3)的输入端和所述第6中间节点(QNI)相连，而输出端为第2输出信号(Qb)；所述第2反相器(XIVG2)的输入端和所述第5中间节点(QI)相连，而输出端为第1输出信号(Q)。The second output inverter (XIVG2) and the third output inverter (XIVG3), the input end of the third inverter (XIVG3) is connected to the sixth intermediate node (QNI), and the output end is the first 2 output signal (Qb); the input end of the second inverter (XIVG2) is connected to the fifth intermediate node (QI), and the output end is the first output signal (Q). 3、带复位功能且基于条件预充结构的D触发器，其特征在于所述D触发器含有：3. A D flip-flop with a reset function and based on a conditional precharge structure, characterized in that the D flip-flop contains: 第一级锁存器，该锁存器含有：The first level of latches, which contain: 第1“或”逻辑电路，含有其衬底相互连接后接地的第1NMOS管(MN1)和第2NMOS管(MN2)，所述第1NMOS管的源极接时钟信号(CLK)，栅极接第2中间数据信号(DB)；所述第2NMOS管的源极和栅极都接第1输入数据信号(D)，该第1输入数据信号(D)和所述第2中间数据信号(DB)反相；The first "or" logic circuit includes a first NMOS transistor (MN1) and a second NMOS transistor (MN2) whose substrates are connected to each other and then grounded. The source of the first NMOS transistor is connected to the clock signal (CLK), and the gate is connected to the first NMOS transistor. 2 intermediate data signals (DB); the source and gate of the second NMOS transistor are both connected to the first input data signal (D), the first input data signal (D) and the second intermediate data signal (DB) inversion; 第2“或”逻辑电路，含有其衬底相互连接后接地的第3NMOS管(MN3)和第4NMOS管(MN4)，所述第3NMOS管的源极接时钟信号(CLK)，栅极接所述第1输入数据信号(D)；所述第4NMOS管的源极和栅极都接第2中间数据信号(DB)；The 2nd "or" logic circuit includes the 3rd NMOS transistor (MN3) and the 4th NMOS transistor (MN4) whose substrates are connected to each other and grounded, the source of the 3rd NMOS transistor is connected to the clock signal (CLK), and the gate is connected to the The first input data signal (D); the source and gate of the fourth NMOS transistor are connected to the second intermediate data signal (DB); 第1 PMOS管(MP1)，该管的栅极同时和所述第1NMOS管和第2NMOS管的漏极相连，而衬底接电源电压VDD；The first PMOS transistor (MP1), the gate of which is connected to the drains of the first NMOS transistor and the second NMOS transistor at the same time, and the substrate is connected to the power supply voltage V DD ; 第4 PMOS管(MP4)，该管的栅极同时和所述第3NMOS管和第4NMOS管的漏极相连，而衬底接电源电压VDD；The fourth PMOS transistor (MP4), the gate of which is connected to the drains of the third NMOS transistor and the fourth NMOS transistor at the same time, and the substrate is connected to the power supply voltage V DD ; 第6 PMOS管(MP16)，该管的漏极同时和所述第4NMOS管的源极相连，而栅极接输入复位信号(RN)经反相器后形成的中间反相复位控制信号R，该管的衬底和源极接电源电压VDD；The sixth PMOS transistor (MP16), the drain of the transistor is connected to the source of the fourth NMOS transistor at the same time, and the gate is connected to the intermediate inverting reset control signal R formed by the input reset signal (RN) through the inverter, The substrate and source of the tube are connected to the power supply voltage V DD ; 第3 PMOS管(MP3)，该管的衬底和源极连接的所述电源电压VDD；The 3rd PMOS tube (MP3), the substrate and the source of the tube are connected to the power supply voltage V DD ; 第2 PMOS管(MP2)，该管的衬底和源极连接的所述电源电压VDD；The second PMOS transistor (MP2), the substrate and the source of the transistor are connected to the power supply voltage V DD ; 第5 NMOS管(MN5)，该管的源极同时连接到所述第1PMOS管、第3PMOS管的漏极以及第2PMOS管的栅极，构成第3中间节点(SALATCH_N)；该第5NMOS管的衬底接地；The 5th NMOS tube (MN5), the source of this tube is connected to the drain of the 1st PMOS tube, the 3rd PMOS tube and the gate of the 2nd PMOS tube at the same time, forming the 3rd intermediate node (SALATCH_N); the 5th NMOS tube Substrate grounding; 第6 NMOS管(MN6)，该管的源极同时连接到所述第3PMOS管、第5NMOS管的栅极以及所述第2PMOS管、第4PMOS管的漏极，形成第4中间节点(SALATCH_P)，该第6NMOS管的栅极接第3中间节点(SALATCH_N)，而衬底接地；The 6th NMOS tube (MN6), the source of this tube is connected to the gate of the 3rd PMOS tube, the 5th NMOS tube and the drain of the 2nd PMOS tube and the 4th PMOS tube at the same time, forming the 4th intermediate node (SALATCH_P) , the gate of the sixth NMOS transistor is connected to the third intermediate node (SALATCH_N), and the substrate is grounded; 下拉第4中间节点(SALATCH_P)用的第17NMOS管(MN17)，该管的源极接所述第4中间节点(SALATCH_P)，栅极接中间反相复位控制信号(R)，而衬底则在和漏极相连后接地；Pull down the 17th NMOS transistor (MN17) used for the 4th intermediate node (SALATCH_P), the source of the tube is connected to the 4th intermediate node (SALATCH_P), the gate is connected to the intermediate inverting reset control signal (R), and the substrate is Grounded after being connected to the drain; 上拉第3中间节点(SALATCH_N)用的第17PMOS管(MP17)管，该管的源极接所述第3中间节点(SALATCH_N)，栅极接输入复位信号(RN)，而衬底则在和漏极相连后所述电源电压VDD；Pull up the 17th PMOS transistor (MP17) used for the third intermediate node (SALATCH_N), the source of the transistor is connected to the third intermediate node (SALATCH_N), the gate is connected to the input reset signal (RN), and the substrate is in After being connected to the drain, the power supply voltage V DD ; 第7 NMOS管(MN7)，该管的漏极和所述第5NMOS管的漏极相连，而衬底接地；The 7th NMOS tube (MN7), the drain of the tube is connected to the drain of the 5th NMOS tube, and the substrate is grounded; 第8 NMOS管(MN8)，该管的漏极和所述第6NMOS管的漏极相连，而衬底接地；The 8th NMOS tube (MN8), the drain of the tube is connected to the drain of the 6th NMOS tube, and the substrate is grounded; 一个反相器(XIVG1)，该反相器的输入端在和所述第7NMOS管栅极相连后接所述第1输入数据信号(D)，而该反相器的输出端为所述第8NMOS管的栅极提供第2中间数据信号(DB)；An inverter (XIVG1), the input terminal of the inverter is connected to the first input data signal (D) after being connected to the gate of the 7th NMOS transistor, and the output terminal of the inverter is the first The gate of the 8NMOS transistor provides the second intermediate data signal (DB); 第9 NMOS管(MN9)，该管的源极同时与所述第7NMOS管、第8NMOS管的漏极相连，栅极接时钟信号(CLK)，而衬底接地；The 9th NMOS tube (MN9), the source of this tube is connected to the drain of the 7th NMOS tube and the 8th NMOS tube at the same time, the gate is connected to the clock signal (CLK), and the substrate is grounded; 第二级锁存器，该锁存器由两个具有相同电器参数的单时钟相位锁存器构成，所述第二级锁存器含有：The second-level latch, which is composed of two single-clock phase latches with the same electrical parameters, the second-level latch contains: 第1个单时钟相位锁存器，含有：1st single clock phase latch with: 第111PMOS管(XOUT1.M1)，该管的源极和衬底相连后接电源电压VDD，而栅极接所述第4中间节点(SALATCH_P)；The 111th PMOS transistor (XOUT1.M1), the source of the transistor is connected to the substrate and then connected to the power supply voltage V DD , and the gate is connected to the fourth intermediate node (SALATCH_P); 第112NMOS管(XOUT1.M2)，该管的源极和所述第111PMOS管的漏极相连，而栅极接所述第4中间节点(SALATCH_P)；The 112th NMOS transistor (XOUT1.M2), the source of which is connected to the drain of the 111th PMOS transistor, and the gate is connected to the fourth intermediate node (SALATCH_P); 第113NMOS管(XOUT1.M3)，该管的源极和所述第112NMOS管的漏极相连，而栅极接时钟信号(CLK)；The 113th NMOS transistor (XOUT1.M3), the source of which is connected to the drain of the 112th NMOS transistor, and the gate is connected to the clock signal (CLK); 第2个单时钟相位锁存器，含有：A second single clock phase latch containing: 第121PMOS管(XOUT2.M1)，该管的源极和衬底相连后接电源电压VDD，而栅极接所述第3中间节点(SALATCH_N)；The 121st PMOS transistor (XOUT2.M1), the source of the transistor is connected to the substrate and then connected to the power supply voltage V DD , and the gate is connected to the third intermediate node (SALATCH_N); 第122NMOS管(XOUT2.M2)，该管的源极和所述第121PMOS管的漏极相连，而栅极接所述第3中间节点(SALATCH_N)；The 122nd NMOS transistor (XOUT2.M2), the source of which is connected to the drain of the 121st PMOS transistor, and the gate is connected to the third intermediate node (SALATCH_N); 第123NMOS管(XOUT1.M3)，该管的源极和所述第122NMOS管的漏极相连，而栅极接时钟信号(CLK)；The 123rd NMOS transistor (XOUT1.M3), the source of which is connected to the drain of the 122nd NMOS transistor, and the gate is connected to the clock signal (CLK); 第27NMOS管(MN27)，该管的栅极接中间反相复位控制信号(R)，而衬底在与所述第122NMOS管、第123NMOS管的衬底相连后接地，该管的漏极接地；The 27th NMOS transistor (MN27), the gate of the transistor is connected to the intermediate inverting reset control signal (R), and the substrate is grounded after being connected to the substrate of the 122nd NMOS transistor and the 123rd NMOS transistor, and the drain of the transistor is grounded ; 电位保持单元，含有第4反相器(XIVG4)和第5反相器(XIVG5)，所述第4反相器(XIVG4)的输入端在和第5反相器(XIVG5)的输出端相连后接所述第111PMOS管的漏极，形成第5中间节点(QI)；所述第4反相器(XIVG4)的输出端在和第5反相器(XIVG5)的输入端相连后接所述第121PMOS管的漏极以及第27NMOS管的源极，形成第6中间节点(QNI)；The potential holding unit includes the fourth inverter (XIVG4) and the fifth inverter (XIVG5), the input end of the fourth inverter (XIVG4) is connected to the output end of the fifth inverter (XIVG5) Then connect the drain of the 111th PMOS transistor to form the 5th intermediate node (QI); the output terminal of the 4th inverter (XIVG4) is connected to the input terminal of the 5th inverter (XIVG5) and then connected to the The drain of the 121st PMOS transistor and the source of the 27th NMOS transistor form the sixth intermediate node (QNI); 第2输出反相器(XIVG2)和第3输出反相器(XIVG3)，所述第3反相器(XIVG3)的输入端和所述第6中间节点(QNI)相连，而输出端为第2输出信号(Qb)；所述第2反相器(XIVG2)的输入端和所述第5中间节点(QI)相连，而输出端为第1输出信号(Q)。The second output inverter (XIVG2) and the third output inverter (XIVG3), the input end of the third inverter (XIVG3) is connected to the sixth intermediate node (QNI), and the output end is the first 2 output signal (Qb); the input end of the second inverter (XIVG2) is connected to the fifth intermediate node (QI), and the output end is the first output signal (Q).
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CN102055463A (en) * 2010-12-08 2011-05-11 北京大学 Contention constrained RAM latch
CN102339637B (en) * 2011-06-01 2014-07-23 北京大学 Condition-precharged sense-amplifier-based flip flop
CN102394601B (en) * 2011-10-21 2013-12-11 中国人民解放军国防科学技术大学 D trigger provided with scanning structure and resisting single event upset
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