CN109884516B - Asynchronous reset trigger verification circuit and integrated circuit verification device - Google Patents
Asynchronous reset trigger verification circuit and integrated circuit verification device Download PDFInfo
- Publication number
- CN109884516B CN109884516B CN201910086037.3A CN201910086037A CN109884516B CN 109884516 B CN109884516 B CN 109884516B CN 201910086037 A CN201910086037 A CN 201910086037A CN 109884516 B CN109884516 B CN 109884516B
- Authority
- CN
- China
- Prior art keywords
- flop
- circuit
- verification
- flip
- trigger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012795 verification Methods 0.000 title claims abstract description 137
- 230000000737 periodic effect Effects 0.000 claims description 19
- 238000010200 validation analysis Methods 0.000 claims 6
- 238000012360 testing method Methods 0.000 abstract description 24
- 238000010586 diagram Methods 0.000 description 18
- 239000013598 vector Substances 0.000 description 14
- 230000000630 rising effect Effects 0.000 description 6
- 238000004904 shortening Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
本发明公开了一种异步复位触发器验证电路以及集成电路验证装置，所述异步复位触发器验证电路包括第一逻辑电路和第二逻辑电路，所述第一逻辑电路和所述第二逻辑电路串联；所述第一逻辑电路包括第一D触发器、或门以及第一反相器；所述第二逻辑电路包括第二D触发器和第二反相器。本发明提供的异步复位触发器验证电路以及集成电路验证装置，减小了进行功能验证占用的电路面积，缩短了测试时间。
The invention discloses an asynchronous reset flip-flop verification circuit and an integrated circuit verification device. The asynchronous reset flip-flop verification circuit includes a first logic circuit and a second logic circuit. The first logic circuit and the second logic circuit connected in series; the first logic circuit includes a first D flip-flop, an OR gate and a first inverter; the second logic circuit includes a second D flip-flop and a second inverter. The asynchronous reset flip-flop verification circuit and the integrated circuit verification device provided by the invention reduce the circuit area occupied by the function verification and shorten the test time.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an asynchronous reset trigger verification circuit and an integrated circuit verification device.
Background
In digital circuits, various kinds of information are represented by a binary basic operation signal, and a flip-flop is a basic unit for storing such a signal. The trigger has a simple structure and reliable operation, and can be widely applied because many other application circuits can be developed on the basis of the trigger. Particularly, the clock-controlled flip-flop provides a condition for simultaneously controlling the working states of a plurality of flip-flops, which are basic unit circuits of a sequential circuit and are often used for constructing transmission, buffering, latch circuits and other common circuits of information.
Fig. 1 is a schematic structural diagram of an asynchronous reset D flip-flop, where the D flip-flop includes a data input end D, a clock input end CK, a reset end RN, and an output end Q. At the arrival of a rising edge of the clock signal, the state of the output Q depends on the state of the output Q before the arrival of the rising edge. Therefore, the D flip-flop has two functions of setting "0" and setting "1". The D trigger has wide application and can be used as a register, a shift register, a frequency division, a waveform generator and the like of a digital signal.
In the prior art, the functional verification of the D flip-flop is completed by off-chip testing, and it is necessary to extract each port of the D flip-flop, and implement verification by traversing all test vectors in the truth table of the D flip-flop shown in fig. 2. The verification method needs to consume more resources, including area consumption caused by leading out four ports of a chip and test time consumption caused by four groups of test vectors.
Disclosure of Invention
The invention aims to solve the problems of large circuit area and long test time for the function verification of the asynchronous reset D trigger.
The invention is realized by the following technical scheme:
an asynchronous reset trigger verification circuit comprises a first D trigger, an OR gate and a first inverter;
the data input end of the first D trigger receives a digital signal '1', the clock input end of the first D trigger is connected with the first input end of the OR gate and serves as the input end of the asynchronous reset trigger verification circuit, the reset end of the first D trigger is connected with the output end of the OR gate, the output end of the first D trigger is connected with the input end of the first phase inverter and serves as the output end of the asynchronous reset trigger verification circuit, and the output end of the first phase inverter is connected with the second input end of the OR gate.
Optionally, an input of the asynchronous reset flip-flop verification circuit is adapted to receive a periodic signal.
Based on the same inventive concept, the invention provides another asynchronous reset trigger verification circuit, which comprises a second D trigger and a second inverter;
the data input end of the second D trigger is connected with the output end of the second phase inverter, the clock input end of the second D trigger serves as the input end of the asynchronous reset trigger verification circuit, the reset end of the second D trigger receives a digital signal '1', and the output end of the second D trigger is connected with the input end of the second phase inverter and serves as the output end of the asynchronous reset trigger verification circuit.
Optionally, an input of the asynchronous reset flip-flop verification circuit is adapted to receive a periodic signal.
Based on the same inventive concept, the invention provides another asynchronous reset trigger verification circuit, which comprises a first logic circuit and a second logic circuit, wherein the first logic circuit and the second logic circuit are connected in series;
the first logic circuit comprises a first D flip-flop, an OR gate and a first phase inverter, wherein a data input end of the first D flip-flop receives a digital signal '1', a clock input end of the first D flip-flop is connected with a first input end of the OR gate and serves as an input end of the first logic circuit, a reset end of the first D flip-flop is connected with an output end of the OR gate, an output end of the first D flip-flop is connected with an input end of the first phase inverter and serves as an output end of the first logic circuit, and an output end of the first phase inverter is connected with a second input end of the OR gate;
the second logic circuit comprises a second D trigger and a second phase inverter, the data input end of the second D trigger is connected with the output end of the second phase inverter, the clock input end of the second D trigger is used as the input end of the second logic circuit, the reset end of the second D trigger receives a digital signal '1', and the output end of the second D trigger is connected with the input end of the second phase inverter and is used as the output end of the second logic circuit.
Optionally, an input end of the first logic circuit is used as an input end of the asynchronous reset trigger verification circuit, an output end of the first logic circuit is connected to an input end of the second logic circuit, and an output end of the second logic circuit is used as an output end of the asynchronous reset trigger verification circuit.
Optionally, an input end of the second logic circuit is used as an input end of the asynchronous reset trigger verification circuit, an output end of the second logic circuit is connected to an input end of the first logic circuit, and an output end of the first logic circuit is used as an output end of the asynchronous reset trigger verification circuit.
Optionally, an input of the asynchronous reset flip-flop verification circuit is adapted to receive a periodic signal.
Optionally, the amplitude of the digital signal "1" is a power supply voltage.
Based on the same inventive concept, the invention provides an integrated circuit verification device, which comprises a data distributor, a data selector and M verification modules, wherein at least one of the M verification modules is the asynchronous reset trigger verification circuit, and M is an integer not less than 2;
the data input end of the data distributor is used as the input end of the integrated circuit verification device, each address end of the data distributor is correspondingly connected with one address end of the data selector and is used for receiving one path of address signals, each output end of the data distributor is correspondingly connected with the input end of one verification module, each input end of the data selector is correspondingly connected with the output end of one verification module, and the output end of the data selector is used as the output end of the integrated circuit verification device.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the asynchronous reset trigger verification circuit provided by the invention, the asynchronous reset trigger is constructed into a logic circuit with only one input end and one output end, and the function verification of the asynchronous reset trigger can be completed only by leading out two ports and configuring two groups of test vectors, so that the circuit area occupied by the function verification is reduced, and the test time is shortened. According to the integrated circuit verification device provided by the invention, the data distributor and the data selector are arranged, so that large-scale verification of a plurality of verification modules can be realized, and the verification efficiency is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of an asynchronous reset D flip-flop;
FIG. 2 is a truth table diagram of an asynchronous reset D flip-flop;
FIG. 3 is a schematic diagram of an asynchronous reset trigger verification circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of test vectors of the asynchronous reset flip-flop verification circuit shown in FIG. 3;
FIG. 5 is a schematic diagram of an asynchronous reset flip-flop verification circuit according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of test vectors of the asynchronous reset flip-flop verification circuit shown in FIG. 5;
FIG. 7 is a schematic diagram of an asynchronous reset flip-flop verification circuit according to yet another embodiment of the present invention;
FIG. 8 is a schematic diagram of an asynchronous reset flip-flop verification circuit according to yet another embodiment of the present invention;
FIG. 9 is a schematic diagram of test vectors for the asynchronous reset flip-flop verification circuit shown in FIGS. 7 and 8;
FIG. 10 is a schematic structural diagram of an integrated circuit verification apparatus according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
Fig. 3 is a schematic structural diagram of an asynchronous reset flip-flop verification circuit, which includes a first D flip-flop 31, an or gate 32, and a first inverter 33.
Specifically, the data input end D of the first D flip-flop 31 receives a digital signal "1", the clock input end CK of the first D flip-flop 31 is connected to the first input end of the or gate 32 and serves as the input end IN1 of the asynchronous reset flip-flop verification circuit, the reset end RN of the first D flip-flop 31 is connected to the output end of the or gate 32, the output end Q of the first D flip-flop 31 is connected to the input end of the first inverter 33 and serves as the output end OUT1 of the asynchronous reset flip-flop verification circuit, and the output end of the first inverter 33 is connected to the second input end of the or gate 32.
When the first D flip-flop 31 is functionally verified, the input terminal IN1 of the asynchronous reset flip-flop verification circuit receives a periodic signal, which may be a clock signal. The operation of the asynchronous reset flip-flop verification circuit is described below with reference to the test vectors shown in fig. 4:
assuming that the initial state of the reset terminal RN of the first D flip-flop 31 is a digital signal "0", the output terminal Q of the first D flip-flop 31 is set to a digital signal "0", regardless of the value of the clock input terminal CK of the first D flip-flop 31, the reset terminal RN of the first D flip-flop 31 is set to a digital signal "1", and the output terminal Q of the first D flip-flop 31 holds data; when the periodic signal received by the clock input terminal CK of the first D flip-flop 31 is a rising edge, the output terminal Q of the first D flip-flop 31 collects the digital signal "1" received by the data input terminal D of the first D flip-flop 31, at this time, since the clock input terminal CK of the first D flip-flop 31 is the digital signal "1", the reset terminal RN of the first D flip-flop 31 is still the digital signal "1", and the output terminal Q of the first D flip-flop 31 holds data; when the periodic signal received by the clock input terminal CK of the first D flip-flop 31 is a falling edge, the output terminal Q of the first D flip-flop 31 holds the digital signal "1", the reset terminal RN of the first D flip-flop 31 is set to the digital signal "0", and the output terminal Q of the first D flip-flop 31 is set to the digital signal "0".
When the initial state of the reset terminal RN of the first D flip-flop 31 is the digital signal "1", the working principle of the asynchronous reset flip-flop verification circuit is similar to that when the initial state of the reset terminal RN of the first D flip-flop 31 is the digital signal "0", and details are not repeated here. The asynchronous reset trigger verification circuit provided in this embodiment can complete verification of the first, third, and fourth rows of the truth table of the asynchronous trigger shown in fig. 2 by only leading out two ports, that is, the clock input terminal CK of the first D flip-flop 31 and the output terminal Q of the first D flip-flop 31, and configuring two sets of test vectors, thereby reducing the circuit area occupied for performing functional verification and shortening the test time.
Example 2
In this embodiment, another asynchronous reset flip-flop verification circuit is provided, and fig. 5 is a schematic structural diagram of the asynchronous reset flip-flop verification circuit, where the asynchronous reset flip-flop verification circuit includes a second D flip-flop 51 and a second inverter 52.
The data input end D of the second D flip-flop 51 is connected to the output end of the second inverter 52, the clock input end CK of the second D flip-flop 51 serves as the input end IN2 of the asynchronous reset flip-flop verification circuit, the reset end RN of the second D flip-flop 51 receives the digital signal "1", and the output end Q of the second D flip-flop 51 is connected to the input end of the second inverter 52 and serves as the output end OUT2 of the asynchronous reset flip-flop verification circuit.
When the second D flip-flop 51 is functionally verified, the input terminal IN2 of the asynchronous reset flip-flop verification circuit receives a periodic signal, which may be a clock signal. The operation of the asynchronous reset flip-flop verification circuit is described below with reference to the test vectors shown in fig. 6:
assuming that the initial state of the output Q of the second D flip-flop 51 is a digital signal "0", the data input D of the second D flip-flop 51 is set to a digital signal "1"; when the periodic signal received by the clock input terminal CK of the second D flip-flop 51 is a rising edge, the output terminal Q of the second D flip-flop 51 collects a digital signal "1" received by the data input terminal D of the second D flip-flop 51, and at this time, the data input terminal D of the second D flip-flop 51 is set to a digital signal "0"; when the periodic signal received by the clock input terminal CK of the second D flip-flop 51 is a falling edge, the output terminal Q of the second D flip-flop 51 holds the digital signal "1", and the data input terminal D of the second D flip-flop 51 holds the digital signal "0"; when the periodic signal received by the clock input terminal CK of the second D flip-flop 51 is a rising edge again, the output terminal Q of the second D flip-flop 51 collects the last state "0" of the data input terminal D of the second D flip-flop 51, and at this time, the data input terminal D of the second D flip-flop 51 is set to the digital signal "1"; when the periodic signal received by the clock input terminal CK of the second D flip-flop 51 is a falling edge again, the output terminal Q of the second D flip-flop 51 holds the digital signal "0", and the data input terminal D of the second D flip-flop 51 holds the digital signal "1"; when the third periodic signal received by the clock input CK of the second D flip-flop 51 is a rising edge, the output Q of the second D flip-flop 51 acquires the last state "1" of the data input D of the second D flip-flop 51, and at this time, the data input D of the second D flip-flop 51 is set to the digital signal "0".
When the initial state of the reset terminal RN of the second D flip-flop 51 is the digital signal "1", the working principle of the asynchronous reset flip-flop verification circuit is similar to that when the initial state of the reset terminal RN of the second D flip-flop 51 is the digital signal "0", and details thereof are not repeated. The asynchronous reset trigger verification circuit provided in this embodiment can complete verification of the second, third, and fourth rows of the truth table of the asynchronous trigger shown in fig. 2 by only leading out two ports, that is, the clock input terminal CK of the second D flip-flop 51 and the output terminal Q of the second D flip-flop 51, and configuring two sets of test vectors, thereby reducing the circuit area occupied for performing functional verification and shortening the test time.
Example 3
Fig. 7 is a schematic structural diagram of an asynchronous reset flip-flop verification circuit, where the asynchronous reset flip-flop verification circuit includes a first logic circuit and a second logic circuit connected in series. The input end of the first logic circuit is used as the input end IN3 of the asynchronous reset trigger verification circuit, the output end of the first logic circuit is connected with the input end of the second logic circuit, and the output end of the second logic circuit is used as the output end OUT3 of the asynchronous reset trigger verification circuit.
The first logic circuit includes a first D flip-flop 31, an or gate 32, and a first inverter 33. The data input end D of the first D flip-flop 31 receives a digital signal "1", the clock input end CK of the first D flip-flop 31 is connected to the first input end of the or gate 32 and serves as the input end of the first logic circuit, the reset end RN of the first D flip-flop 31 is connected to the output end of the or gate 32, the output end Q of the first D flip-flop 31 is connected to the input end of the first inverter 33 and serves as the output end of the first logic circuit, and the output end of the first inverter 33 is connected to the second input end of the or gate 32.
The second logic circuit includes a second D flip-flop 51 and a second inverter 52. A data input end D of the second D flip-flop 51 is connected to an output end of the second inverter 52, a clock input end CK of the second D flip-flop 51 serves as an input end of the second logic circuit, a reset end RN of the second D flip-flop 51 receives a digital signal "1", and an output end Q of the second D flip-flop 51 is connected to an input end of the second inverter 52 and serves as an output end of the second logic circuit.
When the first D flip-flop 31 and the second D flip-flop 51 are functionally verified, the input terminal IN3 of the asynchronous reset flip-flop verification circuit receives a periodic signal, which may be a clock signal. The operation principle of the first logic circuit is described with reference to embodiment 1, the operation principle of the second logic circuit is described with reference to embodiment 2, and a schematic diagram of a test vector of the asynchronous reset trigger verification circuit is shown in fig. 9. The asynchronous reset trigger verification circuit provided in this embodiment can complete verification of the truth table of the asynchronous trigger shown in fig. 2 by only leading out two ports, that is, the clock input terminal CK of the first D flip-flop 31 and the output terminal Q of the second D flip-flop 51, and configuring two sets of test vectors, thereby reducing the circuit area occupied for performing functional verification and shortening the test time.
Example 4
In this embodiment, another asynchronous reset trigger verification circuit is provided, and fig. 8 is a schematic structural diagram of the asynchronous reset trigger verification circuit, where the asynchronous reset trigger verification circuit includes a first logic circuit and a second logic circuit connected in series. The input end of the second logic circuit is used as the input end IN4 of the asynchronous reset trigger verification circuit, the output end of the second logic circuit is connected with the input end of the first logic circuit, and the output end of the first logic circuit is used as the output end OUT4 of the asynchronous reset trigger verification circuit.
The first logic circuit includes a first D flip-flop 31, an or gate 32, and a first inverter 33. The data input end D of the first D flip-flop 31 receives a digital signal "1", the clock input end CK of the first D flip-flop 31 is connected to the first input end of the or gate 32 and serves as the input end of the first logic circuit, the reset end RN of the first D flip-flop 31 is connected to the output end of the or gate 32, the output end Q of the first D flip-flop 31 is connected to the input end of the first inverter 33 and serves as the output end of the first logic circuit, and the output end of the first inverter 33 is connected to the second input end of the or gate 32.
The second logic circuit includes a second D flip-flop 51 and a second inverter 52. A data input end D of the second D flip-flop 51 is connected to an output end of the second inverter 52, a clock input end CK of the second D flip-flop 51 serves as an input end of the second logic circuit, a reset end RN of the second D flip-flop 51 receives a digital signal "1", and an output end Q of the second D flip-flop 51 is connected to an input end of the second inverter 52 and serves as an output end of the second logic circuit.
When the first D flip-flop 31 and the second D flip-flop 51 are functionally verified, the input terminal IN4 of the asynchronous reset flip-flop verification circuit receives a periodic signal, which may be a clock signal. The operation principle of the first logic circuit is described with reference to embodiment 1, the operation principle of the second logic circuit is described with reference to embodiment 2, and a schematic diagram of a test vector of the asynchronous reset trigger verification circuit is shown in fig. 9. The asynchronous reset trigger verification circuit provided in this embodiment can complete verification of the truth table of the asynchronous trigger shown in fig. 2 by only leading out two ports, that is, the clock input terminal CK of the second D flip-flop 51 and the output terminal Q of the first D flip-flop 31, and configuring two sets of test vectors, thereby reducing the circuit area occupied for performing functional verification and shortening the test time.
Example 5
This embodiment provides an integrated circuit verification apparatus, and fig. 10 is a schematic structural diagram of the integrated circuit verification apparatus. The integrated circuit verification device comprises a data distributor 11, a data selector 12 and M verification modules (a verification module 131, verification modules 132, … and a verification module 13M), wherein M is an integer not less than 2 and M is 2NN is the number of address signals and N is not less than 2.
The data input of the data distributor 11 serves as the input IN5 of the integrated circuit verification device; each address terminal of the data distributor 11 is correspondingly connected to an address terminal of the data selector 12 and is configured to receive an address signal, for example, a first address terminal of the data distributor 11 is correspondingly connected to a first address terminal of the data selector 12 and receives an address signal a1, and a second address terminal of the data distributor 11 is correspondingly connected to a second address terminal of the data selector 12 and receives an address signal a 2; each output end of the data distributor 11 is correspondingly connected to an input end of an authentication module, and each input end of the data selector 12 is correspondingly connected to an output end of an authentication module, for example, an input end of an authentication module 131 is connected to a first output end of the data distributor 11, and an output end of the authentication module 131 is connected to a first input end of the data selector 12; the output of the data selector 12 serves as the output of the integrated circuit verification means.
Each verification module may be the asynchronous reset trigger verification circuit provided in any embodiment 1 to embodiment 4, or a part of the M verification modules is the asynchronous reset trigger verification circuit provided in any embodiment 1 to embodiment 4, and a part of the M verification modules is other logic chain verification circuits, which is not limited in this embodiment.
The integrated circuit verification device provided in this embodiment may perform large-scale verification by using a path of periodic signals, decode the address signals through the data distributor 11, distribute the periodic signals for testing to the verification modules corresponding to the address signals, decode the address signals through the data selector 12, and select the output signals of the corresponding verification modules to output. The integrated circuit verification device provided by the embodiment realizes large-scale verification of a plurality of verification modules and improves verification efficiency.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. An asynchronous reset trigger verification circuit is characterized by comprising a first D trigger, an OR gate and a first inverter;
the data input end of the first D trigger receives a digital signal '1', the clock input end of the first D trigger is connected with the first input end of the OR gate and serves as the input end of the asynchronous reset trigger verification circuit, the reset end of the first D trigger is connected with the output end of the OR gate, the output end of the first D trigger is connected with the input end of the first phase inverter and serves as the output end of the asynchronous reset trigger verification circuit, and the output end of the first phase inverter is connected with the second input end of the OR gate.
2. The asynchronous reset flip-flop validation circuit of claim 1, wherein an input of the asynchronous reset flip-flop validation circuit is adapted to receive a periodic signal.
3. An asynchronous reset trigger verification circuit is characterized by comprising a second D trigger and a second inverter;
the data input end of the second D trigger is connected with the output end of the second phase inverter, the clock input end of the second D trigger serves as the input end of the asynchronous reset trigger verification circuit, the reset end of the second D trigger receives a digital signal '1', and the output end of the second D trigger is connected with the input end of the second phase inverter and serves as the output end of the asynchronous reset trigger verification circuit.
4. The asynchronous reset flip-flop validation circuit of claim 3, wherein an input of the asynchronous reset flip-flop validation circuit is adapted to receive a periodic signal.
5. An asynchronous reset trigger verification circuit is characterized by comprising a first logic circuit and a second logic circuit, wherein the first logic circuit and the second logic circuit are connected in series;
the first logic circuit comprises a first D flip-flop, an OR gate and a first phase inverter, wherein a data input end of the first D flip-flop receives a digital signal '1', a clock input end of the first D flip-flop is connected with a first input end of the OR gate and serves as an input end of the first logic circuit, a reset end of the first D flip-flop is connected with an output end of the OR gate, an output end of the first D flip-flop is connected with an input end of the first phase inverter and serves as an output end of the first logic circuit, and an output end of the first phase inverter is connected with a second input end of the OR gate;
the second logic circuit comprises a second D trigger and a second phase inverter, the data input end of the second D trigger is connected with the output end of the second phase inverter, the clock input end of the second D trigger is used as the input end of the second logic circuit, the reset end of the second D trigger receives a digital signal '1', and the output end of the second D trigger is connected with the input end of the second phase inverter and is used as the output end of the second logic circuit.
6. The asynchronous reset flip-flop verification circuit of claim 5, wherein an input of the first logic circuit is configured as an input of the asynchronous reset flip-flop verification circuit, an output of the first logic circuit is configured as an input of the second logic circuit, and an output of the second logic circuit is configured as an output of the asynchronous reset flip-flop verification circuit.
7. The asynchronous reset flip-flop verification circuit of claim 5, wherein an input of the second logic circuit is configured as an input of the asynchronous reset flip-flop verification circuit, an output of the second logic circuit is configured as an input of the first logic circuit, and an output of the first logic circuit is configured as an output of the asynchronous reset flip-flop verification circuit.
8. The asynchronous reset flip-flop validation circuit of claim 6 or 7, wherein an input of the asynchronous reset flip-flop validation circuit is adapted to receive a periodic signal.
9. The asynchronous reset flip-flop verification circuit of claim 6 or 7, wherein the magnitude of the digital signal "1" is a supply voltage.
10. An integrated circuit verification device comprising a data distributor, a data selector, M verification modules, and N address signals, wherein at least one of the M verification modules is the asynchronous reset flip-flop verification circuit of any one of claims 1 to 9, M and N are integers not less than 2, and M is 2N；
The data input end of the data distributor is used as the input end of the integrated circuit verification device, each address end of the data distributor is correspondingly connected with one address end of the data selector and is used for receiving one path of address signals, each output end of the data distributor is correspondingly connected with the input end of one verification module, each input end of the data selector is correspondingly connected with the output end of one verification module, and the output end of the data selector is used as the output end of the integrated circuit verification device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910086037.3A CN109884516B (en) | 2019-01-29 | 2019-01-29 | Asynchronous reset trigger verification circuit and integrated circuit verification device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910086037.3A CN109884516B (en) | 2019-01-29 | 2019-01-29 | Asynchronous reset trigger verification circuit and integrated circuit verification device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109884516A CN109884516A (en) | 2019-06-14 |
| CN109884516B true CN109884516B (en) | 2021-01-12 |
Family
ID=66927224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910086037.3A Active CN109884516B (en) | 2019-01-29 | 2019-01-29 | Asynchronous reset trigger verification circuit and integrated circuit verification device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109884516B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04355386A (en) * | 1991-05-31 | 1992-12-09 | Nec Corp | Test circuit for semiconductor device |
| JPH07306244A (en) * | 1994-05-10 | 1995-11-21 | Matsushita Electric Ind Co Ltd | Scan path flip-flop and flip-flop scan path chain |
| CN1457433A (en) * | 2000-07-26 | 2003-11-19 | 泰拉丁公司 | Automatic test equipment with narrow output pulses |
| CN1697319A (en) * | 2005-06-15 | 2005-11-16 | 清华大学 | D flip-flop with reset and/or set function based on conditional precharge structure |
| EP2030114B1 (en) * | 2006-06-09 | 2013-01-23 | Otrsotech, Limited Liability Company | Transparent test method and scan flip-flop |
| CN106100621A (en) * | 2016-07-22 | 2016-11-09 | 天津大学 | A kind of automatic reset structure for clock handoff procedure |
| CN107463236A (en) * | 2017-08-28 | 2017-12-12 | 珠海格力电器股份有限公司 | Reset detection circuit and reset detection method |
-
2019
- 2019-01-29 CN CN201910086037.3A patent/CN109884516B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04355386A (en) * | 1991-05-31 | 1992-12-09 | Nec Corp | Test circuit for semiconductor device |
| JPH07306244A (en) * | 1994-05-10 | 1995-11-21 | Matsushita Electric Ind Co Ltd | Scan path flip-flop and flip-flop scan path chain |
| CN1457433A (en) * | 2000-07-26 | 2003-11-19 | 泰拉丁公司 | Automatic test equipment with narrow output pulses |
| CN1697319A (en) * | 2005-06-15 | 2005-11-16 | 清华大学 | D flip-flop with reset and/or set function based on conditional precharge structure |
| EP2030114B1 (en) * | 2006-06-09 | 2013-01-23 | Otrsotech, Limited Liability Company | Transparent test method and scan flip-flop |
| CN106100621A (en) * | 2016-07-22 | 2016-11-09 | 天津大学 | A kind of automatic reset structure for clock handoff procedure |
| CN107463236A (en) * | 2017-08-28 | 2017-12-12 | 珠海格力电器股份有限公司 | Reset detection circuit and reset detection method |
Non-Patent Citations (2)
| Title |
|---|
| 一种抗单粒子全加固D触发器的设计;张英武;《固体电子学研究与进展》;20091231;全文 * |
| 数字集成电路中触发器应用;和春华;《云南师范大学学报》;20061130;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109884516A (en) | 2019-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102970013B (en) | Resetting method and resetting control device of register inside chip based on scanning chain | |
| WO2015188163A1 (en) | Systems and methods involving multi-bank, dual-pipe memory circuitry | |
| CN112885396B (en) | Shift register, arithmetic unit and chip | |
| CN109905116B (en) | Programmable pipeline interface circuit | |
| CN114121132B (en) | Test circuit, test device and test method | |
| CN114113989B (en) | DFT test device, test system and test method | |
| CN107665033A (en) | It is a kind of that there is the Digital Logical Circuits module for resetting deburring function | |
| JPH07504076A (en) | Dual edge-triggered memory device and system | |
| CN102841306B (en) | Testing and locating method for FPGA (field programmable gate array) programmable logic unit | |
| US20150206559A1 (en) | Register file module and method therefor | |
| CN111512552A (en) | Selectively providing clock signals using programmable control circuitry | |
| CN107562163B (en) | Digital logic circuit with stable reset control | |
| CN112290922A (en) | Parallel input and serial output circuit and memory using the same | |
| CN108574477B (en) | Configurable delay line | |
| WO2018191683A2 (en) | Circuit for meeting setup and hold times of a control signal with respect to a clock | |
| CN109884516B (en) | Asynchronous reset trigger verification circuit and integrated circuit verification device | |
| CN111624478A (en) | Clock signal control circuit and equipment | |
| CN112019194A (en) | High-speed series circuit | |
| US12092689B2 (en) | Scan test in a single-wire bus circuit | |
| CN214068353U (en) | Shift register, arithmetic unit and chip | |
| KR100840030B1 (en) | Programmable logic circuit | |
| CN104333373B (en) | A kind of T triggers and the frequency divider using the T triggers | |
| US20180191352A1 (en) | Field programmable gate array comprising plurality of functional blocks, and control device for a power plant | |
| JP2011002261A (en) | Scan test circuit, and method and program for designing the same | |
| CN101916588B (en) | In-system-programming (ISP) module and method thereof for in-system-programming of FPAA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |