CN118554919B - High-speed low-power consumption master-slave D trigger - Google Patents

Abstract

The invention discloses a high-speed low-power consumption master-slave D trigger, which comprises a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit, wherein the data input circuit is connected with the master trigger circuit; the data input circuit, the master trigger circuit, the slave trigger circuit and the data output circuit are connected in sequence; a data input circuit for receiving a data input signal; a data output circuit for outputting an output signal from the trigger circuit; the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK; when the clock signal CK is in a low level, the master trigger circuit receives a data input signal, and the slave trigger circuit is in a maintenance state; when the clock signal CK is at a high level, the master flip-flop is in a hold state, and the slave flip-flop receives the memory state of the master flip-flop. The invention has the advantages of high speed, low power consumption and the like.

Description

A high-speed and low-power master-slave D flip-flop

Technical Field

The invention mainly relates to the technical field of digital circuit design, and in particular to a high-speed and low-power master-slave D flip-flop.

Background Art

Since the advent of CMOS integrated circuit technology, the trigger has always been one of the core components of digital integrated circuits. It is the basic unit for realizing sequential logic such as pipelines, state machines, counters, and register files. Its speed directly affects the performance of digital circuits and chips. There are many types of triggers in digital circuits, and the most common ones are RS triggers, JK triggers, D triggers, and T triggers. According to the different structures of the trigger circuits, they are divided into master-slave triggers, sensitive amplifier triggers, and maintenance blocking triggers. Among them, the master-slave D trigger is the most applicable and widely used in digital integrated circuit technology.

Figure 1 shows a schematic diagram of a D flip-flop circuit unit. Figure 2 shows the basic circuit structure of a traditional D flip-flop circuit unit widely used in the design of commercial digital circuit standard cell libraries at various process nodes, usually called a conventional transmission-gate flip-flop (TGFF). The advantage of this structure is its simple structure, but its disadvantage is that it requires a complementary clock signal. The complementary clock signal flips at every clock beat, which not only causes excessive clock load but also high dynamic power consumption. Therefore, the academic community has tried other circuit structures to reduce the clock load and improve certain characteristics of the flip-flop.

H. Kawaguchi proposed a flip-flop circuit driven by a low-voltage swing clock signal (see H.Kawaguchi and T. Sakurai: “A Reduced Clock-Swing Flip-Flop (RCSFF) for 63%Power Reduction”, IEEE Journal of solid-state circuits, vol.33, no.5 1988, pp.807-811). On this basis, J. Kim et al. proposed a flip-flop circuit driven by a half-swing clock signal (see J.-C. Kim, S.-H. Lee, and H.-J. Park, “A low-power half-swing clocking scheme for flip-flop with complementary gate and source drive,” IEICE Trans.Electronics, vol. E82-C, no. 9, pp. 1777–1779, Sep. 1999). However, the low voltage swing increases the voltage threshold and increases the design complexity. Combined with the sensitive amplification technology proposed by M. Matsui et al. (see M.Matsui, H. Hara, et. al, “A 200 MHz 13 mm 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme,” IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1482–1490, Dec. 1994), a trigger design scheme based on sensitive amplification technology under conventional voltage swing can be obtained. The structure is shown in Figure 3 and is called Differential Sense-Amplifying Flip-Flop (DSAFF). This circuit uses differential input and uses sensitive amplification technology to cleverly avoid complementary clock signals, thereby achieving the purpose of saving power; however, the sensitive amplification technology in this circuit structure has stringent requirements on the size of transistors, and the sensitive amplification effect is often greatly affected by process fluctuations.

Summary of the invention

The technical problem to be solved by the present invention is: in view of the technical problems existing in the prior art, the present invention provides a high-speed, low-power master-slave D flip-flop with low power consumption and low delay.

In order to solve the above technical problems, the technical solution proposed by the present invention is:

A high-speed, low-power master-slave D flip-flop, comprising a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit; the data input circuit, the master trigger circuit, the slave trigger circuit and the data output circuit are connected in sequence;

A data input circuit is used to receive a data input signal; a data output circuit is used to output an output signal from the trigger circuit;

Both the master trigger circuit and the slave trigger circuit are controlled by the clock signal CK;

When the clock signal CK is at a low level, the master trigger circuit receives the data input signal, and the slave trigger circuit is in a holding state;

When the clock signal CK is at a high level, the master trigger circuit is in a holding state, and the slave trigger circuit receives the storage state of the master trigger circuit;

The main trigger circuit includes PMOS tubes MP2-MP6 and NMOS tubes MN2-MN6;

The substrate and source of the PMOS tube MP2 are connected to the power supply VDD, the gate is driven by the signal ml_b, and the drain is driven by the signal v1;

The substrate and source of the PMOS tube MP3 are connected to the power supply VDD, the gate is driven by the signal ml_ax, and the drain is driven by the signal v2;

The substrate of the PMOS tube MP6 is connected to the power supply VDD, the gate is controlled by the clock signal CK, the source is connected to the signal v1, and the drain is connected to the signal v2;

The substrate and source of the PMOS tube MP4 are connected to the power supply VDD, the gate is driven by the signal dn, and the drain is driven by the signal ml_b;

The substrate and source of the PMOS tube MP5 are connected to the power supply VDD, the gate is driven by the signal ml_b, and the drain is driven by the signal ml_ax;

The substrate and source of NMOS tube MN6 are grounded to VSS, and the gate is controlled by the clock signal CK;

The substrate of the NMOS tube MN2 is grounded to VSS, the gate is driven by the signal ml_b, the drain is driven by the signal dn, and the source is connected to the drain of the NMOS tube MN6;

The substrate of the NMOS tube MN3 is grounded to VSS, the gate is driven by the signal ml_ax, the drain is driven by the signal ml_b, and the source is connected to the drain of the NMOS tube MN6;

The substrate and source of NMOS tube MN4 are grounded to VSS, the gate is driven by signal dn, and the drain is driven by signal ml_b;

The substrate and source of NMOS tube MN5 are grounded to VSS, the gate is driven by signal ml_b, and the drain is driven by signal ml_ax;

The signal ml_ax and the signal ml_b are a complementary signal pair in the main trigger circuit.

Preferably, the data input circuit includes a PMOS transistor MP1 and an NMOS transistor MN1;

The substrate of the PMOS tube MP1 is connected to the power supply VDD, the source is driven by the signal v1, the gate is controlled by the data input signal D, and the drain is driven by the signal dn;

The substrate and source of the NMOS tube MN1 are grounded to VSS, the gate is controlled by the data input signal D, and the drain is driven by the signal dn.

Preferably, the data input circuit includes an inverter X2 and PMOS tubes MP13-MP16;

Inverter X2, used for generating a complementary signal sen of the enable signal SE;

The substrate of the PMOS tube MP15 is connected to the power supply VDD, the source is connected to the signal v1, and the gate is controlled by the enable signal SE;

The substrate of the PMOS tube MP16 is connected to the power supply VDD, the source is connected to the signal v1, and the gate is controlled by the scanning signal SI;

The substrate of the PMOS tube MP13 is connected to the power supply VDD, the source is connected to the drain of the PMOS tube MP15, and the gate is controlled by the data input signal D; and the drain drive signal dn;

The substrate of the PMOS tube MP14 is connected to the power supply VDD, the source is connected to the drain of the PMOS tube MP16, the gate is controlled by the signal sen; and the drain drives the signal dn;

The substrate and source of the NMOS tube MN15 are connected to the power supply VSS, and the gate is controlled by the complementary signal sen of the enable signal SE;

The substrate and source of the NMOS tube MN16 are connected to the power supply VSS, and the gate is controlled by the scan signal SI;

The substrate of the NMOS tube MN13 is connected to the power supply VSS, the source is connected to the drain of the NMOS tube MN15, the gate is controlled by the data input signal D, and the drain is driven by the signal dn;

The substrate of the NMOS tube MN14 is connected to the power supply VSS, the source is connected to the drain of the NMOS tube MN16, the gate is controlled by the enable signal SE, and the drain is driven by the signal dn.

Preferably, the slave trigger circuit includes PMOS tubes MP7-MP8 and NMOS tubes MN7-MN12;

The substrate and source of the NMOS tube MN12 are grounded to VSS, and the gate is connected to the clock signal CK;

The substrate and source of the NMOS tube MN7 are grounded to VSS, the gate is driven by the signal sl_a, and the drain is driven by the signal sl_bx;

The substrate and source of NMOS tube MN8 are grounded to VSS, the gate is driven by the signal sl_bx, and the drain is driven by the signal sl_a;

The substrate of the NMOS tube MN9 is grounded to VSS, the gate is connected to the signal ml_b, and the source is connected to the drain of the NMOS tube MN12, and the drain drives the signal sl_bx;

The substrate of the NMOS tube MN10 is grounded to VSS, the gate is connected to the signal ml_ax, the source is connected to the drain of the NMOS tube MN12, and the drain drives the signal sl_a;

The substrate of NMOS tube MN11 is grounded to VSS, the gate is controlled by the clock signal CK, the source is connected to the signal v1, and the drain is driven by the signal sl_bx;

The substrate of the PMOS tube MP7 is connected to the power supply VDD, the source is driven by the signal v1, the gate is driven by the signal sl_a, and the drain is driven by the signal sl_bx;

The substrate of the PMOS tube MP8 is connected to the power supply VDD, the source is driven by the signal v2, the gate is driven by the signal sl_bx, and the drain is driven by the signal sl_a;

Signal sl_bx and signal sl_a are a complementary signal pair in the slave trigger circuit.

Preferably, the data output circuit comprises an inverter X1, an input end of the inverter X1 is driven by a signal sl_bx, and an output end drives an output signal Q.

The working principle of the high-speed and low-power master-slave D flip-flop described in the present invention is specifically as follows:

When the clock signal CK is at a low level, MP6 is turned on, making the level values of signals v1 and v2 the same; MP2 and MP3 are controlled by the complementary signal pair ml_ax and ml_b, one of which must be turned on, and the level values of signals v1 and v2 are high levels; at this time, signal dn is affected by the data input signal D and is the reverse signal of the data input signal D;

When the data input signal D is at a high level, the signal dn is at a low level, MN4 is turned off and MP4 is turned on, the signal ml_b is pulled up to a high level, MN5 is driven to be turned on, and the signal ml_ax is pulled down to a low level; when the data input signal is at a low level, the signal dn is at a high level, MP4 is turned off and MN4 is turned on, the signal ml_b is pulled down to a low level, MP5 is driven to be turned on, and the signal ml_ax is pulled up to a high level; that is, when the clock signal CK is at a low level, the main trigger circuit samples the data input signal and updates the state; at the same time, when the clock signal CK is at a low level, the level values of the signals v1 and v2 are both high levels, and MP7, MN7, MP8, and MN8 constitute two inverters connected in the first position, so that the slave trigger circuit maintains the state and drives the inverter X1 to maintain the output signal Q value;

When the clock signal CK is at a high level, MP6 is turned off, MP2 and MP3 are controlled by the complementary signal pair ml_b and ml_ax, and the level values of signals v1 and v2 are different; when the signal ml_b is at a low level, MP2 is turned on and MP3 is turned off. When the data input signal D jumps from a low level to a high level, the signal dn is pulled down to a low level, and MP4 is turned on. Since MP3 is turned off, the jump of the data input signal D will not change the state of the signal ml_b; when the signal ml_b is at a high level, MP2 is turned off and MP3 is turned on. When the data input signal jumps from a high level to a low level, MN1 is turned off and MP1 is turned on. Since MP2 is turned off, the jump of the data input signal D will not cause the state of the signal dn to change; that is, when the clock signal CK is at a high level, the state of the main trigger circuit will not receive the change of the data input signal D;

At the same time, when the clock signal CK is at a high level, MN12 is turned on, driving the slave trigger circuit to update the status; when the signal ml_b is at a high level, MP2 and MN10 are turned off and MN9 is turned on, the pull-up path of the signal sl_bx is turned off and the pull-down path is turned on, and then it is pulled down to a low level, so MP8 is turned on and MN8 is turned off, and the signal sl_a is pulled up to a high level to complete the data update; when the signal ml_b is at a low level, MP2 and MN10 are turned on and MN9 is turned off, because MN11 is turned on, the signal sl_bx is pulled up to a high level, and the signal sl_a is pulled down to a low level to complete the data update; that is, when the clock signal CK is at a high level, the slave trigger circuit completes the data update.

Compared with the prior art, the advantages of the present invention are:

Compared with the traditional D flip-flop TGFF, the high-speed and low-power master-slave D flip-flop of the present invention can effectively overcome the disadvantage of high power consumption caused by excessive clock load of the traditional D flip-flop, reduce the clock load, reduce the number of transistors, and have fewer clock-controlled transistors, saving power consumption; at the same time, at the rising edge of the clock, only two levels of reverse logic are needed to transmit the input change to the output Q, and the delay characteristics are improved. It is very suitable as a standard unit of digital circuits and is suitable for application in the design of chips such as CPU, GPU, and ASIC.

Compared with the differential sensitive amplifier trigger DSAFF, the high-speed and low-power master-slave D trigger of the present invention has the same number of transistors, but has lower power consumption due to the absence of a clock pre-charge tube.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a conventional trigger circuit unit; wherein D is a data input signal, CK is a clock signal, and Q is an output signal.

FIG. 2 is a circuit diagram of a conventional D flip-flop TGFF.

FIG. 3 is a circuit diagram of a conventional differential sensitive amplifier trigger DSAFF.

FIG4 is a circuit diagram of a high-speed, low-power master-slave D flip-flop in Embodiment 1 of the present invention.

FIG5 is a circuit diagram of a high-speed, low-power master-slave D flip-flop with a scan structure in the second embodiment of the present invention.

DETAILED DESCRIPTION

The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

Embodiment 1:

As shown in FIG4 , the high-speed, low-power master-slave D flip-flop of the embodiment of the present invention comprises a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit; the data input circuit, the master trigger circuit, the slave trigger circuit and the data output circuit are connected in sequence;

A data input circuit for receiving a data input signal D; a data output circuit for outputting an output result from the trigger circuit;

Both the master trigger circuit and the slave trigger circuit are controlled by the clock signal CK;

When the clock signal CK is at a low level, the master trigger circuit receives data input, while the slave trigger circuit is in a holding state;

When the clock signal CK is at a high level, the main trigger circuit is not affected by the input signal and is in a holding state, while the slave trigger circuit receives the storage state of the main trigger circuit, so that the trigger state is updated.

Specifically, the data input circuit includes a PMOS tube MP1 and an NMOS tube MN1;

The substrate of the PMOS tube MP1 is connected to the power supply VDD, the source is driven by the signal v1, the gate is controlled by the data input signal D, and the drain is driven by the signal dn;

The substrate and source of the NMOS tube MN1 are grounded to VSS, the gate is controlled by the data input signal D, and the drain is driven by the signal dn.

Specifically, the main trigger circuit includes PMOS tubes MP2-MP6, and NMOS tubes MN2-MN6;

The substrate and source of the PMOS tube MP2 are connected to the power supply VDD, the gate is driven by the signal ml_b, and the drain is driven by the signal v1;

The substrate and source of the PMOS tube MP3 are connected to the power supply VDD, the gate is driven by the signal ml_ax, and the drain is driven by the signal v2;

The substrate of the PMOS tube MP6 is connected to the power supply VDD, the gate is controlled by the clock signal CK, the source is connected to the signal v1, and the drain is connected to the signal v2;

The substrate and source of the PMOS tube MP4 are connected to the power supply VDD, the gate is driven by the signal dn, and the drain is driven by the signal ml_b;

The substrate and source of the PMOS tube MP5 are connected to the power supply VDD, the gate is driven by the signal ml_b, and the drain is driven by the signal ml_ax;

The substrate and source of NMOS tube MN6 are grounded to VSS, and the gate is controlled by the clock signal CK;

The substrate of the NMOS tube MN2 is grounded to VSS, the gate is driven by the signal ml_b, the drain is driven by the signal dn, and the source is connected to the drain of the NMOS tube MN6;

The substrate of the NMOS tube MN3 is grounded to VSS, the gate is driven by the signal ml_ax, the drain is driven by the signal ml_b, and the source is connected to the drain of the NMOS tube MN6;

The substrate and source of NMOS tube MN4 are grounded to VSS, the gate is driven by signal dn, and the drain is driven by signal ml_b;

The substrate and source of the NMOS tube MN5 are grounded to VSS, the gate is driven by the signal ml_b, and the drain is driven by the signal ml_ax.

Specifically, the slave trigger circuit includes PMOS tubes MP7-MP8, and NMOS tubes MN7-MN12;

The substrate and source of the NMOS tube MN12 are grounded to VSS, and the gate is connected to the clock signal CK;

The substrate and source of the NMOS tube MN7 are grounded to VSS, the gate is driven by the signal sl_a, and the drain is driven by the signal sl_bx;

The substrate and source of NMOS tube MN8 are grounded to VSS, the gate is driven by the signal sl_bx, and the drain is driven by the signal sl_a;

The substrate of the NMOS tube MN9 is grounded to VSS, the gate is connected to the signal ml_b, and the source is connected to the drain of the NMOS tube MN12, and the drain drives the signal sl_bx;

The substrate of the NMOS tube MN10 is grounded to VSS, the gate is connected to the signal ml_ax, and the source is connected to the drain of the NMOS tube MN12, and the drain drives the signal sl_a;

The substrate of NMOS tube MN11 is grounded to VSS, the gate is controlled by the clock signal CK, the source is connected to the signal v1, and the drain is driven by the signal sl_bx;

The substrate of the PMOS tube MP7 is connected to the power supply VDD, the source is driven by the signal v1, the gate is driven by the signal sl_a, and the drain is driven by the signal sl_bx;

The substrate of the PMOS tube MP8 is connected to the power supply VDD, the source is driven by the signal v2, the gate is driven by the signal sl_bx, and the drain is driven by the signal sl_a.

Specifically, the data output circuit includes an inverter X1, an input end of the inverter X1 is driven by a signal sl_bx, and an output end drives an output signal Q.

Specifically, signal ml_ax and signal ml_b are a complementary signal pair in the master trigger circuit; when the level value of signal ml_ax is low, the level value of signal ml_b is high; conversely, when the level value of signal ml_ax is high, the level value of signal ml_b is low; similarly, signal sl_bx and signal sl_a are a complementary signal pair in the slave trigger circuit.

In specific applications, when the clock signal CK is at a low level, MP6 is turned on, so that the level values of signals v1 and v2 are the same; because MP2 and MP3 are controlled by the complementary signal pair ml_ax and ml_b, one of them must be turned on, so the level values of signals v1 and v2 are high levels. At this time, the signal dn is affected by the data input signal D and is the reverse signal of signal D. When the data input signal is at a high level, the signal dn is at a low level, MN4 is cut off and MP4 is turned on, the signal ml_b is pulled up to a high level, driving MN5 to turn on, and pulling the signal ml_ax down to a low level; when the data input signal is at a low level, the signal dn is at a high level, MP4 is cut off and MN4 is turned on, the signal ml_b is pulled down to a low level, driving MP5 to turn on, and pulling the signal ml_ax up to a high level. Therefore, when the clock signal CK is at a low level, the main trigger circuit samples the data input signal D and updates the state;

At the same time, when the clock signal CK is at a low level, the level values of the above signals v1 and v2 are both at a high level, so MP7, MN7, MP8, and MN8 form two first-connected inverters, so that the slave trigger circuit maintains the state and drives the inverter X1 to maintain the Q value.

When the clock signal CK is at a high level, MP6 is turned off, because MP2 and MP3 are controlled by the complementary signal pair ml_b and ml_ax, and the level values of signals v1 and v2 are different. When the signal ml_b is at a low level, MP2 is turned on and MP3 is turned off. When the data input signal D jumps from a low level to a high level, the signal dn is pulled down to a low level. Although MP4 is turned on, because MP3 is turned off, the jump of the input signal D will not change the state of the signal ml_b. When the signal ml_b is at a high level, MP2 is turned off and MP3 is turned on. When the data input signal D jumps from a high level to a low level, MN1 is turned off and MP1 is turned on. However, because MP2 is turned off, the state of the signal dn does not change due to the change of the input signal D. Therefore, when the clock signal CK is at a high level, the state of the main trigger circuit will not receive changes in the data input;

At the same time, when the clock signal CK is at a high level, MN12 is turned on, driving the slave trigger circuit to update the state. When the signal ml_b is at a high level, MP2 and MN10 are turned off and MN9 is turned on, the pull-up path of the signal sl_bx is turned off and the pull-down path is turned on, and then it is pulled down to a low level, so MP8 is turned on and MN8 is turned off, and the signal sl_a is pulled up to a high level to complete the data update; when the signal ml_b is at a low level, MP2 and MN10 are turned on and MN9 is turned off. Because MN11 is turned on, the signal sl_bx is pulled up to a high level, and the signal sl_a is pulled down to a low level to complete the data update. Therefore, when the clock signal CK is at a high level, the slave trigger circuit completes the data update. Because the main trigger circuit is always in a holding state, the signals ml_b and ml_ax are not affected by the data input signal D and remain stable, so the state update of the slave trigger circuit occurs at the moment when the CK signal changes from a low level to a high level, that is, the trigger of the present invention is a D trigger triggered by a rising edge.

Compared with the traditional D flip-flop TGFF, the Fast Low-Power Master-Slave D flip-flop (FLPMSFF) of the present invention can effectively overcome the disadvantage of high power consumption caused by excessive clock load of the traditional D flip-flop, reduce the clock load, reduce the number of transistors, and have fewer clock-controlled transistors, thereby saving power consumption; at the same time, at the rising edge of the clock, only two levels of reverse logic are needed to transmit the input change to the output Q, and the delay characteristics are improved, so the device is very suitable as a standard unit of a digital circuit and is suitable for application in the design of chips such as CPU, GPU, and ASIC.

Compared with the differential sensitive amplifier trigger DSAFF, the high-speed and low-power master-slave D flip-flop (FLPMSFF) of the present invention has the same number of transistors, but has lower power consumption due to the absence of a clock pre-charge tube.

Embodiment 2:

The D flip-flop in Example 1 is easily expanded into a high-speed, low-power master-slave D flip-flop with a scan structure, thereby supporting a wide range of testability design requirements in digital integrated circuit design. The circuit structure diagram of the high-speed, low-power master-slave D flip-flop with a scan structure is shown in FIG5 , and only the data input circuit has changed compared to the original flip-flop. Specifically, the data input circuit includes an inverter X2, and PMOS tubes MP13-MP16;

Inverter X2, used for generating a complementary signal sen of the enable signal SE;

PMOS tube MP15, substrate connected to power supply VDD, source connected to signal v1, gate controlled by enable signal SE;

PMOS tube MP16, substrate connected to power supply VDD, source connected to signal v1, gate controlled by scanning signal SI;

The PMOS tube MP13 has a substrate connected to the power supply VDD, a source connected to the drain of the MP15 tube, and a gate controlled by a data input signal D; and a drain drive signal dn;

The PMOS tube MP14 has a substrate connected to the power supply VDD, its source is connected to the drain of the MP16 tube, and the gate is controlled by the signal sen; while the drain drives the signal dn;

NMOS tube MN15, the substrate and source are connected to the power supply VSS, and the gate is controlled by the complementary signal sen of the enable signal SE;

NMOS tube MN16, the substrate and source are connected to the power supply VSS, and the gate is controlled by the scanning signal SI;

NMOS tube MN13, the substrate is connected to the power supply VSS, its source is connected to the drain of MN15 tube, and the gate is controlled by the data input signal D; and the drain drive signal dn;

The NMOS tube MN14 has a substrate connected to the power supply VSS, a source connected to the drain of the MN16 tube, a gate controlled by an enable signal SE, and a drain drive signal dn.

In order to compare the performance characteristics of the FLPMSFF proposed in the present invention, SPICE simulation analysis and comparison are performed on the traditional D flip-flop TGFF, the differential sensitive amplifier flip-flop DSAFF and the FLPMSFF of the present invention respectively based on the circuit simulation tool HSPICE under a commercial FinFET bulk silicon process. The analysis results are shown in Table 1:

Table 1 Comparison of transistor count, CK2Q delay and power consumption simulation results

As shown in the comparative data in Table 1, compared with the traditional D flip-flop, the number of flip-flop transistors of the present invention is reduced by 8%, and the number of clock-controlled transistors is reduced by 66.7%. In the circuit simulation, the clock signal CK is a quasi-square wave signal with a frequency of 2GHz, a duty cycle of 50%, and a rise/fall transition time of 20ps; the data input signal D is a quasi-square wave signal with a duty cycle of 50%, and a rise/fall transition time of 50ps; a 10fF capacitor is mounted at the output end of the flip-flop circuit as a load.

Under the same conditions, the power consumption of the high-speed, low-power master-slave D flip-flop FLPMSFF of the present invention is reduced by 14% compared with the traditional D flip-flop TGFF; and the power consumption is reduced by 12% compared with the differential sensitive amplifier flip-flop DSAFF. Therefore, the high-speed, low-power master-slave D flip-flop of the present invention has a smaller area, lower power consumption, and smaller CK2Q delay than the traditional D flip-flop, and is more suitable for the design of standard cell libraries, and has broad prospects in digital integrated circuit design and chip design.

The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (5)

1. The high-speed low-power consumption master-slave D trigger is characterized by comprising a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit; the data input circuit, the master trigger circuit, the slave trigger circuit and the data output circuit are connected in sequence;

a data input circuit for receiving a data input signal; a data output circuit for outputting an output signal from the trigger circuit;

the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK;

When the clock signal CK is in a low level, the master trigger circuit receives a data input signal, and the slave trigger circuit is in a maintenance state;

When the clock signal CK is at a high level, the main trigger circuit is in a maintenance state, and the slave trigger circuit receives a storage state of the main trigger circuit;

The main trigger circuit comprises PMOS transistors MP2-MP6 and NMOS transistors MN2-MN6;

The PMOS tube MP2 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_b, and the drain electrode is driven by a signal v1;

The PMOS tube MP3 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_ax, and the drain electrode is driven by a signal v2;

the substrate of the PMOS tube MP6 is connected with a power supply VDD, the grid is controlled by a clock signal CK, the source electrode is connected with a signal v1, and the drain electrode is connected with a signal v2;

the PMOS tube MP4 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal dn, and the drain electrode is driven by a signal ml_b;

The PMOS tube MP5 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_b, and the drain electrode is driven by a signal ml_ax;

The substrate and the source electrode of the NMOS tube MN6 are grounded to VSS, and the grid electrode is controlled by a clock signal CK;

The substrate of the NMOS tube MN2 is grounded to VSS, the grid electrode is driven by a signal ml_b, the drain electrode drives a signal dn, and the source electrode is connected with the drain electrode of the NMOS tube MN 6;

The substrate of the NMOS tube MN3 is grounded to VSS, the grid electrode is driven by a signal ml_ax, the drain electrode is driven by a signal ml_b, and the source electrode is connected with the drain electrode of the NMOS tube MN 6;

The substrate and the source electrode of the NMOS tube MN4 are grounded to VSS, the grid electrode is driven by a signal dn, and the drain electrode is driven by a signal ml_b;

The substrate and the source electrode of the NMOS tube MN5 are grounded to VSS, the grid electrode is driven by a signal ml_b, and the drain electrode is driven by a signal ml_ax;

wherein signal ml_ax and signal ml_b are complementary signal pairs in the primary trigger circuit;

The secondary trigger circuit comprises PMOS transistors MP7-MP8 and NMOS transistors MN7-MN12;

NMOS transistor MN12 substrate and source ground VSS, the grid electrode is connected with a clock signal CK;

the substrate and the source electrode of the NMOS tube MN7 are grounded and VSS, the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;

The substrate and the source electrode of the NMOS tube MN8 are grounded and the grid electrode is driven by a signal sl_bx, and the drain electrode drives a signal sl_a;

NMOS transistor MN9 has substrate grounded VSS, gate connected to signal ml_b, source connected to drain of NMOS transistor MN12, drain driving signal sl_bx;

The substrate of the NMOS tube MN10 is grounded to VSS, the grid electrode is connected with a signal ml_ax, the source electrode is connected with the drain electrode of the NMOS tube MN12, and the drain electrode drives the signal sl_a;

The substrate of the NMOS tube MN11 is grounded to VSS, the grid is controlled by a clock signal CK, the source electrode is connected with a signal v1, and the drain electrode is driven by a signal sl_bx;

The PMOS tube MP7 substrate is connected with a power supply VDD, the source electrode is driven by a signal v1, the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;

the PMOS tube MP8 substrate is connected with a power supply VDD, the source electrode is driven by a signal v2, the grid electrode is driven by a signal sl_bx, and the drain electrode is driven by a signal sl_a;

The signal sl_bx and the signal sl_a are complementary signal pairs in the slave flip-flop.

2. The high-speed low-power consumption master-slave D flip-flop according to claim 1, wherein said data input circuit comprises a PMOS transistor MP1 and an NMOS transistor MN1;

the PMOS tube MP1 substrate is connected with a power supply VDD, the source electrode is driven by a signal v1, the grid electrode is controlled by a data input signal D, and the drain electrode is driven by a signal dn;

The substrate and the source of the NMOS transistor MN1 are grounded to VSS, the grid is controlled by a data input signal D, and the drain electrode drives a signal dn.

3. The high-speed low-power consumption master-slave D trigger according to claim 1, wherein the data input circuit comprises an inverter X2 and PMOS tubes MP13-MP16;

an inverter X2 for generating a complementary signal sen of the enable signal SE;

The substrate of the PMOS tube MP15 is connected with a power supply VDD, the source electrode is connected with a signal v1, and the grid electrode is controlled by an enabling signal SE;

the substrate of the PMOS tube MP16 is connected with a power supply VDD, the source electrode is connected with a signal v1, and the grid electrode is controlled by a scanning signal SI;

the substrate of the PMOS tube MP13 is connected with a power supply VDD, the source electrode is connected with the drain electrode of the PMOS tube MP15, and the grid electrode is controlled by a data input signal D; and a drain driving signal dn;

the substrate of the PMOS tube MP14 is connected with a power supply VDD, the source electrode is connected with the drain electrode of the PMOS tube MP16, and the grid electrode is controlled by a signal sen; and a drain driving signal dn;

The substrate and the source electrode of the NMOS transistor MN15 are grounded to VSS, and the grid electrode is controlled by a complementary signal sen of an enable signal SE;

The substrate and the source electrode of the NMOS tube MN16 are grounded to VSS, and the grid electrode is controlled by a scanning signal SI;

The substrate of the NMOS tube MN13 is grounded to VSS, the source electrode is connected with the drain electrode of the NMOS tube MN15, the grid electrode is controlled by a data input signal D, and the drain electrode drives a signal dn;

the substrate of the NMOS tube MN14 is grounded to VSS, the source electrode is connected with the drain electrode of the NMOS tube MN16, the grid electrode is controlled by an enabling signal SE, and the drain electrode drives a signal dn.

4. A high-speed low-power-consumption master-slave D flip-flop according to claim 1 or 2 or 3, characterized in that the data output circuit comprises an inverter X1, the input of which inverter X1 is driven by a signal sl_bx and the output of which drives an output signal Q.

5. The method for applying the high-speed low-power consumption master-slave D flip-flop according to claim 4, wherein:

When the clock signal CK is at a low level, MP6 is turned on so that the level values of the signals v1 and v2 are the same; MP2 and MP3 are controlled by complementary signal pairs ml_ax and ml_b, wherein one of them is conducted, and the level value of the signals v1 and v2 is high; at this time, the signal dn is affected by the data input signal, and is an inverse signal of the data input signal;

When the data input signal is at a high level, the signal dn is at a low level, the MN4 is turned off and the MP4 is turned on, the signal ml_b is pulled up to a high level, the MN5 is driven to be turned on, and the signal ml_ax is pulled down to a low level; when the data input signal is at low level, the signal dn is at high level, MP4 is turned off and MN4 is turned on, the signal ml_b is pulled down to low level, MP5 is driven to be turned on, and the signal ml_ax is pulled up to high level; that is, when the clock signal CK is at a low level, the main trigger circuit samples the data input signal and updates the state; meanwhile, when the clock signal CK is at a low level, the level values of the signals v1 and v2 are both at a high level, and MP7, MN7, MP8 and MN8 form two inverters connected end to end, so that the slave flip-flop circuit maintains a state and drives the inverter X1 to maintain the Q value of an output signal;

When the clock signal CK is at a high level, the MP6 is turned off, the MP2 and the MP3 are controlled by complementary signal pairs ml_b and ml_ax, and the level values of the signals v1 and v2 are different; when the signal ml_b is at a low level, MP2 is turned on and MP3 is turned off, when the data input signal jumps from a low level to a high level, the signal dn is pulled down to a low level, MP4 is turned on, and the data input signal D does not change the state of the signal ml_b due to MP3 being turned off; when the signal ml_b is at a high level, MP2 is turned off and MP3 is turned on, when the data input signal jumps from a high level to a low level, MN1 is turned off and MP1 is turned on, and the jump of the data input signal D does not cause the state change of the signal dn due to the MP2 being turned off; that is, when the clock signal CK is at a high level, the state of the main flip-flop circuit does not receive a change in the data input;

Meanwhile, when the clock signal CK is at a high level, the MN12 is conducted to drive the slave trigger circuit to update the state; when the signal ml_b is at a high level, MP2 and MN10 are turned off and MN9 is turned on, the pull-up path of the signal sl_bx is turned off and the pull-down path is turned on, and then pulled down to a low level, so that MP8 is turned on and MN8 is turned off, and the signal sl_a is pulled up to a high level, thereby completing data updating; when the signal ml_b is at a low level, MP2 and MN10 are turned on and MN9 is turned off, and as MN11 is turned on, the signal sl_bx is pulled up to a high level, and the signal sl_a is pulled down to a low level, so that data updating is completed; i.e., when the clock signal CK is high, the data update is completed from the flip-flop circuit.