CN100437227C - Display panel, bonding pad and manufacturing method thereof, and bonding pad array - Google Patents

Abstract

The invention relates to a display panel, a bonding pad, a manufacturing method thereof and a bonding pad array. The bonding pad is suitable for a display (such as a liquid crystal panel), a printed circuit board or other carriers which have a plurality of pins and need higher circuit bonding precision. The bonding pad is mainly composed of a plurality of leads and one or more dielectric layers. The dielectric layer is configured among the pins to divide the pin area into a plurality of layers, and the tail ends of the pins are not covered by the dielectric layer. The invention also arranges the bonding pads on a carrier to form a bonding pad array. In addition, the invention also applies the bonding pad and the bonding pad array on the display panel.

Description

Display panel, bonding pad and manufacturing method thereof, and bonding pad array

technical field

The present invention relates to a lead pad, and in particular to a lead pad array composed of the above-mentioned lead pad.

Background technique

The rapid progress of the multimedia society is mostly due to the rapid progress of semiconductor components or man-machine display devices. As far as the display is concerned, the cathode ray tube (Cathode Ray Tube, CRT) has been monopolizing the display market in recent years because of its excellent display quality and economy. However, for the environment where individuals operate most terminals/display devices on the table, or from the perspective of environmental protection, the trend of saving energy is predicted. Cathode ray tubes still have many problems in terms of space utilization and energy consumption, and There is no effective solution to the demands of lightness, thinness, shortness, smallness and low power consumption. Therefore, thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT LCD) with superior characteristics such as high image quality, space utilization efficiency, low power consumption and no radiation has gradually become the mainstream of the market.

At present, liquid crystal display panels have been widely used in various portable products, such as display screens of mobile phones, personal digital assistants (Personal Digital Assistant, PDA) and other products. With the increasing requirements of users for the resolution of display panels, many high-resolution panels have come out one after another. In addition to the concerns of aperture ratio, high-resolution LCD panels are directly affected by the size of the panel in terms of circuit layout. However, this phenomenon is most serious in small-sized panels. Therefore, how to break through the bottleneck of circuit layout density has gradually become one of the topics discussed by display panel manufacturers.

FIG. 1 is a schematic structural diagram of a known bonding pad, FIG. 2A is a schematic structural diagram of a conventional bonding pad array, and FIG. 2B is a structural schematic diagram of another conventional bonding pad array. . First, please refer to FIG. 1 and FIG. 2A at the same time. The conventional bonding pad 100 is configured on the carrier 200. Taking the liquid crystal display panel as an example, the bonding pad 100 is usually located on the non-display area of the display panel to communicate with the carrier 200. The I/O terminal on the driver chip is electrically connected, or through an anisotropic conductive film (An-isotropic Conductive Film, ACF) and a flexible printed circuit (Flexible Printed Circuit, FPC) sexual connection. It can be seen from FIG. 2A that the bonding pads 100 in the bonding pad array 202 are arranged in a row with a certain distance P between each other, and the distance from the first bonding pad to the last bonding pad, that is, the distribution range D of the bonding pad array 202, is directly It is limited by the pitch P between the bond pads 100 and the number of bond pads 100 .

When the distribution range D of the bonding pad array 202 is longer, the bonding accuracy between these bonding pads and the chip or the flexible printed circuit will be affected by the cumulative tolerance of the pitch P. In addition, as the resolution of the size panel is continuously improved, the distribution range D of the bonding pad array 202 will gradually approach the side length of the panel, so that the resolution of the size panel cannot be further improved. However, in order to take into account the bonding reliability between the bonding pads 100 and the driver chip or the flexible printed circuit, the pitch P between the bonding pads 100 must be maintained above a predetermined value, so the distribution range D of the bonding pad array 202 cannot be significantly reduced.

Please refer to FIG. 2B . In order to reduce the distribution range of the bonding pad array 202, another prior art is to stagger the bonding pads 100 with each other (staggered arrangement) to form a multi-row bonding pad array 202. Compared with FIG. 2A Therefore, the distance D' from the first bonding pad to the last bonding pad can be greatly reduced.

From the above, it can be known that the bonding pad array 202 in FIG. 2A and FIG. 2B is laid out on a single level on the carrier 200 , no matter what kind of wiring design, it will face the dilemma of poor layout flexibility or impossible layout.

It can be seen that the above-mentioned existing display panels, bonding pads, manufacturing methods thereof, and bonding pad arrays still have many defects, and further improvements are urgently needed. In order to solve the defects of the existing display panels, bonding pads and their manufacturing methods, and bonding pad arrays, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time. This is obviously the relevant industry. urgent problem to be solved.

In view of the defects of the above-mentioned existing display panels, bonding pads and their manufacturing methods, and bonding pad arrays, the inventors actively researched and innovated based on years of rich practical experience and professional knowledge engaged in the design and manufacture of such products, in order to create a The new display panel, the bonding pad and its manufacturing method, and the bonding pad array can improve the existing display panel, the bonding pad, its manufacturing method, and the bonding pad array, making it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.

Contents of the invention

The object of the present invention is to overcome the defects of the existing bonding pads and bonding pad arrays, and provide a new bonding pad and bonding pad array. The technical problem to be solved is to greatly improve the layout of the bonding pads. ) density, so as to effectively shorten the distance from the first bonding pad to the last bonding pad, and still have good accuracy when the number of bonding pads is large, so that it is more suitable for practical use.

Another object of the present invention is to overcome the defects of the existing display panels and provide a display panel with the above-mentioned bonding pads and bonding pad arrays, so that the layout density of the bonding pads can be greatly increased to effectively shorten the first The distance from the bonding pad to the last bonding pad still has good accuracy when the number of bonding pads is large, so it is more suitable for practical use.

Another object of the present invention is to overcome the defects of the existing bonding pad manufacturing method, and provide a bonding pad manufacturing method, which can greatly increase the layout density of bonding pads, so as to effectively shorten the first bonding pad The distance to the last bonding pad, and when the number of bonding pads is large, still has good accuracy, so it is more suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A bonding pad according to the present invention is suitable for being disposed on a substrate, and the bonding pad includes: a first lead layer; and a dielectric layer disposed on the first lead layer; and a The second lead layer is arranged on the dielectric layer and correspondingly located above the first lead layer, and the second lead layer and the first lead layer are electrically insulated from each other.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned bonding pad, the ends of the first and second lead layers are separated from each other by a distance.

The aforementioned bonding pad, wherein the dielectric layer is disposed on the first pin layer and exposes the end of the first pin.

The purpose of the present invention and the solution to its technical problems are also achieved by the following technical solutions. A bonding pad array according to the present invention is a bonding pad array composed of a plurality of bonding pads according to claim 1 .

In the aforementioned array of bonding pads, the bonding pads are arranged alternately in plural rows.

The aforementioned bonding pad array, wherein the pin layers include: a first pin layer, wherein the dielectric layer is configured on the first pin layer and exposes the first pin the end of the layer; and a second pin layer configured on the dielectric layer, and the second pin layer is electrically insulated from the first pin layer.

In the aforementioned bonding pad array, the dielectric layer further covers the substrate.

The purpose of the present invention and the solution to its technical problems are also achieved by the following technical solutions. A display panel according to the present invention comprises the bonding pad as claimed in claim 1 .

The purpose of the present invention and the solution to its technical problems are also achieved by the following technical solutions. A method for manufacturing a bonding pad according to the present invention includes the following steps: providing a base material; forming a first lead layer on the base material; forming a dielectric layer on the first lead layer layer; and forming a second lead layer on the dielectric layer, the second lead layer is correspondingly located above the first lead layer, and the second lead layer and the first lead layer are electrically insulated from each other .

In the above-mentioned manufacturing method of the bonding pad, there is a distance between the lead end of the first lead layer and the lead end of the second lead layer.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from the above technical solutions, in order to achieve the aforementioned object of the invention, the main technical contents of the present invention are as follows:

The present invention provides a bonding pad (lead pad), which is suitable for disposing on a base material (such as a liquid crystal panel, a printed circuit board or other carrier), and the bonding pad is mainly composed of a plurality of pin layers and a layer or It is composed of multiple dielectric layers. Wherein, the dielectric layer is arranged between each pin. In addition, the ends of the above-mentioned lead layers are not covered by the dielectric layer, and the ends of the lead layers are, for example, separated from each other by a distance.

To achieve the above object, the present invention further provides a lead pad array, which is composed of a plurality of the above-mentioned lead pads. Wherein, the bonding pads are, for example, arranged in a row or in a staggered arrangement to form multiple rows.

In the present invention, the lead layer is, for example, divided into two layers, that is, these lead layers are composed of a first lead layer and a second lead layer. When the pin layer is divided into two layers, only one dielectric layer needs to be disposed between the first pin layer and the second pin layer. Wherein, the dielectric layer is arranged on the first lead layer, and for example exposes the end of the first lead layer, while the second lead layer is arranged on the dielectric layer, and the second lead layer is connected with the first lead layer A pin layer is electrically insulated. Likewise, the end of the first lead layer is, for example, at a distance from the end of the second lead layer.

In the present invention, the dielectric layer can be distributed only above the first lead layer, or distributed above the part of the substrate outside the first lead layer and cover the first lead layer, and only expose the first lead layer. end of pin layer.

To achieve the above object, the present invention further provides a method for manufacturing a bonding pad, which includes the following steps: (a) providing a base material; and (b) alternately forming at least two lead layers and at least one pin layer on the base material dielectric layer to form multi-level bond pads.

From the above, it can be known that the present invention provides a bonding pad, which is suitable for displays (such as liquid crystal panels), printed circuit boards, or other carriers that have a large number of pins and require higher circuit bonding accuracy. The bonding pad is mainly composed of a plurality of pins and one or more dielectric layers. Wherein, the dielectric layer is arranged between each pin to separate the pin area into multiple levels, and the end of the pin is not covered by the dielectric layer. In the present invention, the above-mentioned bonding pads are arranged on a carrier to form a bonding pad array. In addition, the present invention also applies the above-mentioned bonding pads and bonding pad arrays to the display panel.

By virtue of the above technical solutions, the present invention has at least the following advantages:

The bonding pad and the bonding pad array of the present invention can greatly increase the layout density of the bonding pads, can effectively shorten the distance from the first bonding pad to the last bonding pad, and still have good performance when the number of bonding pads is large. Accuracy.

The display panel with the above-mentioned bonding pads and the bonding pad array of the present invention can greatly increase the layout density of the bonding pads, can effectively shorten the distance from the first bonding pad to the last bonding pad, and still has the advantages of a large number of bonding pads. good precision.

The bonding pad manufacturing method of the present invention can greatly increase the layout density of the bonding pads, effectively shorten the distance from the first bonding pad to the last bonding pad, and still have good precision when the number of bonding pads is large.

To sum up, since the bonding pin structure of the present invention divides the pin layer into multiple layers to greatly increase the layout density of the bonding pads, it can also effectively shorten the distribution range of the bonding pad array. Therefore, the present invention can further improve the accuracy of bonding. The present invention has above-mentioned many advantages and practical value, and there is no similar structural design and method published or used in similar products and methods, and it is indeed an innovation, no matter in product structure, method or function. The improvement has made great progress in technology, and has produced easy-to-use and practical effects, and has a number of enhanced functions compared with the existing technology, so it is more suitable for practical use, and has a wide range of industrial application value. Sincerely A novel, progressive and practical new design.

The above description is only an overview of the technical solutions of the present invention. In order to understand the technical means of the present invention more clearly and implement them according to the contents of the description, the preferred embodiments of the present invention and accompanying drawings are described in detail below.

Description of drawings

FIG. 1 is a schematic structural diagram of a conventional bonding pad.

FIG. 2A is a schematic structural diagram of a conventional bonding pad array.

FIG. 2B is a schematic structural diagram of another conventional bonding pad array.

3 and 4 are schematic structural diagrams of bonding pads according to the first embodiment of the present invention.

FIG. 5A and FIG. 5B are schematic diagrams of a bonding pad array formed by using the bonding pads of FIG. 3 or FIG. 4 .

6 and 7 are structural schematic diagrams of bonding pads according to a second embodiment of the present invention.

100: Splice Pad 200: Carrier

202: Bonding pad array (array) 300: Bonding pads

302: first pin layer 302a, 306a, 310a: end

304, 305, 308, 311, 312: dielectric layer 306: second pin layer

310: The third pin layer 500: Carrier

502: bonding pad array (array) P: Pitch

D, D’: the distribution range of the bonding pad array D”: the distribution range of the bonding pad array

D"': Range of bond pad array distribution

Detailed ways

The specific structures, manufacturing methods, steps, features and functions of the display panel, bonding pads, manufacturing method thereof, and bonding pad array according to the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

first embodiment

3 and 4 are schematic structural diagrams of bonding pads according to the first embodiment of the present invention. Please firstly refer to FIG. 3 , the bonding pad 300 of this embodiment is mainly composed of a first pin layer 302 , a dielectric layer 304 and a second pin layer 306 . Wherein, the dielectric layer 304 is configured on the first pin layer 302, and exposes the end 302a of the first pin layer 302, and the second pin layer 306 is configured on the dielectric layer 304, and the second The second pin layer 306 is electrically insulated from the first pin layer 302 . In addition, the end 302a of the first lead layer 302 is, for example, at a distance from the end 306a of the second lead layer 306 .

Please refer to FIG. 3 and FIG. 4 at the same time. When the pin layer is divided into two layers (the first pin layer 302 and the second pin layer 306), only a single layer of dielectric layer 304 needs to be configured on the first pin layer. Between the lead layer 302 and the second lead layer 306 . As can be seen from FIG. 3 , the dielectric layer 304 may only be distributed above the first lead layer 302 and expose the end 302 a of the first lead layer 302 . In addition, as can be seen from FIG. 4 , the dielectric layer 305 is distributed over a portion of the substrate other than the first lead layer 302 and covers the first lead layer 302 , only exposing the end 302 a of the first lead layer 302 .

5A and FIG. 5B are schematic diagrams of a bonding pad array formed by using the bonding pads shown in FIG. 3 or FIG. 4 . Please first refer to FIG. 5A. In this embodiment, the bonding pads 300 are disposed on the carrier 500. Taking the liquid crystal display panel as an example, the bonding pads 300 are usually located on the non-display area of the display panel to communicate with the driver chip. The input/output contacts on the circuit board are electrically connected, or are electrically connected to the flexible printed circuit (FPC) through the anisotropic conductive film (ACF). It can be seen from FIG. 5A that the bonding pads 300 in the bonding pad array 502 are arranged in a row with a certain distance P between each other, and the bonding pads 300 are formed by the first lead layer 302, the dielectric layer 304 and the second lead layer 306. double layer structure.

Since the bonding pad 300 of this embodiment adopts a double-level design, it can accommodate double the number of contacts in the same layout area (distance), and therefore, the distribution range of the bonding pad array 502 (the first bonding Pad to the last bonding pad distance) D" will be greatly reduced.

Next, please refer to FIG. 5B . In order to further reduce the distribution range of the bonding pad array 502 and improve bonding accuracy, the present embodiment arranges the double-level bonding pads 300 in multiple columns in a staggered manner. In this embodiment, the distribution range of the bonding pad array 502 (the distance from the first bonding pad to the last bonding pad) D"' can be further reduced.

Based on the above, the bonding pad array 502 in this embodiment can be applied to displays that have a large number of pins and require higher circuit bonding accuracy, such as amorphous silicon thin film transistor liquid crystal displays (a-SiTFT LCD) or Low temperature polysilicon thin film transistor liquid crystal display (LTPS-TFT LCD). Since the thin film transistor array is manufactured through multiple photomasks, the bonding pad array 502 of this embodiment only needs to make minor modifications to the photomask, and its manufacturing method and structure can be integrated into the thin film transistor array (TFT array) manufacturing process. In the process, there is no need to increase the number of masks and the cost of the process.

second embodiment

Please refer to FIG. 6 and FIG. 7 at the same time, which are schematic structural diagrams of bonding pads according to a second embodiment of the present invention. This embodiment is similar to the first embodiment (shown in FIG. 3 and FIG. 4 ), but the difference lies in the number of layers of the pin area. The bonding pad 300 of this embodiment is mainly composed of a first lead layer 302 , a dielectric layer 304 , a second lead layer 306 , a dielectric layer 308 and a third lead layer 310 . Wherein, the dielectric layer 304 and the dielectric layer 308 are configured between the first pin layer 302, the second pin layer 306 and the third pin layer 310, so as to separate the pin area into three levels, and the first The ends 302 a , 306 a , 310 a of the pin layer 302 , the second pin layer 306 and the third pin layer 310 are not covered by the dielectric layer 304 , 308 . In addition, the ends 302 a , 306 a , 310 a of the first pin layer 302 , the second pin layer 306 and the third pin layer 310 are, for example, at a distance from each other.

As can be seen from FIG. 6, the dielectric layer 304 can only be distributed on the first pin layer 302, and expose the end 302a of the first pin layer 302; the dielectric layer 308 can only be distributed on the second pin layer 306 above, and expose the end 306a of the second lead layer 306; and the third lead layer 310 is located above the dielectric layer 308.

In addition, as can be seen from FIG. 7 , the dielectric layer 311 is distributed above part of the base material other than the first pin layer 302 and covers the first pin layer 302, only exposing the first pin layer 302. end 302a; the dielectric layer 312 is distributed over part of the dielectric layer 311 and covers the second pin layer 306, only exposing the end 306a of the second pin layer 306; and the third pin layer 310 is located in the dielectric layer 312 above.

The bonding pad (array) structures disclosed in the above-mentioned first embodiment and the second embodiment are, for example, alternately forming at least two pin layers and at least one dielectric layer on the substrate to form a multi-level bonding pad (array) structure .

Although the first embodiment and the second embodiment described above are described with the bonding pads composed of double-layer pins and three-layer pins, they do not limit the number of layers of the bonding pads of the present invention. It can be deduced from the above that the bonding pad of the present invention can be composed of N pins and (N−1) dielectric layers, and N is greater than or equal to 2.

To sum up, the bonding pads of the present invention divide the pins into multiple layers to greatly increase the layout density of the bonding pads, thereby effectively shortening the distance from the first bonding pad to the last bonding pad. In addition, while greatly shortening the distance from the first bonding pad to the last bonding pad, the cumulative tolerance sum of all bonding pads on the pitch can also be effectively reduced, and this design can further improve the accuracy of bonding.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the method and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims (10)

1. A bonding pad suitable for disposing on a substrate, characterized in that the bonding pad comprises: a first pin layer; a dielectric layer disposed on the first pin layer; and A second pin layer is arranged on the dielectric layer and correspondingly located above the first pin layer, and the second pin layer is electrically insulated from the first pin layer. 2. The bonding pad according to claim 1, wherein the ends of the first and second lead layers are spaced apart from each other by a distance. 3. The bonding pad as claimed in claim 1, wherein the dielectric layer is disposed on the first pin layer and exposes the end of the first pin. 4. A bonding pad array, characterized in that it is composed of a plurality of bonding pads according to claim 1. 5. The bonding pad array according to claim 4, wherein the bonding pads are arranged in plural rows in a staggered manner. 6. The bonding pad array according to claim 4, wherein said lead layer comprises a dielectric layer, a first lead layer and a second lead layer, wherein said dielectric layer is configured on the first lead layer and exposes the end of the first lead layer. 7. The bonding pad array of claim 6, wherein the dielectric layer further covers the substrate. 8. A display panel comprising the bonding pad as claimed in claim 1. 9. A method of making a joint pad, characterized in that it comprises the following steps: providing a substrate; forming a first pin layer on the substrate; forming a dielectric layer over the first pin layer; and A second pin layer is formed on the dielectric layer, the second pin layer is correspondingly located above the first pin layer, and the second pin layer is electrically insulated from the first pin layer. 10. The method for fabricating bonding pads as claimed in claim 9, wherein the lead ends of the first lead layer are separated from the lead ends of the second lead layer by a distance.

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