JPH10256469A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To pack a plurality of semiconductor chips in one package at a high stack mounting density without increasing the thickness of the package by suppressing the looping heights of wires. SOLUTION: A semiconductor device is constituted by fixing a first semiconductor chip 10 on an island 13 and a second semiconductor chip on the first chip 10. Then the first bonding pad 12a of the first chip 10 is wire-bonded 'upward' to a lead terminal 17 and the second bonding pad 12b of the second chip 11 is wire-bonded 'downward' to the lead terminal 17. The main part of a semiconductor device thus constituted is molded with a resin 18 including the semiconductor chips 10 and 11. The position of the island 13 is lowered so that the rear surface of the island 13 may be exposed on the surface of the resin 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of crossing bonding wires and reducing the thickness of a package while superposing and molding a plurality of semiconductor chips.

[0002]

2. Description of the Related Art A transfer molding method for sealing a semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. Technology. A lead frame is used as a support material for the semiconductor chip 1. The semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pads of the semiconductor chip 1 and the leads 4 are connected to the wires 5.
It is manufactured by setting a lead frame in a mold having a desired outer shape, injecting an epoxy resin into the mold, and curing the lead frame.

On the other hand, the wave of miniaturization and weight reduction of various electronic devices is unavoidable, and semiconductor devices incorporated therein are required to have higher capacity, higher function, and higher integration. Therefore, it has existed as an idea before (for example, Japanese Patent Application Laid-Open No. 55-1111517).
Attention has been paid to a technique for sealing a plurality of semiconductor chips in one package, and there has been a movement to realize it. That is, FIG.
As shown in (B), a first semiconductor chip 1a is fixed on the island 3 and a second semiconductor chip 1a is fixed on the first semiconductor chip 1a.
The semiconductor chip 1b is fixed, the corresponding bonding pad and the lead 4 are connected by bonding wires 5a and 5b, and sealed with the resin 2.

[0004]

[0007] Despite the increase in cost, there is no other choice but to integrate a plurality of chips, that is, there is an extremely strong demand for reduction in size and size. Therefore, there is a strong desire to store the package in a surface-mounted and thin package rather than a DIP-type package having a sufficient external dimension, and this has a greater merit as a whole.

However, the semiconductor chip 1 and the island 3 cannot be made thinner than a certain thickness due to the need to have mechanical strength. There is. FIG. 6 shows the bonding wires 5a and 5b.
As shown in FIG. 6 (A), it is necessary to rise vertically by a certain amount or more, so that the distance between the first wire 5a and the second wire 5b (shown in FIG. 6 (A) 7) becomes narrow. However, in order to prevent contact accidents between them, there is a restriction that they are arranged in parallel with each other. As a result, the first wire 5a and the second wire 5b cannot be arranged to cross each other as shown by reference numeral 8 in FIG.
However, there is a disadvantage in that the positional relationship between them is restricted and the degree of freedom of design is lost.

If crossing is to be performed, the height of the second wire 5b (reference numeral 9 in FIG. 6A) is made unnecessarily high in order to secure the interval 7, and eventually the outer shape of the package is obtained. Increases the dimensions. Further, pushing up the external dimensions of the package by stacking the chips does not fit into the external dimensions of the conventionally prepared package, so most of the manufacturing equipment used in the post-process such as a mold and a test and measurement apparatus is used. There is a disadvantage that the cost must be significantly increased due to capital investment because the design must be different.

Specifically, the present inventor has stated that
The thickness t of the surface mount type called TSOP type is about 1.0
The goal was to stack and house two chips in a package that was only mm. Other than the lead frame method, a bare chip method, whose external dimensions are almost the same as the semiconductor chip, and a film carrier method using a film and copper foil instead of a metal plate can be considered as further miniaturization methods, but the cost is too high Moreover, it becomes difficult to secure reliability. Therefore, there is a strong demand to be realized by the lead frame and transfer molding technology, which is an extension of the conventional technology.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems. The first semiconductor chip is disposed below the height of the lead and the second semiconductor chip is disposed above the lead. , And the first wire from the first semiconductor chip is wire-bonded by a launching method, and the second wire from the second semiconductor chip is wire-bonded by a down-loading method. A possible semiconductor device is provided.

Further, the leads and the islands are stepped so that the back surface of the island on which the semiconductor chip is mounted is exposed on the surface of the resin, and a plurality of semiconductor chips are stacked on the island to increase the height of the resin. It is intended to provide a semiconductor device in which is reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. First, FIG.
FIG. 3B is a sectional view showing the semiconductor device of the present invention, FIG. 3 is a top view showing the semiconductor device of the present invention, and FIG. 4 is a rear view showing the semiconductor device of the present invention. 2A is a sectional view taken along the line AA in FIG. 3, and FIG. 2B is a sectional view taken along the line BB in FIG.

In the figure, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. First and second semiconductor chips 1
Various active and passive circuit elements are formed on the silicon surfaces 0 and 11 in the previous process. A first bonding pad 12a for external connection is formed in a peripheral portion of the chip of the first semiconductor chip 10. Similarly, a second bonding pad 12b is formed on the surface of the second semiconductor chip 11. Each bonding pad 12
A passivation film such as a silicon nitride film, a silicon oxide film, and a polyimide-based insulating film is formed so as to cover a and 12b, and the upper portions of the bonding pads 12a and 12b are opened for electrical connection.

The first semiconductor chip 10 is die-bonded on the lead frame island 13 with an epoxy-based conductive adhesive 14 such as Ag paste, and the second semiconductor chip 11 is formed on the passivation film of the first semiconductor chip 10. Is fixed with an insulating epoxy adhesive 15. One end of a first bonding wire 16a such as a gold wire is wire-bonded to the surface of the first bonding pad 12a on the surface of the first semiconductor chip 10, and the other end of the first bonding wire 16a is led out. Is wire-bonded to the tip 17a of the lead terminal 17 for use. Similarly, one end of a second bonding wire 16 b is wire-bonded to the surface of the second bonding pad 12 b of the second semiconductor chip 11, and the other end is wire-bonded to the tip 17 a of the lead terminal 17.
Thus, each of the bonding pads 12a and 12b and each of the leads 17 are electrically connected.

A main part including the first and second semiconductor chips 10 and 11, the tip 17 a of the lead terminal, and the first and second bonding wires 16 a and 16 b is surrounded by an epoxy-based thermosetting resin 18. Molded and packaged. The lead terminal 17 is formed of a resin 18 on the side wall of the package.
From the position of about half of the thickness. That is, referring to FIG.
1 and the lower resin thickness t 2 are almost the same thickness. The lead terminal 17 led out of the resin 18 is bent downward at one end, bent again, and formed into a Z-shape. This forming shape corresponds to the lead terminal 1
7 is a shape for surface mounting use, in which the backside fixing portion 17b of 7 is adhered to a conductive pattern formed on a printed circuit board.

In this semiconductor device, first, holding tie bars 1 provided at four corners of island 13 in a state of a lead frame are provided.
9, the height of the island 13 and the height of the lead terminal tip 17a are made different, and the first and second semiconductor chips 10 and
11 by die bonding and bonding pads 12a, 12
b and the tip 17a of the lead terminal are wire-bonded, and then the lead frame 17 and the lead terminal 17 are sandwiched and fixed between the upper and lower dies so that the island 13 is located in the cavity provided in the upper and lower dies. The resin can be obtained by injecting and curing the resin in such a state.

The lead frame has a thickness of 150-2.
Each part such as the island 13 and the lead terminal 17 is formed by etching or punching a 00 μm copper- or iron-based plate-like material, and each part is a lead frame until cut off after the molding process. It is held in the body. In the held state, the height of the leading end portion 17a of the lead terminal and the height of the frame coincide with each other, and only the island 13 is stepped to have a different height. Therefore, in the completed device, the tie bar 19 holding the island 13 is bent upward inside the resin 18, extends substantially horizontally again at a position corresponding to the height of the lead 14, and
8 The cut surface is exposed on the surface and terminated.

Each of the semiconductor chips 10 and 11 is polished on the back surface by a back grinding process immediately before the assembling process to obtain a 250
The thickness is about 300 μm. The thickness of the lead terminal 17 (t3 in FIG. 2A) is about 130 μm. Since the island 13 is formed at the same time from the plate-like material, the plate thickness of the island 13 is also the same value, which is almost the limit value for maintaining the mechanical strength of each part.

FIG. 1 shows bonding wires 16a and 16b.
It is an expanded sectional view which shows a part. While the tip 17a of the lead terminal 17 is located at about half the height of the package thickness, the surface of the first bonding pad 12a is located below the bonding area 20 of the lead terminal tip 17a.
The surface of the second bonding pad 12b is located above the bonding area 20.

The first bonding wire 16a is connected to the first bonding wire 16a.
1st bond is made on the surface of the bonding pad 12a, and after rising vertically, it is bent at the same or slightly higher position as the bonding area 20 and extends in the horizontal direction to make a 2nd bond on the surface of the bonding area 20. . Since the “launch” is higher at the second bond position than at the first bond position, the first bonding wire 1
The length of the wire can be shortened without dripping 6a downward. Therefore, the loop height of the wire can be minimized.

The second bonding wire 16b is connected to the second bonding wire 16b.
1st bond is hit on the bonding pad 12b of
After being raised vertically to a certain height (illustrated by t4), it is bent, extends downward, and a second bond is hit farther than the first bonding wire 16a on the surface of the bonding area 20. Since “down” is lower at the second bond position than at the first bond position, a “certain height t4” is provided so that the second bonding wire 16b does not contact the corner of the second semiconductor chip 11. I have. still,
In the ball bonding method, a gold ball 21 is formed by melting the tip portion of a gold wire and using its surface tension.
Is pressed to form the first bond, but the heating at the time of forming the gold ball causes 15
A recrystallized portion is generated over a length of 0 to 200 μ, and a portion that is easily bent is formed in this portion. Therefore, the above “certain height t4” is within the length of the recrystallized portion.

As described above, the first bonding wire 16
By setting “a” to “launch”, the loop height of the first bonding wire 16b can be reduced, so that it is easy to provide an interval (t5 in the drawing) with the second bonding wire. Accordingly, reference numeral 8 in FIG.
The first and second bonding wires 16 as shown in FIG.
a and 16b can be arranged so as to intersect, and the restriction on the positional relationship between the lead and the pad can be relaxed. Moreover, the height t4 of the second bonding wire 16b does not need to be excessively increased, so that the package outer shape is not unnecessarily pushed up.

In the case of a 1 mm-thick package targeted by the present inventors, the height of the island 13 is
In the conventional design in which the height t of the lead terminal 17 is subtracted, the thickness t2 of the upper resin 18 is only about 430 μm, and the first and second semiconductor chips are reduced to 430 μm. Naturally, it is impossible to stack and store 10 and 11.

Therefore, in the present invention, the height of the island 13 is reduced to the limit, and the back surface 13a of the island 13 is
By molding so as to be exposed on the surface of No. 8, a margin was given to the thickness of the resin. The back surface 13a of the island is resin 1
8 and a flat surface, which are used when the lead frame is set in the cavity.
Can be obtained by setting the contact with the cavity surface of the lower mold and sealing the resin. Since the position of the island 13 has been lowered, the thickness of the island 13 and the first and second
Thickness of the semiconductor chips 10 and 11, and the adhesive 14,
Even if the thickness of 15 (each 30 to 40 μ is required) is subtracted, 240 to 30
It has become possible to leave the thickness of the resin 18 of 0 μm.

By setting the first bonding wire 16a to "launch", the loop height can be suppressed, and the second bonding wire 16b can be maintained while maintaining the interval t5 with the second bonding wire 16b.
Can be reduced in the loop height t4. Therefore, it is possible to sufficiently store the resin in the above-mentioned resin thickness. As described above, according to the present invention, by arranging the position so that the back surface 13 a of the island 13 is exposed on the lower surface of the resin 18, the thickness of the resin 18 can have a margin, and the outer shape of the resin 18 can be increased. The dimensions can be reduced. Thereby, the first and second semiconductor chips 1 are packaged in one package.
It is possible to provide a semiconductor device that does not increase the thickness of the external dimensions even when 0 and 11 are stacked.

Therefore, conventional equipment such as a mold and a test and measurement device can be used as it is simply by changing the lead frame, and new equipment investment is not required, so that the cost of the product can be reduced. Moreover, the first and second semiconductor chips 1
Since the thicknesses of 0 and 11 do not need to be made thinner than necessary and the mechanical strength of the silicon wafer can be maintained, the handleability of the wafer after the back grinding step is excellent.

Since the semiconductor chips 10 and 11 are stacked and the wires 16 are struck from the same side, the second semiconductor chip 10 is formed on the first semiconductor chip 10 so that the bonding pads 12 formed on the surface thereof are exposed. The restriction that the size must be larger than the chip 11 is added.
Therefore, when the island 13 is designed to be larger than the first semiconductor chip 10, the back surface of the island 13 is exposed on most of the lower surface of the resin 18, and the thermal expansion of the island 13 and the resin 18 is increased. There is a concern that package warpage may occur due to the difference from the coefficient.

Therefore, the size of the island 13 is made smaller than that of the first semiconductor chip 10 so that the island 13 made of a material having a thermal expansion coefficient smaller than that of the resin 18 is formed.
The area of the package can be reduced, and the difference in shrinkage ratio can be reduced to prevent the package from warping. At this time, the tie bar 19 for holding the island bypasses the first semiconductor chip 10 and extends to some extent horizontally with the island 13 and then bends upward in order to correspond to a plurality of chip sizes. As a result, as shown in FIG. 3, the tie bar 19 is molded in such a shape that the back surface of the horizontally extending portion 19a is exposed to the surface of the resin. The horizontally extending portion 19a also has the effect of increasing the adhesion to the resin 18.

[0027]

As described above, according to the present invention,
By stacking a plurality of semiconductor chips 10 and 11 in one package, there is an advantage that a product of high-density mounting can be provided according to a demand for reduction in size and size of electronic equipment. Also,
By setting the first bonding wire 16a to “launch”, the first and second bonding wires 16a, 1a
Since the loop height t4 can be kept low while maintaining the interval t5 of 6b, there is an advantage that the external dimensions can be reduced.

Further, the first and second bonding wires 1
Since a sufficient interval t5 can be provided between 6a and 16b, an intersecting wiring in which both are crossed and wire-bonded to different lead terminals 17 can be realized. Therefore,
Each bonding pad 12a, 12b and lead terminal 17
Can be relaxed, and the degree of freedom in design can be increased.

Further, by arranging the island 13 so as to be exposed on the lower surface of the resin 18, there is an advantage that the thickness of the resin 18 can be reduced. Therefore, without increasing the thickness of the resin 18, the plurality of semiconductor chips 10, 1
1 has the advantage that it can be stacked and stored. The stacking and storage can double the mounting efficiency, for example, as compared to the case where chips are stored side by side.

Further, since the thickness of the resin 18 is not increased, the outer dimensions of the resin 18 can be made the same as those of the conventional product. As a result, a manufacturing apparatus such as a mold and a test and measurement apparatus can be shared, and there is an advantage that the cost of a product can be reduced. That is, in the present invention, all other manufacturing lines can be shared only by changing the design of the lead frame.

Further, since the thickness of the semiconductor chips 10 and 11 does not need to be made thinner than necessary, the mechanical strength of the silicon wafer can be maintained, and there is an advantage that the wafer can be easily handled.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a plan view for explaining the present invention.

FIG. 4 is a rear view for explaining the present invention.

FIG. 5 is a sectional view for explaining a conventional example.

6A is a sectional view for explaining a conventional example, and FIG.
It is a top view.

Claims (8)

[Claims] 1. A first semiconductor chip fixed on an island, a first bonding pad formed on a surface of the first semiconductor chip, and a second bonding chip fixed on the first semiconductor chip. A second bonding pad formed on the surface of the second semiconductor chip, a resin sealing the periphery of the first and second semiconductor chips, and a first height from a bottom surface of the resin. And a lead terminal extending from the vicinity of the first and second semiconductor chips and extending to the outside from a side surface of the resin; and electrically connecting the first bonding pad and the lead terminal. A first bonding wire to be connected; a second bonding wire to electrically connect the second bonding pad to the lead terminal; and a height of the first bonding pad. Wherein the first lower than the height position, and wherein a height of the second bonding pads are respectively located at a higher position than the first height. 2. The semiconductor device according to claim 1, wherein a resin is sealed so that a back surface of the island is exposed to a back surface of the resin. 3. The semiconductor device according to claim 1, wherein the first height is approximately half the thickness of the entire resin. 4. The method according to claim 1, wherein the first bonding wire extends substantially vertically from the first bonding pad.
2. The semiconductor device according to claim 1, wherein the semiconductor device is bent near the first height, extends in a substantially horizontal direction, and is fixed to a surface of the lead terminal. 5. The semiconductor device according to claim 1, wherein a difference in height from a position of the lead terminal to a surface of the first semiconductor chip is larger than at least a length from a ball to a bent portion of the first wire. The semiconductor device according to claim 1, wherein: 6. The semiconductor device according to claim 1, wherein the second bonding wire draws a locus that always passes through a high position with respect to the loop of the first bonding wire. 7. The semiconductor device according to claim 1, wherein said first bonding wire and said second bonding wire cross each other and are connected to different lead terminals. 8. The semiconductor device according to claim 1, wherein said lead terminals are lead-formed in a Z-shape for surface mounting.