CN101510383A - Flat display panel - Google Patents

Abstract

The invention provides a flat display panel, which comprises a substrate, a driving chip, a plurality of control circuit lines and wirings. The display area and the peripheral circuit area are defined on the substrate, the driving chip is arranged on the peripheral circuit area and comprises a plurality of pins, the space between the adjacent pins is not equal, and the space between the pins at the central part of the driving chip is smaller than the space between the pins at the outer side of the driving chip. The control circuit line is arranged in the display area, and the wiring is arranged in the peripheral circuit area and is electrically connected with the control circuit line and the pins.

Description

flat display panel

technical field

The invention relates to a flat display panel, in particular to a flat display panel with driver chips with unequal pitch pins.

Background technique

Compared with traditional non-flat displays such as cathode ray tube displays, flat-panel displays have the characteristics of light weight and thin thickness, and have gradually become mainstream products in the display market. For example, they are used in home TVs, personal computer monitors, mobile phones, and digital cameras. Portable electronic products such as portable music players. According to different display technologies, types of flat panel displays include plasma displays, liquid crystal displays, and organic light emitting displays. Generally speaking, the above-mentioned types of flat-panel displays are provided with electronic components or light-emitting components on thin substrates. Taking thin-film transistor liquid crystal display as an example, it usually includes two glass substrates, upper and lower, wherein thin-film transistors, scanning lines, signal lines, and pixel electrodes are arranged on the surface of the lower glass substrate, and color filters and black color filters are arranged on the surface of the upper glass substrate. For components such as the matrix layer, the position of the upper and lower glass substrates is fixed by the frame glue, and liquid crystal molecules are filled between the two, which constitutes a thin film transistor liquid crystal display panel. In addition, the thin film transistor liquid crystal display usually further includes a plurality of chips, which are electrically connected to the scanning lines and the signal lines to control the switching of each pixel of the display.

As the development of flat-panel displays tends to high-resolution design, the distribution of scanning lines and signal lines is becoming more and more dense, so the spacing between the pins of the chip is getting smaller and smaller, which in turn produces many problems caused by shrinking the process size. technical problem. For example, if the pitch of the pins of the chip is too small, the bonding process between the chip and the wire may be caused by heat expansion and contraction, etc., causing the conductive material to expand and deviate outwards, resulting in short circuit of the pins. In addition, in order to match the wiring design of signal lines and scanning lines, the wires connected to the chip usually have different lengths, which will cause uneven impedance of each wire, thereby affecting the signal transmission speed and quality of signal lines and scanning lines.

Contents of the invention

One of the objects of the present invention is to provide a flat display panel, which includes at least one driver chip disposed on a substrate, and the pins of the driver chip have different pitches, so as to improve the gap between pins in the prior art. If it is too small, there will be problems such as pin short circuit and uneven wire impedance.

The invention provides a flat display panel, which includes a substrate, at least one driving chip, a plurality of control circuit lines and a plurality of wirings. Wherein, a display area and a peripheral circuit area are defined on the substrate, and are arranged on at least one side of the display area. The driving chip is arranged in the peripheral circuit area, and includes a plurality of pins, and the distances between adjacent pins are not completely equal. In addition, the control circuit lines are arranged in the display area, and the wires are arranged in the peripheral circuit area and electrically connected with the control circuit lines and pins. The plurality of wirings include at least the first wiring and the adjacent second wiring and the third wiring, the pin connected to the first wiring and the pin connected to the second wiring and the third wiring There are first spacing and second spacing between them, wherein the first spacing is greater than the second spacing, the line width of the second wiring is greater than the line width of the first wiring, and the line width of the first wiring is greater than that of the third wiring line width.

According to the claims of the present invention, a flat display panel is further disclosed, which includes a substrate, at least one driving chip, a plurality of control circuit lines and a plurality of wirings. A display area and a peripheral circuit area are defined on the substrate, which are arranged on at least one side of the display area. The driver chip is located in the peripheral circuit area, which includes multiple pins, and the distance between adjacent pins is not completely equal, and the distance between the pins in the central part of the driver chip is smaller than that between the pins on the outer side of the driver chip. spacing. The control circuit line is arranged in the display area, and the wiring is arranged in the peripheral circuit area, and is electrically connected with the control circuit line and the pins, and the wiring has a bending configuration area.

Since the driver chip of the flat display panel of the present invention has pins with unequal pitches, it can effectively avoid the problem of short circuit of the pins caused by too close pitches. At the same time, the outer wiring connected to the pins with larger spacing can have a larger line width, which can greatly reduce the wiring impedance. Therefore, the wiring located in the central part does not need a large number of winding lines or zigzagging lines. The impedance of each wiring can be uniformed, and the material cost and wiring space can be saved.

Description of drawings

FIG. 1 is a schematic top view of a flat display panel of the present invention.

FIG. 2 is a partially enlarged schematic diagram of the driver chip and wiring shown in FIG. 1 .

FIG. 3 is a schematic diagram of a second embodiment of the driver chip and wiring design of the flat display panel of the present invention.

FIG. 4 is a schematic diagram of a third embodiment of the driver chip and wiring design of the flat display panel of the present invention.

FIG. 5 is a partially enlarged schematic view of the wiring 26n shown in FIG. 4 .

FIG. 6 is a schematic diagram of a fourth embodiment of the driver chip and wiring design of the flat display panel of the present invention.

FIG. 7 is a schematic diagram of a fifth embodiment of the driver chip and wiring design of the flat display panel of the present invention.

Reference number

10 Flat Display Panel 12 Substrate

14 Display Area 14a Display Area Boundary

16 Peripheral circuit area 18, 20 Driver chip

22, 24 Control circuit wires 26, 28, 26g～26p wiring

26a The third wiring 26b The first wiring

26c Second Wiring 26d Sixth Wiring

26e 4th wiring 26f 5th wiring

30. 30a～30f Pins 32 Bending configuration area

A1, A2, A3, A4 Amplitude B1, B2 Wiring Angle

C1 Center Line D Wiring Spacing

E1, E2 The crest of the wave-shaped trace

M1, M2 The end of the peak and trough

T1 trough of wavy trace w w line width

P1, P2, P3, P4 pin spacing

Detailed ways

Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are schematic diagrams of a first embodiment of a flat display panel of the present invention, wherein FIG. 1 is a schematic top view of a flat display panel, and FIG. 2 is an enlarged schematic diagram of some components of FIG. 1 . As shown in FIG. 1, the flat display panel 10 of the present invention includes a substrate 12, which defines a display area 14 and a peripheral circuit area 16, wherein the peripheral circuit area 16 is arranged on at least one side of the display area 14. In this embodiment, The peripheral circuit area 16 is disposed on the periphery of the display area 14 . The flat display panel 10 further includes a plurality of driver chips 18, 20 disposed in the peripheral circuit area 16, a plurality of control circuit lines 22, 24 disposed in the display area 14, and a plurality of wires 26, 28 disposed in the peripheral circuit area 16, wherein The wires 26, 28 are electrically connected to at least one control circuit wire 22, 24, respectively. The control circuit lines 22 and the control circuit lines 24 can be signal lines and scan lines respectively, and the driving chip 18 and the driving chip 20 can respectively include a signal line driving circuit and a scanning line driving circuit. In the display area 14, the signal lines and the scan lines are respectively parallel to each other. In addition, the driving chips 18, 20 preferably include chip on film (chip on film, COF) type chips, which are directly attached to the surface of a flexible soft film (not shown), and then pasted with a soft film. Attached to peripheral circuit area 16.

Please refer to FIG. 2 , which is a partially enlarged schematic diagram of the driving chip 18 and the wiring 26 shown in FIG. 1 . The driver chip 18 includes a plurality of pins 30 arranged side by side, and the pitches between adjacent pins 30 are not completely equal. For example, the distance between pin 30a and pin 30b is P1; the distance between pin 30b and pin 30c is P2; the distance between pin 30d and pin 30e is P3; and the distance between pin 30e and pin 30f is P4, and the pitches P1, P2, P3, and P4 are not exactly equal. In this embodiment, the closer to the outside of the driver chip 18 , the larger the distance between the pins 30 is. As shown in FIG. 2 , the driver chip 18 defines a centerline C1, which divides the driver chip 18 into left and right sides, and the pins 30a, 30b, 30c, 30d, 30e, and 30f are all located on the left side of the centerline C1. , and are arranged in sequence from the center line C1 to the outside of the driver chip 18, therefore, the pitch P1 is smaller than the pitch P2, the pitch P2 is smaller than the pitch P3, and the pitch P3 is smaller than the pitch P4 (similarly, it is arranged between the pins 30c, 30d The distance between the pins 30 must be greater than the distance P2 and smaller than the distance P3). In a preferred embodiment, the minimum pitch between adjacent pins 30, such as the pitch P1, is about 20 microns, and the maximum pitch, such as the pitch P4, is about 50 microns. In addition, the pins 30 on both sides of the central line C1 are symmetrically arranged with the central line C1 as the axis of symmetry. Therefore, if the pins 30 on the right side of the central line C1 are located farther away from the central line C1, the distance between them will increase. The distance between is also larger. Furthermore, the number of wires 26 corresponds to the number of pins 30 of the driver chip 18 , and each wire 26 is connected to a pin 30 respectively. For convenience of description, the wires 26 shown in FIG. 2 are identified by numerals 26a to 26f. The third wiring 26a, the first wiring 26b, the second wiring 26c, the sixth wiring 26d, the fourth wiring 26e and the fifth wiring 26f are sequentially arranged on the left side of the central line C1, wherein the third wiring Line 26a and second wiring 26c are adjacent to first wiring 26b, sixth wiring 26d and fifth wiring 26f are adjacent to fourth wiring 26e, second wiring 26c and sixth wiring 26d The wiring 26 between them is omitted and not shown in FIG. 2 . The third wiring 26a, the first wiring 26b, the second wiring 26c, the sixth wiring 26d, the fourth wiring 26e and the fifth wiring 26f are respectively connected to the pins 30a, 30b, 30c, Pin 30d, pin 30e and pin 30f. Therefore, the pitch P1 between the pin 30b connected to the first wiring 26b and the pin 30a connected to the third wiring 26a is smaller than the distance between the pin 30b connected to the first wiring 26b and the second wiring 26c. The pitch P2 between the connected pins 30c. Similarly, the sixth wiring 26d and the fifth wiring 26f are adjacent to the fourth wiring 26e and located on both sides thereof, and the pin 30e connected to the fourth wiring 26e is connected to the pin 30e connected to the sixth wiring 26d. There is a pitch P3 between the pins 30d, and there is a pitch P4 between the pins 30e connected to the fourth wiring 26e and the pins 30f connected to the fifth wiring 26f, and the pitch P4 is greater than the pitch P3.

It should be noted that, since the distances between adjacent pins 30 are not completely equal, the distances between some adjacent pins 30 may also be the same. For example, if the pin pitches P1, P2, P5, P6, P3, and P4 are sequentially included from the left side of the central line C1 to the outside of the driver chip 18 (wherein P5 and P6 are not shown in the figure), the above pins The size relationship between the pitches can be P1<P2<P5=P6<P3<P4.

On the other hand, the wires 26 may not have completely the same line width. In this embodiment, the wires 26 located on both sides of the center line C1 are symmetrically arranged with the center line C1 as the axis of symmetry, and the width of the wires 26 connected to the pins 30 on the outer part of the driver chip 18 is larger than The wiring 26 connected to the pin 30 of the central part of the driving chip 18, and the closer to the outside of the driving chip 18, the larger the line width of the wiring 26, for example, the line width of the fifth wiring 26f is greater than that of the fourth wiring 26e. width, and the line width of the fourth wiring 26e is larger than that of the sixth wiring 26d. Therefore, the line widths of the wirings 26 on either side of the central line C1 are different. In a preferred embodiment, the line width w of each wire 26 is a minimum of about 6 to 8 microns.

Since the wires 26 connected to a single driver chip 18 are arranged in the peripheral circuit area 16 in a fan-out (fan-out) drawing mode, the wires 26 (such as the sixth wire 26d, the fourth wire 26d, etc. The wiring 26e and the fifth wiring 26f) are longer than the wiring 26 near the center of the driver chip 18 (such as the third wiring 26a, the first wiring 26b and the second wiring 26c). In order to avoid higher impedance due to the longer wiring of the outer wiring 26, according to the spirit of the present invention, the outer wiring 26 has a larger line width to make the impedance of all the wiring 26 uniform. In addition, there are different pitches between the pins 30 of the driving chip 18, and the pitches of the outer pins 30 are larger, so there is also a larger distance and space between adjacent wirings 26, which can be increased by increasing The line width can effectively improve the uneven impedance caused by the long cable.

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of a second embodiment of the driver chip and wiring design of the flat display panel of the present invention. For ease of description, the same components as those in the previous embodiment are denoted by the same component symbols, and the wires 26 on the left side of the central line C1 are respectively distinguished by 26g, 26h, 26i, and 26j. In the second embodiment, each wiring 26 has a curved configuration area 32 respectively. In the curved configuration area 32, the wiring 26 has a plurality of zigzag or wave shapes that are repeated continuously, wherein the zigzag pattern is as shown in FIG. 3 . The zigzag or wavy pattern of each wiring 26 has an amplitude respectively. For example, the amplitudes of the wirings 26g, 26h, 26i, and 26j are denoted by A1, A2, A3, and A4 respectively, which represent the width of the zigzag groove of the zigzag pattern. In a preferred embodiment, the amplitude (such as amplitude A4, A3) of the wiring 26 on the outside of the driving chip 18 is greater than the amplitude (such as amplitude A1) of the wiring 26 in the central part of the driving chip 18, or the closer to the outside of the driving chip 18 The amplitude of the wiring 26 is slightly larger than the amplitude of the wiring 26 inside it. Under this design, in the bending arrangement area 32 of each wiring 26, the wiring 26 with a smaller amplitude needs to go around more sawtooth numbers, so its length is longer than that of the wiring 26 with a larger amplitude. the trace length. In addition, similar to FIG. 2, the width of the outer wiring 26 in this embodiment is greater than the width of the wiring 26 close to the central part of the driver chip 18, for example, the width of the wiring 26j is greater than the width of the wiring 26i, and the width of the wiring 26h The width is larger than that of the wiring 26g. It is worth noting that, in order to meet the limitations of current lithography, etching and other process technologies, the minimum distance between adjacent wirings 26 is about 6 to 8 microns, for example, wiring 26j and wiring 26i are in the bending configuration area 32 The minimum spacing dmin between the zigzag patterns is about 6 microns. Furthermore, the pins 30 on the driving chip 18 are symmetrical about the central axis C1 as the axis of symmetry, and the widths and routing patterns of the wires 26 on both sides of the central axis C1 are also symmetrical about the central axis C1. However, in other embodiments, the pins 30 on both sides of the central axis C1 and the wires 26 do not need to be exactly the same or symmetrical to each other.

Please refer to FIG. 4 . FIG. 4 is a schematic diagram of a third embodiment of the driver chip and wiring design of the flat display panel of the present invention. In this embodiment, part of the wires 26 has a curved arrangement area 32 , and is arranged in the peripheral circuit area 16 in a wave-shaped pattern around the meander line. In the curved configuration area 32 , the amplitudes A1 and A2 of the wires 26 represent the length of the wave shape, that is, the distance between the midpoint of an adjacent crest and trough and the midpoint of an adjacent adjacent crest and trough. To clearly illustrate how the amplitudes A1 and A2 are defined, FIG. 5 shows a partially enlarged schematic diagram of the wiring 26n. As shown in Figure 5, there is a midpoint M1 between the adjacent peak E1 and the trough T1, and there is a midpoint M2 between the adjacent peak E2 and the trough T1, and the distance between the two adjacent midpoints M1 and M2 is It is defined as the amplitude A2 of the wiring 26n. Similar to the previous embodiment, the wiring 26 near the central line C1, such as the wiring 26k, 261, 26m, has a smaller amplitude, and the wiring 26 near the outside of the driver chip 18, such as the wiring 26n, 26o, has a smaller amplitude. Larger, so the traces are shorter. In addition, the outermost wire 26p does not have a bending configuration area, but in other embodiments, none of the outer wires 26 (such as wires 26n, 26o, 26p) may have a bending configuration area. Furthermore, as in the previous embodiment, the wiring 26 closer to the outside of the driver chip 18 has a larger line width, for example, the line width of the wiring 26p is greater than that of the wiring 26o, and the line width of the wiring 26m is greater than that of the wiring 26m. The line width of line 261.

Please refer to FIG. 6 . FIG. 6 is a schematic diagram of a fourth embodiment of the driver chip and wiring design of the flat display panel of the present invention. As in the previous embodiment, the spacing between the pins 30 of the driving chip 18 is not exactly the same, for example, the spacing between the pins 30 located on the outside of the driving chip 18 is relatively large, while the spacing between the pins 30 located in the central part of the driving chip 18 The spacing is small. In this embodiment, each wire 26 corresponds to a pin 30 and has the same wire width. In addition, each wiring 26 has a curved configuration area 32 , including a winding wire design in a zigzag pattern. However, the wiring 30 close to the central line C1 has a smaller amplitude (for example, the amplitude A1 ), while the wiring 26 corresponding to the pin 30 outside the driving chip 18 has a larger amplitude.

FIG. 7 is a schematic diagram of a fifth embodiment of the driver chip and wiring design of the flat display panel of the present invention. As shown in the figure, the driver chip 18 includes a plurality of pins 30 , and the spacing between the pins 30 is not exactly the same. It should be noted that the arrangement positions of the pins 30 on the left and right sides of the centerline C1 are not mirror-symmetrical, for example, the distance between the two leftmost pins 30a and 30b of the driver chip 18 is P1, while in The distance between the two rightmost pins 30c and 30d of the driving chip 18 is P2, and the distance P1 is greater than the distance P2. The wires 26 are respectively correspondingly connected to a pin 30, wherein the wire width of the wire 26 close to the central part of the driver chip 18 is smaller than the wire 26 near the outside of the driver chip 18, for example, the wire width of the wire 26a is smaller than that of the wire 26c , the line width of the wiring 26d is larger than that of the wiring 26c, and the line width of the wiring 26f is larger than that of the wiring 26d and the wiring 26e. The wiring 26 on the right side of the central line C1 also has a similar line width variation design. It should be noted that the routing pattern of the wiring 26 on both sides of the central line C1 is not completely symmetrical. For example, the wiring 26i on the right side of the central line C1 has a bending configuration area 32, while the wiring 26k and 26j are There is no bent arrangement area, however, none of the wirings 26 d , 26 e , and 26 f on the left side of the central line C1 has the bent arrangement area 32 . In addition, the angle B1 between the wiring 26k and the boundary 14a of the display area is not equal to the angle B2 between the wiring 26f and the boundary 14a of the display area. In this embodiment, the angle B2 is greater than the angle B1.

The flat display panel of the present invention can be applied to ion display, liquid crystal display and organic light-emitting display or any display panel that requires bonding of chips and wires. In addition, the aforementioned embodiments illustrate the spirit of the present invention by taking the routing design of the signal line and the signal line driver chip as an example. Similar designs can also be applied to the scanning line and the scanning line driver chip or the connection between the scanning line and the chip pins. wire design.

Compared with the prior art, since the pins of the driving chip of the flat display panel of the present invention have unequal pitches, it is possible to avoid the wiring short circuit problem caused by too close pitch of the pins in the known technology. In a preferred embodiment, the distance between the pins near the outside of the driver chip is larger, so the wiring connected to the outer pins has a larger routing space. The present invention also utilizes this characteristic design to make the outer wiring have a larger Large line width to effectively reduce the impedance of the outer wiring, so that the wiring close to the central part of the driver chip does not need to have a very fine winding line or winding line design like the design of the known technology, resulting in a significant increase in its Cable length. In short, the present invention uses the unequal spacing pins on the driver chip and the design of adjusting the width of the wiring, and cooperates with the change of the amplitude of the bending configuration area, which can make the wiring impedance uniform and effectively improve the quality of the wiring process. rate, further improving the display quality of the flat display panel.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (23)

1. a two-d display panel is characterized in that, described panel comprises:

One substrate, definition has a viewing area and a periphery circuit region, is located at least one side of described viewing area;

At least one chip for driving is located at described periphery circuit region, and described chip for driving comprises a plurality of pins, and the spacing between adjacent described these pins is not exclusively equal;

Many control circuit lines are arranged at described viewing area; And

Many distributions, be arranged at described periphery circuit region and be electrically connected with described these control circuit lines and described these pins, described these distributions comprise one first distribution and adjacent one second distribution and one the 3rd distribution at least, have one first spacing and one second spacing respectively between described pin that described first distribution is connected and described second distribution and described these pins that described the 3rd distribution is connected, wherein said first spacing is greater than described second spacing, and the live width of described second distribution is greater than the live width of described first distribution, and the live width of described first distribution is greater than the live width of described the 3rd distribution.

2. two-d display panel as claimed in claim 1 is characterized in that, described these control circuit lines are parallel each other in described viewing area.

3. two-d display panel as claimed in claim 1, it is characterized in that the live width of described these distributions that is connected in described these pins in the described chip for driving outside is greater than the live width of described these distributions of described these pins that are connected in described chip for driving middle body.

4. two-d display panel as claimed in claim 1, it is characterized in that, described chip for driving has a center line, and the spacing between described these pins of approaching more described center line is more little, and big more away from the spacing between described these pins of described center line more.

5. two-d display panel as claimed in claim 4 is characterized in that, described these pins that are positioned at the described center line both sides of described chip for driving are to be that axis of symmetry and left-right symmetric are arranged with described center line.

6. two-d display panel as claimed in claim 5 is characterized in that, described these distributions that are positioned at the described center line both sides of described chip for driving are that axis of symmetry and left-right symmetric are arranged with described center line.

7. two-d display panel as claimed in claim 4 is characterized in that, described these distributions that are positioned at the described center line both sides of described chip for driving are asymmetric setting.

8. two-d display panel as claimed in claim 1 is characterized in that, described these distributions have a curved configuration district.

9. two-d display panel as claimed in claim 8 is characterized in that, described these distributions in the described curved configuration district have a plurality of sawtooth or the wave-like of continuous repetition, and described these sawtooth or the wave-like of each described distribution have an amplitude.

10. two-d display panel as claimed in claim 9 is characterized in that, the amplitude of described these distributions in the described chip for driving outside is the amplitude greater than described these distributions of described chip for driving middle body.

11. two-d display panel as claimed in claim 9 is characterized in that, in described curved configuration district, the minor increment of adjacent described these distributions is about 6 to 8 microns.

12. two-d display panel as claimed in claim 1 is characterized in that, the minimum spacing of adjacent described these pins is about 20 microns, and maximum spacing is about 50 microns.

13. two-d display panel as claimed in claim 1 is characterized in that, described these distributions of the middle body of described chip for driving have a curved configuration district, and described these distributions in the outside of described chip for driving do not have described curved configuration district.

14. two-d display panel as claimed in claim 1 is characterized in that, described these chip for driving comprise crystal grain mantle joint chip.

15. a two-d display panel is characterized in that, described panel comprises:

One substrate, definition has a viewing area and a periphery circuit region, is located at least one side of described viewing area;

At least one chip for driving, be located at described periphery circuit region, described chip for driving comprises that the spacing between a plurality of pins and adjacent described these pins is not exclusively equal, between described these pins of the middle body of wherein said chip for driving between apart from being less than distance between between described these pins in the described chip for driving outside;

Many control circuit lines are arranged at described viewing area; And

Many distributions are arranged at described periphery circuit region and are electrically connected with described these control circuit lines and described these pins, and wherein said these distributions have a curved configuration district.

16. two-d display panel as claimed in claim 15, it is characterized in that the live width of described these distributions that is connected in described these pins in the described chip for driving outside is the live widths greater than described these distributions of described these pins of the middle body that is connected in described chip for driving.

17. two-d display panel as claimed in claim 15 is characterized in that, the live width of described these distributions is identical.

18. two-d display panel as claimed in claim 15 is characterized in that, described these distributions in the described curved configuration district have a plurality of sawtooth or the wave-like of continuous repetition, and described these sawtooth or the wave-like of each described distribution have an amplitude.

19. two-d display panel as claimed in claim 18 is characterized in that, the amplitude of described these distributions in the described chip for driving outside is the amplitude greater than described these distributions of the middle body of described chip for driving.

20. two-d display panel as claimed in claim 18 is characterized in that, in described curved configuration district, the minor increment of adjacent described these distributions is about 6 to 8 microns.

21. two-d display panel as claimed in claim 15 is characterized in that, the minimum spacing of described adjacent described these pins is about 20 microns, and maximum spacing is about 50 microns.

22. two-d display panel as claimed in claim 15 is characterized in that, described these distributions of the middle body of described chip for driving have a curved configuration district, and described these distributions in the described chip for driving outside do not have described curved configuration district.

23. two-d display panel as claimed in claim 15 is characterized in that, described these chip for driving comprise crystal grain mantle joint chip.

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