CN100433365C - Aluminium gallium nitride/gallium nitride high electronic migration rate transistor and its manufacturing method - Google Patents

Abstract

Aiming at the dual contradictions of high breakdown voltage but small transconductance or large transconductance and low breakdown voltage existing in existing semiconductor devices, the present invention discloses an aluminum gallium nitride/nitride compound with both advantages. Gallium high electron mobility transistor, and its manufacturing method is given at the same time, including a channel layer (3), a barrier layer (4), and a source electrode (5) and a drain electrode (6) are arranged on the barrier layer (4) , a groove (7) is provided on the barrier layer (4) between the source electrode (5) and the drain electrode (6), and a square or T-shaped gate electrode is installed in the groove (7) and covered with a dielectric The role of the dielectric layer is to reduce the leakage current on the gate electrode and increase the maximum current of the device; the function of the groove (7) is to increase the transconductance of the device. The invention also discloses a production method. The advantage of the present invention is that the device has small gate leakage current and large driving current while maintaining large transconductance of the device.

Description

AlGaN/GaN High Electron Mobility Transistor and Manufacturing Method

technical field

The invention relates to a semiconductor structure and a manufacturing method thereof, in particular to an aluminum gallium nitride/gallium nitride high electron mobility transistor and a manufacturing method thereof.

Background technique

At present, the use of semiconductor solid-state devices in microwave systems can effectively reduce the size of the system and improve reliability. With the development of science and technology, various microwave application systems urgently need electronic devices suitable for high temperature, high frequency, high power, and radiation resistance. All aspects are greatly restricted, so it is necessary to find new semiconductor materials to replace Si and GaAs. GaN is a new type of wide-bandgap semiconductor material. The insulated gate aluminum gallium nitride (AlGaN)/gallium nitride (GaN) HEMT based on it has comparable output power density, high temperature resistance and radiation resistance compared with devices based on Si and GaAs. It is expected that AlGaN/GaN HEMT will fully exceed the power output capability of GaAs devices in the frequency range of 2.5-30GHz, so AlGaN/GaN HEMT has become a hot spot in international research in recent years.

Khan et al. (Khan et al. Applied Physics Letters, vol.63, no.9, pp.1214-1215, 1993.) disclosed the first AlGaN/GaN HEMT with DC characteristics in 1993, and published the first An AlGaN/GaN HEMT with microwave characteristics (Khan et al.Applied Physics Letters, Vol.65, no.9, pp.1121-1123, Aug.1994.), and the research on AlGaN/GaN HEMT devices has been extensive since then developed and made rapid progress.

Wu et al. (Wu et al. IEEE Electron Device Letters, vol.17, no.9, pp.455-457, 1996.) disclosed the first AlGaN/GaN HEMT device with microwave power output in 1996. The 2GHz output power density is 1.1W/mm. Then in 2000, Green et al. (Green et al.IEEE Electron Device Lett., Vol.21no.6, pp.268-270, 2000.) disclosed that the use of SiN passivation technology can effectively suppress the current of AlGaN/GaN HEMT The collapse laid the foundation for the improvement of device performance. Since then, device structures and process technologies such as MIS, field plate, and gate trench have been disclosed one after another. Combined with passivation technology, the power output capability of AlGaN/GaN HEMT has been further improved. At present, the output power density of published small-size AlGaN/GaN HEMTs can reach more than 30W/mm (Wu et al. IEEE Electron Device Lett., Vol.25, No.3, pp.117-119, 2004.), large The single-chip continuous wave output power of large-scale devices has also reached more than 100W (Nagy et al. IEEE MTT-S International Microwave Symposium Digest, pp.483-486, 2005.), and the pulse power output even reached 368W (Therrien et al. IEEEIEDM Tech. Digest, pp.568-571, 2005.)

The current collapse phenomenon of AlGaN/GaN HEMT seriously restricts the performance of the device. At present, SiN passivation is generally used to suppress the current collapse in the process, but the problem is that the leakage current on the gate of the device increases after passivation. Considering the material structure, Kikkawa et al. (Kikkawa et al. IEEE IEDM Tech. Digest, pp.585-588, 2001.) disclosed that the introduction of a GaN cap layer can also effectively suppress the current collapse. Since the band gap of the GaN cap layer is smaller than that of AlGaN, the introduction of the GaN cap layer will lead to a greater drop in the breakdown voltage of the device after passivation or a further increase in the leakage current on the device gate, especially when GaN The cap layer is in a doped state. When the breakdown voltage of the device decreases, the corresponding working voltage of the device will also decrease, which will reduce the dynamic range of the device in the microwave working state, thereby reducing the microwave power output capability of the device; at the same time, the increase of the leakage current on the gate is also detrimental to the device. reliability.

In order to reduce the leakage current on the device gate and increase the breakdown voltage, it is necessary to introduce a dielectric layer with high breakdown electric field strength under the device gate to make an insulating gate AlGaN/GaN HEMT. Referring to Fig. 1, it shows a commonly used insulated gate AlGaN/GaN HEMT structure, the HEMT includes a semi-insulating SiC substrate 1, on which epitaxy is sequentially carried out by metal-organic compound chemical vapor deposition (MOCVD) or other suitable epitaxy methods. The grown AlN buffer layer 2, the GaN high resistance layer 3 and the AlGaN barrier layer 4, the source ohmic contact 5 and the drain ohmic contact 6 made on the barrier layer 4, the dielectric layer between the source ohmic contact and the drain ohmic contact 51 and the metal grid 8 fabricated on the dielectric layer.

Khan et al. (Khan et al. Appl. Phys. Letters, Vol. 77, p. 1339, 2000) disclosed an insulating gate AlGaN/GaN HEMT in which the dielectric layer is SiO ₂ in the figure. Referring to FIG. 1, during the preparation of this HEMT, the dielectric layer 51 is SiO ₂ , and is obtained by plasma-enhanced chemical vapor deposition (PECVD).

Hu et al. (Hu et al. Appl. Phys. Letters, Vol. 79, p. 2832, 2000) disclosed an insulating gate AlGaN/GaN HEMT in which the dielectric layer 51 in FIG. 1 is silicon nitride (SiN). Referring to FIG. 1 , the SiN dielectric layer 51 of the HEMT is also deposited by PECVD.

Ye et al. (Ye et al.Appl.Phys.Letters, Vol.86, p.2832, 2005) disclosed that the dielectric layer 51 in FIG. 1 is aluminum oxide (Al ₂ O ₃ ) fabricated by atomic layer deposition technology. insulated gate AlGaN/GaN HEMT. Referring to Fig. 1, in the process of preparing this HEMT, the dielectric layer 51 is obtained by the following method: a layer of Al ₂ O is deposited on the AlGaN/GaN heterojunction material grown by MOCVD by using atomic layer deposition technology. ₃ Dielectric layer 51, and then annealed at 600°C for 60s under an oxygen atmosphere. The source ohmic contact 5, the drain ohmic contact 6, and the metal gate 8 are not fabricated until the _Al2O3 dielectric layer ₅₁ is deposited, and additional photolithography and etching processes are required during the fabrication of the source ohmic contact 5 and the drain ohmic contact 6. etch to remove the underlying dielectric layer 51 to expose the barrier layer 4 .

The introduction of a dielectric layer 51 with a high breakdown electric field strength between the metal gate 8 and the barrier layer 4 in the device 1 reduces the leakage current on the metal gate 8 and correspondingly increases the breakdown voltage, but the disadvantage is that it increases The threshold voltage of the device is reduced, that is, the transconductance of the device is reduced, which will affect the frequency characteristics of the device.

Contents of the invention

The purpose of the present invention is to invent a kind of aluminum gallium nitride/aluminum nitride compound having both advantages in view of the double contradiction of high breakdown voltage but small transconductance or large transconductance and low breakdown voltage existing in existing semiconductor devices. Gallium nitride high electron mobility transistor, and its manufacturing method is also given.

Technical scheme of the present invention is:

An aluminum gallium nitride/gallium nitride high electron mobility transistor comprising:

One selected from sapphire, Si and SiC as the substrate 1,

a buffer layer 2 on the substrate 1,

a gallium nitride channel layer 3 on the buffer layer 2,

an aluminum gallium nitride barrier layer 4 formed on the channel layer 3,

The source electrode 5 and the drain electrode 6 formed on the barrier layer 4, the distance between the source electrode 5 and the drain electrode 6 is 2-5 microns,

It is characterized in that a groove 7 is provided on the barrier layer 4 between the source electrode 5 and the drain electrode 6, and a gate electrode is installed in the groove 7, and the gate electrode may be square Gate electrode 8, or T-shaped gate electrode 12; when the gate electrode installed in the groove 7 is a square gate electrode 8, its lower end extends into the groove 7, and its upper end protrudes from the first dielectric layer 9 On the highest surface, the coverage of the first dielectric layer 9 includes the upper surface of the barrier layer 4 between the source electrode 5 and the drain electrode 6 and the bottom surface of the groove 7; when the gate electrode installed in the groove 7 is T-shaped When the gate electrode 8 is used, its vertical lower end extends into the groove 7, and its horizontal upper end protrudes on the fourth dielectric layer 18. The fourth dielectric layer 18 is located in the groove 7, and its upper part is located in the second dielectric layer. Above the three dielectric layers 13 , the third dielectric layer 13 is located on the barrier layer 4 between the source electrode 5 and the drain electrode 6 except for the groove 7 .

A second dielectric layer 11 capable of covering the exposed portion of the barrier layer 4 is provided on the first dielectric layer 9 .

When the fourth dielectric layer 18 is not covered or partially covered on the third dielectric layer 13, a fifth dielectric layer 19 capable of covering the exposed part of the barrier layer 4 is provided on the third dielectric layer 13 , when the fourth dielectric layer 18 completely covers the third dielectric layer 13 , a sixth dielectric layer 20 capable of covering the exposed part of the barrier layer 4 is provided on the third dielectric layer 13 .

The first dielectric layer 9, the second dielectric layer 11, the third dielectric layer 13, the fourth dielectric layer 18, the fifth dielectric layer 19, and the sixth dielectric layer 20 are silicon nitride, aluminum nitride, silicon dioxide Or any one of aluminum oxide, the thickness of which is 5-15nm.

The thickness of the barrier layer 4 is between 15-50nm.

The lower end of the T-shaped gate electrode 12 is biased in the groove 7, and the distance between the first side 14 and the second side 15 is less than 0.5 microns, and the distance between the third side 16 and the fourth side 17 is 0.5 microns. ~1.5 microns, that is, the shortest lateral distances between the two sides of the horizontal upper end of the gate electrode and the lower end of the protrusion are less than 0.5 micron and 0.5-1.5 micron respectively.

According to the difference of gate electrode, the method of the present invention has two kinds, respectively as follows:

1. A method for manufacturing an aluminum gallium nitride/gallium nitride high electron mobility transistor with a square gate electrode, characterized in that it comprises the following steps:

- sequentially forming a buffer layer 2, a GaN channel layer 3 and an AlGaN barrier layer 4 on the substrate 1 by MOCVD or RF-MBE;

- forming a first ohmic contact region 5 on the barrier layer 4 as a source electrode;

- forming a second ohmic contact region 6 on the barrier layer 4 at a distance of 2-5 microns from the first ohmic contact region as a drain electrode;

- forming a groove 7 on the barrier layer 4 between the source electrode and the drain electrode by dry or wet etching;

- Deposit a first dielectric layer 9 on the barrier layer 4 between the source electrode 5 and the drain electrode 6, the deposition method of the first dielectric layer 9 includes but not limited to sputtering, electron beam evaporation, plasma enhanced Any of chemical vapor deposition PECVD;

— Forming the gate electrode 8 on the first dielectric layer 9 , the gate electrode 8 is located in the space between the parallel planes where the two sidewalls of the groove 7 are located.

If necessary, the above method also includes depositing a second dielectric layer 11 on the first dielectric layer 9 to cover the exposed portion of the barrier layer 4 by using the same method.

Two, a method for manufacturing an aluminum gallium nitride/gallium nitride high electron mobility transistor of a T-shaped gate electrode, is characterized in that it comprises the following steps:

——The buffer layer 2, the GaN channel layer 3, and the AlGaN barrier layer 4 are sequentially formed on the substrate 1 by MOCVD or RF-MBE method;

- forming a first ohmic contact region 5 on the barrier layer 4 as a source electrode;

- forming a second ohmic contact region 6 on the barrier layer 4 at a distance of 2-5 microns from the first ohmic contact region as a drain electrode;

- forming a groove 7 on the barrier layer 4 between the source electrode and the drain electrode by dry or wet etching;

- Deposit a third dielectric layer 13 on the surface of the barrier layer 4 between the source electrode 5 and the drain electrode 6 except the groove 7, the deposition method of the third dielectric layer 13 includes but not limited to sputtering, Electron beam evaporation, plasma enhanced chemical vapor deposition PECVD;

- Deposit a fourth dielectric layer 18 on the third dielectric layer 13 and the groove 7, the deposition method of the fourth dielectric layer 18 includes but not limited to sputtering, electron beam evaporation or plasma enhanced chemical vapor deposition PECVD;

— Form a T-shaped gate electrode 12 on the fourth dielectric layer 18 , and the two second side surfaces 15 and 16 of the gate electrode 12 are located in the space between the parallel planes where the two side walls of the groove 7 are located.

If necessary, the above method also includes depositing a fifth dielectric layer 19 that can cover the exposed portion on the barrier layer 4 by using the same method on the third dielectric layer 13 or depositing a fifth dielectric layer 19 that can cover The exposed part on the barrier layer 4 is covered by the sixth dielectric layer 20 .

In summary, one aspect of the present invention provides a grooved insulating gate AlGaN/GaN HEMT. The HEMT comprises: one selected from sapphire, Si and SiC as a substrate, a buffer layer formed on the substrate made of III-nitride, and a III-nitride layer ( called "channel layer") and a layer of III-nitride layer with a wider energy gap (called "barrier layer") grown on it, the first ohm layer made on the barrier layer The contact area is used as the source electrode, the second ohmic contact area formed on the barrier layer and separated from the first ohmic contact area is used as the drain, and the groove formed on the barrier layer between the source electrode and the drain electrode , the dielectric covering the barrier layer between the source electrode and the drain electrode, the gate electrode on the dielectric and facing the groove, and the gate electrode forms a sandwich structure with the dielectric layer and the barrier layer.

Another aspect of the present invention provides a method for manufacturing a grooved insulating gate aluminum gallium nitride/gallium nitride HEMT. The method includes the following steps: using any suitable growth method such as MOCVD, RF-MBE, etc. to sequentially grow epitaxially on the substrate to obtain the buffer layer, GaN channel layer and barrier layer of the device, and the band gap of the barrier layer is larger than that of GaN The channel layer, coupled with the strong spontaneous polarization and piezoelectric polarization effects of the III-nitride itself, will form a two-dimensional electron gas with high density near the interface of the heterojunction material. The substrate is any one of sapphire, Si and SiC. Preferably, semi-insulating 4H-SiC and semi-insulating 6H-SiC are used as the substrate. The selection of the buffer layer is related to the substrate material. The barrier layer is generally The _{AlxGa1 -} xN (0<x<1) with a bandgap larger than the GaN channel layer has a thickness of about 15nm to 50nm.

Two ohmic contact regions with a distance of 2 microns to 5 microns are provided on the barrier layer as the source ohmic contact electrode and the drain ohmic contact electrode respectively, and the dry barrier layer between the source ohmic contact electrode and the drain ohmic contact electrode is used method or wet etching method to form a rectangular groove, the width of the groove, the distance between the two sides of the groove and the source ohmic contact electrode and the drain ohmic contact electrode depends on the purpose of the device to be fabricated, and the depth of the groove depends on the potential The thickness of the barrier layer.

After the groove is made, deposit a layer of dielectric material with a thickness of 5 nanometers to 15 nanometers on the barrier layer between the source ohmic contact electrode and the drain ohmic contact electrode. The optional dielectric material includes but is not limited to aluminum nitride (AlN ), silicon nitride (SiN), silicon oxide (SiO ₂ ) and aluminum oxide (Al ₂ O ₃ ), dielectric deposition methods include but not limited to sputtering, electron beam evaporation, plasma enhanced Chemical vapor deposition (PECVD). After that, a metal gate electrode is formed on the dielectric layer, so that the barrier layer, the dielectric layer and the metal gate electrode form a sandwich structure, and the fabrication of the grooved insulating gate AlGaN/GaN HEMT is completed.

The present invention has the following advantages:

On the one hand, the present invention inherits the advantages of small gate leakage current, high breakdown voltage and greater current driving capability of traditional insulated gate structure devices, increases the dynamic range of devices driven by microwave signals, thereby improving the performance of devices. Microwave power output capability. On the other hand, the recessed gate structure is added to compensate for the decrease in device transconductance caused by the introduction of an oxide layer or an insulating layer, thereby increasing the microwave power gain of the device and improving the frequency characteristics of the device. The method proposed by the invention has the advantages of simplicity and practicality.

Description of drawings

Figure 1 is a cross-sectional view of a conventional insulated gate AlGaN/GaN HEMT;

Fig. 2 is one of structural representations of the present invention;

Fig. 3 is the sectional view of depositing a dielectric layer again on the surface of AlGaN/GaN HEMT in Fig. 2;

4A-4C are schematic diagrams of the manufacturing process of the HEMT with the structure of FIG. 2;

5A-5B the possible misalignment of the gate electrodes of the present invention;

Fig. 6 is the second structural representation of the present invention;

Fig. 7 is a sectional view of a dielectric layer deposited on the surface of the AlGaN/GaN HEMT in Fig. 6;

Fig. 8 is the third structural diagram of the present invention;

Fig. 9 is a cross-sectional view of a dielectric layer deposited on the surface of the AlGaN/GaN HEMT in Fig. 8;

10A-10D are schematic diagrams of the manufacturing process of the HEMT with the structure shown in FIG. 2 and/or FIG. 3 of the present invention.

Detailed ways

The following structural drawings and embodiments further illustrate the present invention.

Embodiment one.

Figure 2 shows a device 32 of an embodiment of the invention. In the device 32, 1 is a substrate, 2 is a buffer layer, 3 is a GaN channel layer, and 4 is an _{AlxGa1 -xN} (0<x<1) barrier layer. The substrate 1 is any one of sapphire, Si and SiC. Preferably, semi-insulating 4H-SiC (0001) and semi-insulating 6H-SiC (0001) are used as substrates, which have high thermal conductivity, and GaN has the characteristics of small lattice mismatch, not only easy to grow high-quality GaN epitaxial materials, but also conducive to the heat dissipation of devices. Currently, Cree and II-VI companies in the United States sell SiC substrates in 4H and 6H forms. . The buffer layer 2 is located between the substrate and the channel layer, and is mainly used as a transitional effect to reduce the stress introduced by the lattice mismatch between the channel layer and the substrate. The selection of the buffer layer is related to the substrate material. are well known in the art and will not be described further. The channel layer 3 is a GaN layer with a thickness of about 1 micron. The composition x of aluminum in the barrier layer 4 is preferably between 0.15 and 0.3, and the thickness is preferably 15 nanometers to 30 nanometers. Since the band gap of the barrier layer 1 is greater than that of the channel layer 3, at the interface of the two layers There will be a sheet-like charge region, and all the electrons in the sheet-like charge region form a two-dimensional electron gas. Sometimes in order to increase the concentration of the two-dimensional electron gas at the interface, the barrier layer 4 can be doped, doped The maximum concentration is about 4×10 ¹⁸ cm ^-3 . The buffer layer 2, the channel layer 3, and the barrier layer 4 are obtained by epitaxial growth on the substrate 1 sequentially by MOCVD, RF-MBE or any other suitable growth method, and the specific growth process can refer to relevant literature.

On the barrier layer provide ohmic contact electrode 5 as source electrode, ohmic contact electrode 6 as drain electrode, source electrode 5 and drain electrode 6 can be Ti/Al/Ni/Au, Ti/Al/Mo/Au, Ti/Al /Ti/Au or any other suitable material that can form an ohmic contact with the barrier layer, the metal on the source electrode 5 and the drain electrode 6 is preferably formed by electron beam evaporation, and rapidly annealed at a high temperature of 780°C to 900°C for 30s About, nitrogen (N ₂ ) or any other suitable inert gas is required to protect the metals of the source electrode 5 and the drain electrode 6 from being oxidized during the rapid annealing process. As mentioned above, the distance between the source electrode 5 and the drain electrode 6 is generally 2 microns to 5 microns.

A groove 7 is provided on the barrier layer between the source ohmic contact electrode and the drain ohmic contact electrode, the groove 7 can be formed by dry or wet etching, and the preferred etching method is dry etching , including Reactive Ion Etching (RIE) and Inductively Coupled Plasma Etching (ICP), the methods and principles of dry etching Group III nitrides are well known, so I won’t go into details here. For details, please refer to the literature of Egawa et al. (Egawa et al. Appl. Phys. Lett., vol.76, pp.121-123, 2000) or Coffie et al. (Coffie et al. Applied Physics Letters Vol.83, p.4779, 2003). The distance between the side wall of the source side of the groove and the source electrode, the distance between the side wall of the drain side and the drain electrode, and the width of the groove are determined according to actual needs, and depend on the precision that can be achieved by photolithography in manufacturing. As mentioned above, the groove The depth of the groove depends on the thickness of the barrier layer, and it is preferable that the thickness of the barrier layer under the groove remains 8 nm to 20 nm.

A first dielectric layer 9 is deposited on the exposed surface of the barrier layer 4. The materials that can be used for the dielectric layer include but are not limited to aluminum nitride (AlN), silicon nitride (SiN), silicon oxide (SiO ₂ ) and three A kind of in aluminum oxide (Al ₂ O ₃ ), the method for depositing the first dielectric layer 9 includes but not limited to sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD), preferably adopts electron Beam Evaporation Deposition Technology. The thickness of the dielectric layer is preferably 5 nm to 15 nm as mentioned above.

A gate electrode 8 is provided on the first dielectric layer 9, and metals that can be used for the gate electrode include but not limited to Ni/Au, Ni/Pt/Au. The sidewall of the source side of the gate electrode 8 can be selected to be in contact with or not in contact with the sidewall of the source side of the groove 7 , and the sidewall of the drain side of the gate electrode 8 can also be selected to be in contact with or separated from the sidewall of the drain side of the groove 7 .

4A-4C are some implementations of this embodiment, including forming a groove 7 on the barrier layer, and forming a first dielectric layer 9 and a gate metal 8 on the groove by using a self-alignment technique. As mentioned above, the buffer layer 2, the channel layer 3 and the barrier layer 4 are formed by sequential epitaxial growth on the substrate 1 by MOCVD, RF-MBE or any other suitable growth method, and the source ohmic contact is formed on the barrier layer 4. Electrode 5 and drain ohmic contact electrode 6 .

The groove on the barrier layer is patterned so that the groove 7 can be formed by etching. As shown in Figure 4A, form mask 41 on the surface of device, so that the place that device does not need to form groove is protected, and the preferred material of mask 41 is photoresist, and its thickness is about 2 microns, so that play barrier The effect of etching; as shown in FIG. 4B , the barrier layer 4 is etched using the aforementioned etching method, and the remaining thickness of the barrier layer under the groove 7 is 8 nm to 20 nm.

After the groove 7 is formed by etching, as shown in FIG. 4C, the mask 41 is removed, and a first dielectric layer 9 is deposited on the exposed surface of the barrier layer 4. The optional dielectric layer material includes but is not limited to aluminum nitride (AlN ), silicon nitride (SiN), silicon oxide (SiO ₂ ) and aluminum oxide (Al ₂ O ₃ ), the method of depositing the first dielectric layer 9 preferably adopts the method of electron beam evaporation to The thickness of the first dielectric layer 9 is precisely controlled, and the thickness of the first dielectric layer 9 is 5 nanometers to 15 nanometers as mentioned above. Using conventional technology to form the gate metal 8 on the first dielectric layer 9, since the groove and the gate metal are not formed by a self-alignment process, deviations may occur, as shown in Figures 5A-5B, so that the gate metal part If the coverage is beyond the groove, the slight deviation will not have a big impact on the function of the device, but the large deviation will be detrimental to the device.

In order to protect the device, sometimes as shown in Figure 3, a second dielectric layer 11 is deposited on the surface of the device 32 to passivate the device to form a device 33. The second dielectric layer 11 includes aluminum nitride (AlN), silicon nitride (SiN), silicon oxide (SiO ₂ ) and aluminum oxide (Al ₂ O ₃ ), the deposition methods include sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD) .

In summary, the manufacturing method of this embodiment includes the following steps:

- sequentially forming a buffer layer 2, a GaN channel layer 3 and an AlGaN barrier layer 4 on the substrate 1 by MOCVD or RF-MBE;

- forming a first ohmic contact region 5 on the barrier layer 4 as a source electrode;

- forming a second ohmic contact region 6 on the barrier layer 4 at a distance of 2-5 microns from the first ohmic contact region as a drain electrode;

- forming a groove 7 on the barrier layer 4 between the source electrode and the drain electrode by dry or wet etching;

- Deposit a first dielectric layer 9 on the barrier layer 4 between the source electrode 5 and the drain electrode 6, the deposition method of the first dielectric layer 9 includes but not limited to sputtering, electron beam evaporation, plasma enhanced Any of chemical vapor deposition PECVD;

— Forming the gate electrode 8 on the first dielectric layer 9 , the gate electrode 8 is located in the space between the parallel planes where the two sidewalls of the groove 7 are located.

If necessary, the above method also includes depositing a second dielectric layer 11 on the first dielectric layer 9 to cover the exposed portion of the barrier layer 4 by using the same method.

Embodiment two.

FIG. 6 is a device 34 with a T-shaped gate according to an embodiment of the present invention. Similar to device 32 in FIG. 2 , device 34 has substrate 1 , buffer layer 2 , GaN channel layer 3 and AlGaN barrier layer 4 . The device 34 also has a source electrode 5 and a drain electrode 6 located on the barrier layer with the device 32. The surface of the device 34 is covered by the third dielectric layer 13 except the groove 7, and the bottom and side walls of the groove are covered by the fourth dielectric layer. Covered by the layer 18, the fourth dielectric layer 18 extends toward the source electrode 5 and the drain electrode 6 on the surface of the device and covers the third dielectric layer 13, the fourth dielectric layer 18 only exists under the gate electrode 12, and the gate electrode of the device 12 is a T-shaped gate structure. The distance between the first side 14 and the second side 15 in the T-shaped grid 12 is less than 0.5 micron, and the distance between the third side 16 and the fourth side 17 is about 1 micron, that is, the T-shaped grid 12 is not completely symmetrical. A symmetrical "T" gate structure is required to improve the performance of AlGaN/GaN HEMTs.

The buffer layer 2, the GaN channel layer 3 and the AlGaN barrier layer 4 device 32 are formed on the substrate 1 by sequential epitaxial growth using MOCVD, RF-MBE or any other suitable growth method, followed by the source electrode 5 and the drain electrode 6 The production of them is exactly the same as in the previous embodiment.

A third dielectric layer 13 is deposited on the exposed part of the barrier layer 4 to facilitate the formation of the required "T" gate. The preferred dielectric material for the third dielectric layer 13 is SiN, which has been proven to effectively inhibit For the current collapse phenomenon caused by the surface state of the device, the thickness of the third dielectric layer 13 is preferably more than 100 nm.

The forming process of the groove 7 is shown in Figs. 10A-10B. As shown in Figure 10A, form mask 42 on the surface of device, so that the place that device does not need to form groove is protected, and the preferred material of mask 42 is photoresist, and its thickness is about 2 microns, so that play barrier The effect of etching; as shown in Figure 10B, firstly, the dielectric layer is etched, and the etching method for SiN dielectric material is known, and will not be described in detail here, and then the barrier is etched by the etching method described above. Layer 4 is etched to form recesses 7 .

The formation of the fourth dielectric layer 18 and the T-shaped gate 12 is shown in FIGS. 10C-10D . As shown in FIG. 10C , the mask 42 is removed and a mask 43 is formed on the surface of the device to protect the place where the third dielectric layer 13 does not need to be deposited. As shown in FIG. 10D, a third dielectric layer 13 is deposited on the entire surface of the device. The optional dielectric layer material is as mentioned above. The method for depositing the third dielectric layer 13 preferably adopts the method of electron beam evaporation, so that In the subsequent implementation of the stripping process, the thickness of the third dielectric layer 13 is 5 nanometers to 15 nanometers as mentioned above, and the optional dielectric layer materials include but are not limited to aluminum nitride (AlN), silicon nitride (SiN) , silicon oxide (SiO ₂ ) and aluminum oxide (Al ₂ O ₃ ). During the deposition of the dielectric layer, the third dielectric layer 13 also covers the mask 43 at the same time. After the deposition of the third dielectric layer 13 is completed, a layer of gate metal 12 is deposited on the entire surface of the device using electron beam evaporation deposition technology. During the deposition of the gate metal 12, the gate metal 12 also covers the On the third dielectric layer 13 above 43 , the sum of the thickness of the gate metal 12 and the thickness of the third dielectric layer 13 should be guaranteed to be less than half of the thickness of the mask 43 . Finally, the mask 43 and the gate metal 12 on the third dielectric layer 13 are removed by a lift-off process to obtain the device 36 .

In the embodiments of FIGS. 10C-10D , the gate metal 12 and the third dielectric layer 13 are realized through a self-alignment process, thereby ensuring that the third dielectric layer 13 is completely under the gate metal 12 .

As shown in FIG. 6, sometimes in order to protect the device, a fifth dielectric layer 19 is deposited on the surface of the device 34 to passivate the device 35. The optional dielectric layer materials include aluminum nitride (AlN), silicon nitride (SiN), silicon oxide (SiO ₂ ) and aluminum oxide (Al ₂ O ₃ ), the deposition methods include sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD).

In a nutshell, the method for manufacturing a transistor with a T-shaped structure mainly includes the following steps:

——The buffer layer 2, the GaN channel layer 3, and the AlGaN barrier layer 4 are sequentially formed on the substrate 1 by MOCVD or RF-MBE method;

- forming a first ohmic contact region 5 on the barrier layer 4 as a source electrode;

- forming a second ohmic contact region 6 on the barrier layer 4 at a distance of 2-5 microns from the first ohmic contact region as a drain electrode;

- forming a groove 7 on the barrier layer 4 between the source electrode and the drain electrode by dry or wet etching;

- Deposit a third dielectric layer 13 on the surface of the barrier layer 4 between the source electrode 5 and the drain electrode 6 except the groove 7, the deposition method of the third dielectric layer 13 includes but not limited to sputtering, Electron beam evaporation, plasma enhanced chemical vapor deposition PECVD;

- Deposit a fourth dielectric layer 18 on the third dielectric layer 13 and the groove 7, the deposition method of the fourth dielectric layer 18 includes but not limited to sputtering, electron beam evaporation or plasma enhanced chemical vapor deposition PECVD;

— Form a T-shaped gate electrode 12 on the fourth dielectric layer 18 , and the two second side surfaces 15 and 16 of the gate electrode 12 are located in the space between the parallel planes where the two side walls of the groove 7 are located.

If necessary, the above method also includes depositing a fifth dielectric layer 19 that can cover the exposed portion on the barrier layer 4 by using the same method on the third dielectric layer 13 or depositing a fifth dielectric layer 19 that can cover The sixth dielectric layer 20 covered by the exposed part on the barrier layer 4

Embodiment three.

FIG. 8 shows a device 36 with a T-shaped gate according to another embodiment of the present invention. Same as the device in the previous embodiment, the device 36 has a substrate 1, a buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, a source electrode 5 and a drain electrode 6 on the barrier layer, and the surface of the device 36 except The groove 7 is covered by the third dielectric layer 13, and the fourth dielectric layer 18 not only exists under the gate metal but also covers the exposed part of the third dielectric layer 13. The gate electrode 12 of the device 36 is the same as the device 34. T-shaped gate structure. Similarly, the distance between the first side 14 and the second side 15 is less than 0.5 micron, and the distance between the third side 16 and the fourth side 17 is about 1 micron, so as to improve the performance of the AlGaN/GaN HEMT.

The formation of the buffer layer 2, the GaN channel layer 3, the AlGaN barrier layer 4, the source electrode 5 and the drain electrode 6 is the same as in the previous embodiment, and the formation process of the groove 7 is shown in Figures 10A-10B, the method and the device 34 same.

After the groove 7 is formed as shown in Figure 10B, the mask 42 on the device surface is removed, and the fourth dielectric layer 18 is deposited on the exposed surface of the barrier layer 4. The optional dielectric material is the same as the device 34, and the fourth dielectric layer is deposited. The method of the dielectric layer 18 is preferably sputtering, so as to form a good coverage on the side of the groove, and the thickness of the fourth dielectric layer 18 is 5 nanometers to 15 nanometers. Use conventional technology to form the gate metal 12 on the fourth dielectric layer 18. Since the groove and the gate metal are not formed by a self-alignment process, deviations may occur as with the device 32, and the same slight deviation will not be correct. The functionality of the device has a large influence, but large deviations are detrimental to the device.

As shown in Figure 9, a sixth dielectric layer 20 is deposited on the surface to passivate the device to form a device 37. The optional dielectric layer materials include aluminum nitride (AlN), silicon nitride (SiN), silicon oxide ( SiO ₂ ) and aluminum oxide (Al ₂ O ₃ ), the deposition method includes sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD).

The manufacturing method can be carried out with reference to the second embodiment.

The parts not described in detail in the present invention are the same as the prior art.

Claims (13)

1, a kind of aluminum gallium nitride/GaN high electron mobility transistor comprises:

One substrate (1),

One is positioned at the resilient coating (2) on the described substrate (1),

One is positioned at the gallium nitride channel layer (3) on the described resilient coating (2),

One at the last aluminum gallium nitride barrier layer (4) that forms of described channel layer (3),

Go up source electrode (5) and the drain electrode (6) that forms at barrier layer (4), the spacing between source electrode (5) and the drain electrode (6) is the 2-5 micron,

It is characterized in that: on the barrier layer (4) between described source electrode (5) and the drain electrode (6), be provided with a groove (7), in described groove (7), gate electrode be installed, described gate electrode or be square gate electrode (8), or be T shape gate electrode (12); When the gate electrode of installing in the groove (7) is square gate electrode (8), its lower end is stretched in the described groove (7), and the coverage of first dielectric layer (9) comprises the bottom surface of the upper surface and the groove (7) of the barrier layer (4) between source electrode (5) and the drain electrode (6); When the gate electrode of installing in the groove (7) is T shape gate electrode (8), its perpendicular shape lower end is stretched in the described groove (7), its horizontal shape upper end projection is on the 4th dielectric layer (18), described the 4th dielectric layer (18) is arranged in groove (7), its top is positioned on the 3rd dielectric layer (13), and the 3rd dielectric layer (13) is positioned on the barrier layer (4) except groove (7) part between source electrode (5) and the drain electrode (6).

2, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1 is characterized in that being provided with second dielectric layer (11) that barrier layer (4) expose portion can be covered on described first dielectric layer (9).

3, aluminum gallium nitride/GaN high electron mobility transistor according to claim 2, it is characterized in that described first dielectric layer (9), second dielectric layer (11) are any in silicon nitride, aluminium nitride, silicon dioxide or the alundum (Al, its thickness is 5-15nm.

4, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, it is characterized in that when described the 4th dielectric layer (18) does not cover or partly cover on the 3rd dielectric layer (13), on described the 3rd dielectric layer (13), be provided with the 5th dielectric layer (19) that barrier layer (4) expose portion can be covered, when described the 4th dielectric layer (18) covers on the 3rd dielectric layer (13) fully, on described the 3rd dielectric layer (13), be provided with the 6th dielectric layer (20) that barrier layer (4) expose portion can be covered.

5, aluminum gallium nitride/GaN high electron mobility transistor according to claim 4, it is characterized in that described the 3rd dielectric layer (13), the 4th dielectric layer (18), the 5th dielectric layer (19) and the 6th dielectric layer (20) are any in silicon nitride, aluminium nitride, silicon dioxide or the alundum (Al, its thickness is 5-15nm.

6, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, it is characterized in that described first dielectric layer (9), the 3rd dielectric layer (13), the 4th dielectric layer (18) are any in silicon nitride, aluminium nitride, silicon dioxide or the alundum (Al, its thickness is 5-15nm.

7, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, the thickness that it is characterized in that described barrier layer (4) is between 15-50nm.

8, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, the lower end that it is characterized in that described T shape gate electrode (12) is biased in the described groove (7), and its first side (14) and second side (15) spacing are less than 0.5 micron, and the 3rd side (16) are 0.5～1.5 micron with the 4th side (17) spacing.

9, aluminum gallium nitride/GaN high electron mobility transistor according to claim 1, wherein substrate (1) is any among SiC, sapphire or the Si.

10, a kind of described method that has the aluminum gallium nitride/GaN high electron mobility transistor of square gate electrode of claim 1 of making is characterized in that it may further comprise the steps:

---upward adopt MOCVD or RF-MBE method to form resilient coating (2), GaN channel layer (3) and AlGaN barrier layer (4) successively at substrate (1);

---go up formation first ohmic contact regions (5) as the source electrode at barrier layer (4);

---upward form second ohmic contact regions (6) as drain electrode at a distance of the place of 2-5 micron at barrier layer (4) with first ohmic contact regions;

---on the barrier layer between source electrode and the drain electrode (4), utilize the method for dry method or wet etching to form a groove (7);

---the barrier layer (4) between source electrode (5) and drain electrode (6) is gone up deposit one first dielectric layer (9), and the deposition process of first dielectric layer (9) comprises any in sputter or electron beam evaporation or the plasma reinforced chemical vapor deposition;

---go up formation gate electrode (8) at first dielectric layer (9), gate electrode (8) is positioned at the folded space of parallel plane at (7) two sidewall places of groove.

11, manufacturing according to claim 10 has the method for the aluminum gallium nitride/GaN high electron mobility transistor of square gate electrode, it is characterized in that it also comprise utilize identical method on first dielectric layer (9) again deposit one deck cover second dielectric layer (11) of barrier layer (4) expose portion.

12, a kind of method of making the aluminum gallium nitride/GaN high electron mobility transistor of the described T of the having shape of claim 1 gate electrode is characterized in that it may further comprise the steps:

---upward adopt MOCVD or RF-MBE method to form resilient coating (2), GaN channel layer (3), AlGaN barrier layer (4) successively at substrate (1);

---go up formation first ohmic contact regions (5) as the source electrode at barrier layer (4);

---upward form second ohmic contact regions (6) as drain electrode at a distance of the place of 2-5 micron at barrier layer (4) with first ohmic contact regions;

---on the barrier layer between source electrode and the drain electrode (4), utilize the method for dry method or wet etching to form a groove (7);

---deposit 1 the 3rd dielectric layer (13) on the surface of barrier layer (4) except that groove (7) between source electrode (5) and drain electrode (6), the deposition process of the 3rd dielectric layer (13) comprises sputter, electron beam evaporation or plasma reinforced chemical vapor deposition;

---go up deposit 1 the 4th dielectric layer (18) at the 3rd dielectric layer (13) and groove (7), the deposition process of the 4th dielectric layer (18) comprises sputter, electron beam evaporation or plasma reinforced chemical vapor deposition;

---go up formation T shape gate electrode (12) at the 4th dielectric layer (18), second side (15) of gate electrode (12) and the 3rd side (16) are positioned at the folded space of parallel plane at (7) two sidewall places of groove.

13, manufacturing according to claim 12 has the method for the aluminum gallium nitride/GaN high electron mobility transistor of T shape gate electrode, it is characterized in that it comprises that also utilizing identical method to go up deposit one at the 3rd dielectric layer (13) can go up the 6th dielectric layer (20) that deposit one can cover the expose portion on the barrier layer (4) with the 5th dielectric layer (19) of the covering of the expose portion on the barrier layer (4) or at the 4th dielectric layer (18).

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