CN100395884C - Method of Forming CMOS Transistors - Google Patents

Abstract

The invention relates to a method for forming a CMOS transistor on a base plate, wherein only need two implantation steps, can form all source and drain electrodes and lightly doped, first of all, form source and drain electrode of a NMOS transistor, it utilizes a photoresist layer covering source and drain electrode of PMOS transistor as shielding, and implant a phosphorus dopant; and then forming a lightly doped NMOS transistor and a source and a drain of a PMOS transistor, shielding the source and the drain of the NMOS transistor by using a photoresist layer covering the source and the drain of the NMOS transistor and a grid, and implanting a boron dopant, wherein the dosage of the boron dopant is less than that of the phosphorus dopant.

Description

Method of Forming CMOS Transistors

technical field

The present invention relates to a process method for forming CMOS transistors, and in particular to a process method for forming source/drain and lightly doped CMOS transistors by using two implants.

Background technique

Most of the thin film transistors in flat panel displays today are made of amorphous silicon (amorphous silicon) process, and a few high-end products are made of polysilicon (poly silicon) process with high electron mobility. Polysilicon technology allows the integration of more electronic circuits, thereby reducing overall product complexity and weight. However, since the maximum temperature in the polysilicon manufacturing process is about 300°C or higher, far exceeding the temperature at which plastics begin to soften, it can only be applied to glass substrates.

Please refer to FIGS. 1A˜1I , which show a manufacturing process of a conventional low temperature polysilicon thin film transistor. First, in FIG. 1A, a buffer layer 102 and a polysilicon layer are sequentially formed on a substrate 100, wherein the polysilicon layer is formed by crystallizing and tempering an amorphous silicon layer with an excimer laser; then, a polysilicon layer is formed. A patterned photoresist layer (not shown in the figure) is etched with the photoresist layer as a mask to form the polysilicon layer 104 shown in FIG. 1A.

Next, referring to FIG. 1B, a gate oxide layer 108 is deposited on the buffer layer 102 and the polysilicon layer 104, and a conductive layer is formed on the gate oxide layer 108. After photolithography and etching processes, a gate is formed. Pole 110. Then, in FIG. 1C, a photoresist layer 112 is formed, and the photoresist layer 112 covers the entire PMOS transistor region and the gate and lightly doped region of the NMOS transistor region, and the photoresist layer 112 is used as a shield to implant A heavy concentration of phosphorus dopant forms the source/drain electrodes 104a, 104b, 104c and 104d of the NMOS transistor.

Afterwards, in FIG. 1D , the remaining photoresist layer 112 is removed, and the substrate 100 is implanted with light-concentration phosphorous dopants directly using the gate 110 as a shield to form lightly doped 104m, 104n, and 104x of NMOS transistors. with 104y. Next, in FIG. 1E , a photoresist layer 114 is formed again, the photoresist layer 114 covers the entire NMOS transistor area, and with the photoresist layer 114 as a shield, the substrate 100 is implanted with a heavy concentration of boron dopant, and The source/drain 104i and 104j of the P-type transistor are formed.

In FIG. 1F, the photoresist layer 114 is removed first, and then an interlayer dielectric layer 116 is formed on the gate 110 and the gate oxide layer 108, and several openings are formed on the interlayer dielectric layer 116 and the gate. in the oxide layer 108 . Then, in FIG. 1G , electrodes 118 are formed that can be electrically connected to the source/drain electrodes 104a, 104b, 104c, 104d, 104i, and 104j.

Next, in FIG. 1H , a protective layer 120 is formed on the electrode layer 118 and the interlayer dielectric layer 116 , and an opening is formed in the protective layer 120 in the pixel region to expose the electrode 118 . Finally, in FIG. 1I , a transparent electrode 122 that can be electrically connected to the electrode 118 in the pixel area is formed to complete the process of having a low temperature polysilicon thin film transistor.

The known technology requires a total of eight mask plate manufacturing processes and three ion implantation steps to complete the entire low-temperature polysilicon thin film transistor manufacturing process. Among them, the eight mask plate manufacturing processes are respectively carried out in FIGS. 1A-1C and FIGS. 1E-1I, and three times The steps of ion implantation are respectively performed in FIGS. 1C˜1E . However, each process step will increase the process cost, therefore, it is necessary to propose a method that can reduce the process steps.

Contents of the invention

In view of this, the object of the present invention is to provide a process method for forming CMOS transistors with fewer process steps.

According to the purpose of the present invention, a method for forming a first-type transistor and a second-type transistor on a substrate is proposed, wherein the first-type transistor has a lightly doped region and a first heavily doped region, and the second-type transistor has a lightly doped region and a first heavily doped region. The transistor has a second heavily doped region. The method at least includes: forming a first polysilicon layer and a second polysilicon layer with a thickness of 200-1000 angstroms on the substrate, wherein the first polysilicon layer and the second polysilicon layer are formed on the substrate. The second polysilicon layer corresponds to the first type transistor and the second type transistor; depositing a gate oxide layer with a thickness of 500-1500 angstroms on the first polysilicon layer and the second polysilicon layer on the gate oxide layer, forming a first gate and a second gate composed of one of molybdenum, chromium or titanium/aluminum/titanium, and respectively located on the first polysilicon layer and the Above the second polysilicon layer, the lightly doped region and the first heavily doped region are arranged at both ends of the first gate, and the second heavily doped region is arranged at both ends of the second gate; forming the first heavily doped transistor of the first type in the first heavily doped region of the first type transistor, using a photoresist layer covering the second heavily doped region and the first gate as a shield, and implanting the first dopant to form; and forming the light doping of the first type transistor and the second heavily doping of the second type transistor respectively in the lightly doped region of the first type transistor and the second type transistor In the second heavily doped region, the photoresist layer covering the first heavily doped region of the first-type transistor is used to shield the first gate and the second gate, and the second dopant is implanted. Formed, the dose of the second dopant is smaller than the dose of the first dopant. The dosage of the first dopant in the present invention is between 3×10 ¹³ /cm ² and 5×10 ¹⁵ /cm ² , and the dosage of the second dopant is 3×10 ¹³ /cm ² to 5×10 ¹⁵ /cm ² Between, the first heavily doped and the second heavily doped are source and drain.

After the step of forming the light doping of the first type transistor and the second heavy doping of the second type transistor, the present invention further includes: forming an inner layer dielectric layer with a thickness of 500-7000 angstroms on the gate oxide layer , the first gate and the second gate; selectively expose the first heavily doped, the second heavily doped, the first gate and the second gate; and form molybdenum, chromium or titanium An electrode composed of one of /aluminum/titanium is used to electrically connect the exposed first heavily doped, the second heavily doped, the first gate and the second gate.

After the electrode forming step, the present invention further includes: forming a patterned protective layer on the interlayer dielectric layer and the electrode, and the patterned protective layer exposes a part of a first-type transistor located in the pixel region electrode; and forming a transparent electrode composed of indium tin oxide (ITO) to electrically connect the exposed part of the electrode of the first type transistor.

The first-type transistor of the present invention is an NMOS transistor, and the second-type transistor is a PMOS transistor, wherein the first dopant is a phosphorus dopant, and the second dopant is a boron dopant; or the first-type transistor is a PMOS transistor, and the second dopant is a PMOS transistor. The type II transistor is an NMOS transistor, wherein the first dopant is a boron dopant, and the second dopant is a phosphorus dopant.

In order to further illustrate the above-mentioned purpose, structural features and effects of the present invention, the present invention will be described in detail below in conjunction with the accompanying drawings.

Description of drawings

1A-1I, which show the manufacturing process of a traditional low-temperature polysilicon thin film transistor.

2A to 2H show the manufacturing process of the low temperature polysilicon thin film transistor of the present invention.

Detailed ways

The invention provides a method capable of reducing the process steps of low-temperature polysilicon thin film transistors.

Please refer to FIGS. 2A-2J , which show the manufacturing process of the low temperature polysilicon thin film transistor of the present invention. First, in FIG. 2A, a buffer layer 202 and a polysilicon layer 204 are sequentially formed on a substrate 200, and then a patterned photoresist layer (not shown in the figure) is formed, and photolithography The glue layer is etched for masking to form the polysilicon layer 204 shown in FIG. 2A.

The substrate 200 of the present invention can be made of glass or plastic, and the polysilicon layer 204 has a thickness of about 200-1000 angstroms, and is formed by crystallizing and tempering an amorphous silicon layer formed on the buffer layer 202 by using an excimer laser. . The two polysilicon layers 204 on the left are used to form a CMOS transistor, and the polysilicon layer 204 on the right is used to form an NMOS transistor in a pixel region.

The buffer layer 202 can be made of silicon oxide or silicon nitride, which is used as a heat insulating layer during the excimer laser tempering process, for example, even if the temperature of the upper polysilicon layer 204 is as high as about 1500° C. during the tempering process , the local temperature of a plastic substrate will not exceed about 250° C., and the time for the local temperature to rise is extremely short, so the shape of the plastic substrate will not change.

Then, referring to FIG. 2B , a gate oxide layer 208 is formed on the buffer layer 202 and the polysilicon layer 204 , the thickness of the gate oxide layer 208 is about 500-1500 angstroms, and its material can be silicon dioxide. Next, a conductive layer is deposited on the entire substrate 200, and a gate layer 210 is formed by photolithography and etching processes. The gate layer 210 can be made of molybdenum (Mo), chromium (Cr) and titanium/aluminum/titanium (Ti/ Al/Ti) composition.

Afterwards, in FIG. 2C , a patterned photoresist layer 212 is formed on the substrate 210 through a photolithography process, and the photoresist layer 212 completely covers the PMOS transistor area where the CMOS transistor is to be formed. And using the photoresist layer 212 as a shield, the substrate 200 is implanted with heavily concentrated phosphorous dopants, the dose of which is about 3×10 ¹³ dose/cm ² to 5×dose/cm 2 , to form heavily doped 204A, 204B, 204C and 204D are in the source/drain regions and lightly doped regions of the NMOS transistors. At this time, the heavily doped parts 204A, 204B, 204C and 204D are formed in the source/drain region of the NMOS transistor, which is the source/drain of the NMOS transistor. This part will be completed after the steps in FIG. 2D are completed. , and then explain.

Afterwards, in FIG. 2D, the remaining photoresist layer 212 is removed, and a patterned photoresist layer 214 is formed on the gate oxide layer 208 by photolithography process again. The photoresist layer 214 covers the CMOS The source/drain region of the NMOS transistor of the transistor and the source/drain region of the NMOS transistor of the pixel region do not cover the PMOS transistor region of the CMOS transistor. And using the photoresist layer 214 as a shield, the substrate 200 is implanted with boron dopant with a heavy concentration, and the dose is about 3el3dose/cm ² -5el5dose/cm ² , so as to form the source/drain 204i of the PMOS transistor and 204j, and lightly doped NMOS transistors 204m, 204n, 204x, and 204y. In the heavily doped 204A, 204B, 204C and 204D, except the lightly doped 204m, 204n, 204x and 204y, the rest are the source/drain 204a, 204b, 204c and 204d of the NMOS transistor.

It should be noted that the dose used in the present invention for implanting boron dopants must be less than the dose used for implanting phosphorus dopants. In this way, the NMOS transistor that has been twice implanted with boron dopants and phosphorus dopants Only the lightly doped region can have lightly doped 204m, 204n, 204x and 204y. Of course, the embodiments of the present invention are not limited to forming lightly doped NMOS transistors, and forming lightly doped PMOS transistors can also be another embodiment of the present invention. In this case, the photoresist layer 212 is used as the shielding The implantation step carried out is to implant boron dopant, and the implantation step carried out by using the photoresist layer 214 as a shield is to implant phosphorus dopant, and the dose used for implanting boron dopant must be greater than that of implanting Dosage of phosphorus dopant used.

Next, in FIG. 2E , first remove the photoresist layer 214, and then form an interlayer dielectric layer 216 on the entire substrate 200, and use photolithography and etching processes to form several openings in the interlayer dielectric layer. Among the gate oxide layer 216 and the gate oxide layer 208 , the interlayer dielectric layer 216 may be composed of silicon dioxide, and its thickness is about 500˜7000 angstroms. Then, in FIG. 2F, a conductive layer is formed on the ILD layer 216, and fills the openings in the ILD layer 216 and the gate oxide layer 208, and then photolithography and etching processes are used, An electrode 218 is formed that can be electrically connected to the gate 210 and portions of the source/drains 204a, 204b, 204c, 204d, 204i, and 204j. This embodiment shows the situation where the electrode 218 is electrically connected to the source/drain electrodes 204a, 204b, 204c, 204d, 204i and 204j.

Next, in FIG. 2G , a protection layer 220 is formed on the electrode 218 and the interlayer dielectric layer 216 , and an opening is formed in the protection layer 220 in the pixel region by using photolithography and etching processes. Finally, in FIG. 2H, a conductive layer composed of indium tin oxide (ITO) is formed on the protective layer 220, and fills the openings in the protective layer 220, and then photolithography and etching processes are used to form a The electrode 218 in the pixel area is electrically connected to the transparent electrode 222 to complete the manufacturing process with the low temperature polysilicon thin film transistor.

The manufacturing method disclosed in the above-mentioned embodiments of the present invention only needs eight masking plate manufacturing processes and two ion implantation steps to complete the entire low-temperature polysilicon thin film transistor manufacturing process, wherein the eight masking plate manufacturing processes are respectively shown in FIG. 2A -2H, and two steps of ion implantation were performed in FIG. 2C and FIG. 2D respectively. In view of the method of the present invention, there is one less ion implantation step than the conventional technology, so the cost of the manufacturing process can be greatly reduced.

In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone familiar with the technical field may make various modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

Although the present invention has been described with reference to the current specific embodiments, those of ordinary skill in the art should recognize that the above embodiments are only used to illustrate the present invention, and other modifications can be made without departing from the spirit of the present invention. Various equivalent changes and modifications, therefore, as long as the changes and modifications to the above embodiments are within the spirit of the present invention, they will all fall within the scope of the claims of the present invention.

Claims (20)

1. method that on a substrate, forms first transistor npn npn and second transistor npn npn, wherein this first transistor npn npn has a lightly doped region and first heavily doped region, and this second transistor npn npn has second heavily doped region, and this method comprises at least:

Form first polysilicon layer and second polysilicon layer on this substrate, wherein this first polysilicon layer and this second polysilicon layer are corresponding to this first transistor npn npn and this second transistor npn npn;

The deposition grid oxic horizon is on this first polysilicon layer and this second polysilicon layer;

Form first grid and second grid on this grid oxic horizon, and lay respectively at the top of this first polysilicon layer and this second polysilicon layer, these first grid two ends are provided with this lightly doped region and this first heavily doped region, and these second grid two ends are provided with this second heavily doped region;

First heavy doping that forms first transistor npn npn is in first heavily doped region of this first transistor npn npn, and it is that to utilize a photoresist layer that hides this second heavily doped region be to shield with this first grid, and implants one first admixture and form; And

In second heavily doped region of second heavy doping that forms the light dope of first transistor npn npn and second transistor npn npn respectively at the lightly doped region of this first transistor npn npn and this second transistor npn npn, it is that the photoresist layer that utilize to hide first heavily doped region of this first transistor npn npn is to shield with this first grid and second grid, and implant second admixture and form, the dosage of this second admixture is the dosage less than this first admixture.

2. the method for claim 1 is characterized in that, this forms before first polysilicon layer and the second polysilicon layer step, also comprises forming the step of a resilient coating on this substrate, and wherein this resilient coating comprises silica or silicon nitride.

3. the method for claim 1 is characterized in that, after this forms the second heavy doping step of the light dope of first transistor npn npn and second transistor npn npn, also comprises:

Form inner layer dielectric layer on this grid oxic horizon, this first grid and this second grid;

Optionally expose this first heavy doping, this second heavy doping, first grid and second grid; And

Form this first heavy doping, this second heavy doping, first grid and second grid that electrode is exposed with electric connection.

4. method as claimed in claim 3 is characterized in that, the thickness of this inner layer dielectric layer is 500～7000 dusts.

5. method as claimed in claim 3 is characterized in that, this electrode is formed by one of them of molybdenum, chromium or titanium/aluminium/titanium.

6. method as claimed in claim 3 is characterized in that, after this forms the electrode step, also comprises:

Formation has the protective layer of pattern on this inner layer dielectric layer and this electrode, and this protective layer exposure one with pattern is positioned at the partial electrode of first transistor npn npn of pixel region; And

Form transparency electrode to electrically connect the partial electrode that is exposed of first transistor npn npn.

7. method as claimed in claim 6 is characterized in that this transparency electrode is formed by indium tin oxide.

8. the method for claim 1 is characterized in that, the thickness of this first polysilicon layer and second polysilicon layer is 200～1000 dusts.

9. the method for claim 1 is characterized in that, the thickness of this grid oxic horizon is 500～1500 dusts.

10. the method for claim 1 is characterized in that, this first grid and this second grid are formed by one of them of molybdenum, chromium or titanium/aluminium/titanium.

11. the method for claim 1 is characterized in that, this first transistor npn npn is a nmos pass transistor, and this second transistor npn npn is the PMOS transistor.

12. method as claimed in claim 11 is characterized in that, this first admixture is the phosphorus admixture.

13. method as claimed in claim 11 is characterized in that, this second admixture is the boron admixture.

14. the method for claim 1 is characterized in that, this first transistor npn npn is the PMOS transistor, and this second transistor npn npn is a nmos pass transistor.

15. method as claimed in claim 14 is characterized in that, this first admixture is the boron admixture.

16. method as claimed in claim 14 is characterized in that, this second admixture is the phosphorus admixture.

17. the method for claim 1 is characterized in that, this first heavy doping is source electrode and drain electrode.

18. the method for claim 1 is characterized in that, this second heavy doping is source electrode and drain electrode.

19. the method for claim 1 is characterized in that, the dosage of this first admixture is 3 * 10 ¹³Dose/cm ²To 5 * 10 ¹⁵Dose/cm ²Between.

20. the method for claim 1 is characterized in that, the dosage of this second admixture is 3 * 10 ¹³Dose/cm ²To 5 * 10 ¹⁵Dose/cm ²Between.

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