CN100388490C - Thin film transistor array substrate and method of manufacturing the same - Google Patents

Abstract

A thin film transistor array substrate and a method of manufacturing the same, in which a light shielding layer is formed between leads of a peripheral circuit region while manufacturing thin film transistors in a pixel region. The light shielding layer is formed by a metal layer and is used for shielding a region where light leakage is possible between leads of the source/drain layer or the gate layer. In addition, a stable voltage can be applied to the shading layer to reduce signal interference among the leads, and whether the leads are short-circuited with the shading layer can be detected through the applied voltage while the thin film transistor array is electrically detected.

Description

Thin film transistor array substrate and manufacturing method thereof

technical field

The present invention relates to a display panel and its manufacturing method, and in particular to a thin film transistor array substrate and its manufacturing method.

Background technique

With the substantial progress of computer performance and the high development of Internet and multimedia technology, the transmission of image information has mostly changed from analog to digital transmission. In order to match the modern life pattern, the volume of video or image devices tends to be thinner and thinner day by day. The traditional cathode ray tube (Cathode Ray Tube, CRT) display has been monopolizing the display market in recent years because of its excellent display quality and economy. However, for the environment where individuals operate multiple terminals/display devices on the table, or from the perspective of environmental protection, if the trend of energy saving is predicted, there are still many problems in the space utilization and energy consumption of cathode ray tubes. However, there is no effective solution to the requirements of lightness, thinness, shortness, smallness and low power consumption.

Therefore, in recent years, with the maturity of optoelectronic technology and semiconductor manufacturing technology, it has also led to the vigorous development of flat panel display (Flat Panel Display), in which liquid crystal display (Liquid Crystal Display, LCD) is based on its low voltage operation, no radiation scattering, The advantages of light weight and small size have gradually replaced traditional cathode ray tube displays and become the mainstream of display products in recent years.

Please refer to FIG. 1 , which is a schematic cross-sectional view of a known liquid crystal display module. In order to simplify the illustration, FIG. 1 only illustrates the required components. The LCD module at least includes a TFT array substrate 110 , a color filter film substrate 120 , a black matrix layer 122 , a sealant 130 , a liquid crystal layer 140 , polarizers 152 , 154 and a frame 160 . Wherein, the black matrix layer 122 is arranged on the color filter film substrate 120, the sealant 130 is arranged between the color filter film substrate 120 and the TFT array substrate 110, and the liquid crystal layer 140 is arranged between the color filter film substrate 120 and the thin film transistor array substrate 110. In the enclosed space formed by the transistor array substrate 110 and the sealant 130 . In addition, the polarizers 152 and 154 are respectively disposed on the other surfaces of the TFT array substrate 110 and the color filter film substrate 120 without the liquid crystal layer 140 , and the outer frame 160 is disposed on the polarizer 152 . In addition, the thin film transistor array substrate 110 can be divided into a pixel area 110a and a peripheral circuit area 110b, wherein a plurality of leads 112 are arranged in the peripheral circuit area 110b for the operation of the display.

Following the above, the known method of forming the liquid crystal layer 140 is to first enclose a closed area between the thin film transistor array substrate 110 and the color filter film substrate 120 with the sealant 130, and then use the capillary principle to slowly seal the liquid crystal layer 140 through the external atmosphere. The liquid crystal is injected into the enclosed area surrounded by the TFT array substrate 110 and the color filter film substrate 120 . Since this injection process is time-consuming, in order to meet the mass production requirements of large-size LCD panels in the future, a liquid crystal drop filling (One DropFill, ODF) technology has also been proposed recently. The so-called liquid crystal dripping technique is to first form the sealant 130 on the thin film transistor array substrate 110 or the color filter film substrate 120, then drop the liquid crystal into the area surrounded by the sealant 130, and then place the thin film transistor array substrate 110 and the The color filter film substrate 120 is bonded together, and the sealant 130 is hardened by irradiation of ultraviolet light to bond the two substrates.

It is worth mentioning that it is known that in order to make the sealant 130 uniformly exposed to ultraviolet radiation, so as to avoid contamination of part of the liquid crystal 140 due to incomplete curing of the sealant 130, the black matrix layer on the color filter film substrate 110 is usually 122 retracts a certain distance towards the center of the panel. However, due to the shrinkage of the black matrix layer 122, a possible light leakage area 170 is generated between the black matrix layer 122 and the sealant 130, and because there is no light-shielding barrier between the leads 112 in the peripheral circuit area 110b, so The light 180 emitted by the backlight module may pass through the gaps between the lead wires 112 , and problems such as front view light leakage or side view light leakage may occur at the junction of the outer frame 160 and the TFT array substrate 110 .

Contents of the invention

In view of this, the purpose of the present invention is to provide a thin film transistor array substrate and its manufacturing method, so as to solve the problem of light leakage caused by the peripheral circuit area.

Based on the above purpose, the present invention proposes a thin film transistor array substrate, which has a pixel region and a peripheral circuit region located on the periphery of the pixel region. The thin film transistor array substrate includes, for example, a transparent substrate, a thin film transistor array, a plurality of first leads, a plurality of a second lead wire and the first light-shielding layer. Wherein, the thin film transistor array is arranged on the transparent substrate in the pixel area, and the thin film transistor array at least includes a first conductive layer and a second conductive layer. In addition, the first lead is arranged on the transparent substrate in the peripheral circuit area, and the first lead and the first conductive layer are the same film layer, while the second lead is arranged on the transparent substrate in the peripheral circuit area, and the second lead and the first conductive layer are the same film layer. The second conductive layer is the same film layer. In addition, the first light-shielding layer is located on the transparent substrate in the peripheral circuit area, wherein the first light-shielding layer is arranged corresponding to the gap between adjacent first leads, and the first light-shielding layer and the second conductive layer are the same film layer.

Based on the above purpose, the present invention also proposes a method for manufacturing a thin film transistor array substrate. First, a transparent substrate is provided, and the transparent substrate has a pixel area and a peripheral circuit area. Next, a patterned gate layer is formed in the pixel region, and a plurality of first leads and a plurality of first welding pads connected to the first leads are formed in the peripheral line region at the same time. Then, an insulating layer is formed on the transparent substrate, so that the insulating layer covers the gate layer and the first lead. Next, a patterned channel layer is formed on the insulating layer above the gate layer. Afterwards, a patterned source/drain layer is formed on the channel layer, and at the same time a plurality of second leads and a plurality of second pads connected to the second leads are formed in the peripheral wiring area, wherein the source/drain is formed At the same time as the electrode layer, it also includes forming a first light-shielding layer above the gap between the adjacent first lead wires.

Based on the above purpose, the present invention also proposes another manufacturing method of a thin film transistor array substrate. First, a transparent substrate is provided, and the transparent substrate has a pixel area and a peripheral circuit area. Next, a patterned gate layer is formed in the pixel region, and a plurality of first leads and a plurality of first welding pads connected to the first leads are formed in the peripheral line region at the same time. Then, an insulating layer is formed on the transparent substrate, so that the insulating layer covers the gate layer and the first lead. Next, a patterned channel layer is formed on the insulating layer above the gate layer. After that, a patterned source/drain layer is formed on the channel layer, and a plurality of second leads and a plurality of second welding pads connected to the second leads are formed in the peripheral circuit area at the same time. Wherein, while forming the gate layer, it also includes forming a light-shielding layer under the predetermined gap between adjacent second lead wires.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a known liquid crystal display module.

2 and 3 are respectively a schematic top view and a partial cross-sectional view of a thin film transistor array substrate of the present invention.

FIG. 4 is an enlarged partial cross-sectional view of the gate wiring.

FIG. 5 is an enlarged partial cross-sectional view of the source wiring.

6 and 7 are schematic top views of the first pad and the second pad, respectively, according to another embodiment of the present invention.

8A to 8E are sequential schematic diagrams of the manufacturing process of the thin film transistor array substrate of the present invention.

Description of main component marking

110: TFT array substrate

110a: pixel area

110b: Peripheral line area

112: lead

120: Color filter film substrate

122: Black matrix layer

130: sealant

140: liquid crystal layer

152, 154: Polarizing plate

160: outer frame

170: Areas where light may leak

180: light

202: Transparent substrate

210: thin film transistor array substrate

210a: pixel area

210b: Peripheral Line Area

212: thin film transistor array

214: gate layer

216: insulation layer

218: Channel layer

220: Source/drain layer

222: protective layer

232: Gate wiring

232a: first pad

234: Source wiring

234a: second pad

242: The first shading layer

244: second light-shielding layer

Detailed ways

Please refer to FIGS. 2 and 3 . FIGS. 2 and 3 are respectively a schematic top view and a partial cross-sectional view of a thin film transistor array substrate of the present invention. The thin film transistor array substrate 210 can be divided into, for example, a pixel area 210a and a peripheral line area 210b located on the periphery of the pixel area 210a, wherein the transparent substrate 202 in the pixel area 210a is provided with a thin film transistor array 212 composed of a plurality of thin film transistors and pixel electrodes, for example. (not shown in the figure), and the transparent substrate 202 in the peripheral circuit area 210 b is provided with a plurality of leads connected to the thin film transistor array, which may be gate wiring 232 or source wiring 234 , for example. In addition, the ends of the gate wiring 232 and the source wiring 234 are respectively connected to a plurality of first pads 232 a and a plurality of second pads 234 a for bonding with external circuits. In addition, as shown in FIG. 3 , the thin film transistor array 212 includes, for example, a gate layer 214, an insulating layer 216, a channel layer 218, a source/drain layer 220, and a protective layer 222, among which the gate in the peripheral circuit region 210b The pole wiring 232 is the same film layer as the gate layer 214 .

As shown in FIG. 3 , in order to avoid light leakage between the gate wirings 232 in the present invention, a patterned first light-shielding layer 242 is formed above the gate wirings 232 , wherein the first light-shielding layer 242 covers at least the phase The gap between adjacent gate wirings 232, and the first light-shielding layer 242 can be formed simultaneously with the source/drain layer 220, for example, its detailed structure please refer to the local part of the gate wiring 232 shown in FIG. Enlarged cross-section. Similarly, in the present invention, a light-shielding layer can also be formed at the source wiring 234, please refer to the partial cross-sectional enlarged view of the source wiring 234 shown in FIG. Below the source wires 234 , it is disposed corresponding to the thinning between adjacent source wires 234 , and the second light-shielding layer 244 can be formed simultaneously with the gate layer 214 , for example.

Based on the above, the TFT array substrate 210 of the present invention can shield the gap between the adjacent gate wiring 232 or the adjacent source wiring 234 through the first light-shielding layer 242 and the second light-shielding layer 244, wherein the present invention can be used in While forming the thin film transistor array 212, the first light-shielding layer 242 and the second light-shielding layer 244 are patterned, so that the first light-shielding layer 242 and the second light-shielding layer 244 only correspond to adjacent gate wirings 232 or adjacent source lines. The gap setting of the pole wiring 234 . Therefore, compared with other designs in which the light-shielding layer fully covers the lead wires, the present invention can greatly reduce the phenomenon of resistance-capacitance hysteresis (RCdelay). Of course, under consideration of possible errors caused by the actual manufacturing process, the light shielding layer (the first light shielding layer 242 and the second light shielding layer 244) and the light leakage region (the adjacent gate wiring 232 and the adjacent source wiring 234 gap) partially overlap.

In another embodiment of the present invention, the above-mentioned first light-shielding layer 242 and second light-shielding layer 244 can also extend to the first pad 232a and the second pad 234a respectively, so as to avoid possible side-view light leakage. question. Please refer to FIGS. 6 and 7 . FIGS. 6 and 7 respectively show schematic top views of the first pad and the second pad according to another embodiment of the present invention. As shown in FIG. 6 , the first light shielding layer 242 extends to cover the gap between the adjacent first pads 232 a in addition to the gap between the adjacent gate lines 232 . In addition, as shown in FIG. 7 , the second light shielding layer 244 extends to cover the gap between the adjacent second pads 234 a in addition to the gap between the adjacent source wirings 234 .

In addition, according to the features of the present invention, the present invention can also provide a stable voltage to the above-mentioned first light-shielding layer 242 and second light-shielding layer 244 through the external pads, so that the gap between the leads (gate wiring 232) can be effectively improved. Or the mutual interference of the source wiring 234) leads to the problem of poor display image quality. In addition, by applying the voltage, it is also helpful to check whether there is a short circuit between the lead wire and the light-shielding layer when the thin film transistor array is electrically detected.

In order to describe the features of the present invention in detail, the following describes the method for manufacturing the above-mentioned thin film transistor array substrate 210 . Please refer to FIGS. 8A-8E , which are schematic diagrams sequentially showing the manufacturing process of the thin film transistor array substrate of the present invention.

First, as shown in 8A, a transparent substrate 202 is provided, wherein the transparent substrate 202 has a pixel area 212a and a peripheral circuit 212b, and the transparent substrate 202 is, for example, a glass substrate or a plastic substrate.

Next, as shown in FIG. 8B, a metal layer (not shown) is formed in the pixel region 212a, and the metal layer is patterned to define a patterned gate layer 214 in the pixel region 212a, and in the peripheral circuit region 212b defines a plurality of gate wirings 232 and a plurality of first pads (not shown) connected to the gate wirings 232 . Wherein, the method for forming the metal layer is, for example, a sputtering method.

Next, as shown in FIG. 8C , an insulating layer 216 is formed on the transparent substrate 202 so that the insulating layer 216 covers the gate layer 214 and the gate wiring 232 . Wherein, the method of forming the insulating layer 216 is, for example, depositing a silicon nitride layer or a silicon oxide layer by plasma chemical vapor deposition.

Then, as shown in FIG. 8D , a channel material layer (not shown) is formed on the insulating layer 216 , and the channel material layer is patterned to define a channel layer 218 on the insulating layer 216 above the gate 212 . Wherein, the material of the channel layer 218 is, for example, amorphous silicon (a-Si).

Afterwards, as shown in FIG. 8E, another metal layer (not shown) is formed on the transparent substrate 202, and the metal layer is patterned to define a patterned source/drain layer in the pixel region 212a. 220, and define a plurality of source wirings 234 and a plurality of second bonding pads (not shown in the figure) connected to the source wirings 234 in the peripheral wiring area 212b. In addition, the present invention also defines a first light-shielding layer 242 above the gap between adjacent gate wirings 232 , and according to the features of the present invention, the first light-shielding layer 242 can also extend to cover the gap between adjacent first pads.

Of course, forming other film layers such as the protective layer 222 (as shown in FIG. 3 ), the electrode film (not shown in the figure) and the alignment film (not shown in the figure) are also included on the substrate 202, but the related manufacturing process It is well known to those skilled in the art, and the present invention will not be described in detail here.

Based on the above, in an embodiment of the present invention, the second light-shielding layer 244 (as shown in FIGS. 5 and 7 ) can also be defined while forming the gate layer 214, wherein the formed second light-shielding layer 244 corresponds to the predetermined gap below the adjacent source wiring 234 , and according to the features of the present invention, the second light-shielding layer 244 can also extend to cover the predetermined gap between the adjacent second bonding pads 242 .

To sum up, the thin film transistor array substrate and its manufacturing method of the present invention form a light-shielding layer in the region where light leakage may occur in the peripheral circuit area while manufacturing the thin-film transistor, and the light-shielding layer formed at the same time as the gate layer can be used to shield The light leakage between the source wiring and its bonding pad, and the light-shielding layer formed simultaneously with the source/drain layer can be used to shield the light leakage between the gate wiring and its bonding pad. Of course, within the scope of not departing from the idea of the present invention, the thin film transistor array substrate and its manufacturing method of the present invention can also be placed only at one of the gate wiring or source wiring, or where light leakage is more likely to occur. Part of the peripheral circuit area forms a light-shielding layer to save manufacturing cost and process time. It is worth mentioning that although the light-shielding layer in the above embodiments is formed at the same time as the gate layer or the source/drain layer of the thin film transistor, the light-shielding layer of the present invention can also be formed with The gate layer or the source/drain layer is fabricated separately, and the material of the light-shielding layer can be black resin or other materials with light-shielding effect besides metal.

The thin film transistor array substrate and its manufacturing method of the present invention have at least the following features and advantages:

(1) The light-shielding layer is patterned to reduce the overlapping area between the light-shielding layer and the leads, thereby effectively reducing the RC delay between the light-shielding layer and the leads.

(2) The light-shielding layer can extend to between the pads, so it also helps to improve the problem of side-view light leakage.

(3) A stable voltage can be applied to the light-shielding layer to reduce the signal interference between the lead wires, thus contributing to the improvement of display quality.

(4) There is an external stable voltage on the light-shielding layer, so when the thin-film transistor array performs electrical detection, it can simultaneously detect whether there is a short circuit between the lead wire and the light-shielding layer.

(5) The light-shielding layer is formed simultaneously in the manufacturing process of the thin film transistor array, so there is no need to add additional manufacturing process steps, which can effectively save process cost and time.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any ordinary person in the technical field to which the invention belongs can make some changes and modifications without departing from the spirit and scope of the present invention. improvement, so the scope of protection of the present invention should be defined by the claims.

Claims (16)

1. A thin film transistor array substrate, characterized in that it has a pixel area and a peripheral circuit area positioned at the periphery of the pixel area, and the thin film transistor array substrate comprises: transparent substrate; a thin film transistor array, disposed on the transparent substrate in the pixel area, and the thin film transistor array includes at least a first conductive layer and a second conductive layer; A plurality of first leads are arranged on the transparent substrate in the peripheral circuit area, and these first leads and the first conductive layer are the same film layer; A plurality of second leads are arranged on the transparent substrate in the peripheral circuit area, and these second leads are the same film layer as the second conductive layer; The first light-shielding layer is located on the transparent substrate in the peripheral circuit area, the first light-shielding layer is arranged corresponding to the gap between the adjacent first leads, and the first light-shielding layer and the second conductive layer are the same film layer, wherein the first light-shielding layer is applied with a first stable voltage; and A second light-shielding layer, the second light-shielding layer is located on the transparent substrate in the peripheral circuit area, and is arranged corresponding to the gap between the adjacent second leads, and the second light-shielding layer is the same as the first conductive layer The film layer, wherein the second light-shielding layer is applied with a second stable voltage. 2. The TFT array substrate according to claim 1, wherein the first conductive layer is a gate layer, and the second conductive layer is a source/drain layer. 3. The TFT array substrate according to claim 1, wherein the first conductive layer is a source/drain layer, and the second conductive layer is a gate layer. 4. A thin film transistor array substrate, characterized in that it has a pixel area and a peripheral line area positioned at the periphery of the pixel area, and the thin film transistor array substrate comprises: transparent substrate; a thin film transistor array, disposed on the transparent substrate in the pixel area, and the thin film transistor array includes at least a first conductive layer and a second conductive layer; A plurality of first leads are arranged on the transparent substrate in the peripheral circuit area, and these first leads and the first conductive layer are the same film layer; A plurality of first pads are arranged on the transparent substrate in the peripheral circuit area and connected to the first leads, and the first pads are the same film layer as the first conductive layer; A plurality of second leads are arranged on the transparent substrate in the peripheral circuit area, and these second leads are the same film layer as the second conductive layer; A plurality of second pads are arranged on the transparent substrate in the peripheral circuit area and connected to the second leads, and the second pads are the same film layer as the second conductive layer; and The first light-shielding layer is located on the transparent substrate in the peripheral circuit area, the first light-shielding layer is arranged corresponding to the gap between the adjacent first leads and the adjacent first pads, and the first light-shielding layer and the adjacent first pads The second conductive layer is the same film layer. 5. The thin film transistor array substrate according to claim 4, further comprising a second light-shielding layer, the second light-shielding layer is located on the transparent substrate in the peripheral circuit area, and corresponds to the adjacent second leads and The gaps between the adjacent second pads are arranged, and the second light-shielding layer and the first conductive layer are the same film layer. 6. The thin film transistor array substrate according to claim 5, wherein a stable voltage is applied to the first light-shielding layer. 7. The thin film transistor array substrate according to claim 6, wherein a stable voltage is applied to the second light-shielding layer. 8. The TFT array substrate according to claim 4, wherein a stable voltage is applied to the first light-shielding layer. 9. The thin film transistor array substrate according to claim 4, wherein the first conductive layer is a gate layer, and the second conductive layer is a source/drain layer. 10. The TFT array substrate according to claim 4, wherein the first conductive layer is a source/drain layer, and the second conductive layer is a gate layer. 11. A method for manufacturing a thin film transistor array substrate, characterized by comprising: providing a transparent substrate, and the transparent substrate has a pixel area and a peripheral circuit area; forming a patterned gate layer in the pixel region, and simultaneously forming a plurality of first leads and a plurality of first pads connected to the first leads in the peripheral circuit region; forming an insulating layer on the transparent substrate, so that the insulating layer covers the gate layer and the first leads; forming a patterned channel layer on the insulating layer above the gate layer; and forming a patterned source/drain layer on the channel layer, and simultaneously forming a plurality of second leads and a plurality of second pads connected to the second leads in the peripheral circuit area, Wherein, while forming the source/drain layer, it also includes forming a first light-shielding layer above the gaps between the adjacent first leads. 12 . The method for manufacturing a thin film transistor array substrate according to claim 11 , further comprising extending the first light shielding layer above the gap between the adjacent first pads when forming the first light shielding layer. 13 . 13 . The method for manufacturing a TFT array substrate according to claim 11 , further comprising forming a second light-shielding layer under the predetermined gaps adjacent to the second lead wires when forming the gate layer. 14 . 14. The method for manufacturing a thin film transistor array substrate according to claim 13, characterized in that when forming the second light-shielding layer, it further comprises extending the second light-shielding layer to the predetermined adjacent second bonding pads. Below the gap. 15. A method for manufacturing a thin film transistor array substrate, characterized by comprising: providing a transparent substrate, and the transparent substrate has a pixel area and a peripheral circuit area; forming a patterned gate layer in the pixel area, and simultaneously forming a plurality of first leads and a plurality of first pads connected to the first leads in the peripheral line area; forming an insulating layer on the transparent substrate, so that the insulating layer covers the gate layer and the first leads; forming a patterned channel layer on the insulating layer above the gate layer; and forming a patterned source/drain layer on the channel layer, and simultaneously forming a plurality of second leads and a plurality of second pads connected to the second leads in the peripheral circuit area, Wherein, while forming the gate layer, it also includes forming a light-shielding layer under the predetermined gaps adjacent to the second leads. 16 . The method for manufacturing a thin film transistor array substrate according to claim 15 , further comprising extending the light shielding layer below the predetermined gaps adjacent to the second pads when forming the light shielding layer. 17 .

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