CN100377334C - Word line structure of split gate flash memory unit and manufacturing method thereof - Google Patents

Abstract

A word line structure of a split gate flash memory cell and a manufacturing method thereof. The method first provides a gate structure of a split gate flash memory cell, wherein a material layer of a word line is formed on the gate structure. A covering layer is then formed on the word line material layer. Next, a chemical mechanical polishing (CMP) technique is used to remove part of the covering layer and part of the word line material layer. After an oxide layer is formed on the surface of the exposed word line material layer, the remaining covering layer and the word line material layer below are removed, thereby forming a box-shaped word line of the split gate flash memory cell.

Description

Word line structure of split gate flash memory unit and manufacturing method thereof

technical field

The present invention relates to a split gate flash memory unit (Split Gate Flash Memory Cell) word line (Word Line) and its manufacturing method, in particular to a chemical mechanical polishing (CMP) technology to manufacture split gate flash The method of the square (Box-shape) word line of the memory unit.

Background technique

Among the flash memory devices, compared with the stacked gate flash memory device, the split gate flash memory device is not only smaller in size, but also saves more power. Therefore, split-gate flash memory has become a very popular storage device at present. In the split gate flash memory, polysilicon spacers are usually used as word lines to reduce the size of the split gate flash memory.

Please refer to FIG. 1 to FIG. 7 . FIG. 1 to FIG. 7 are process cross-sectional views of word lines of conventional split-gate flash memory cells. Firstly, an oxide layer 102 , a polysilicon layer 104 and a nitride layer 106 are sequentially stacked on a semiconductor substrate 100 . Wherein, the oxide layer 102 and the polysilicon layer 104 are used to make a material layer of a floating gate (Floating Gate). The nitride layer 106 and the polysilicon layer 104 are defined by lithography and etching processes, and part of the nitride layer 106 and part of the polysilicon layer 104 are removed to form an opening 108 to provide a region for forming part of the memory gate device. Wherein, the opening 108 does not expose the oxide layer 102 , and the sidewall of the opening 108 in the region of the polysilicon layer 104 is inclined to form a groove-like structure, as shown in FIG. 1 .

After the opening 108 is formed, silicon nitride spacers 109 are formed on the sidewalls of the opening 108 by means of deposition and etch-back. Then, the silicon oxide spacer 110 is formed on the silicon nitride spacer 109 in the opening 108 by means of deposition and etching back, and the formed structure is shown in FIG. 2 . After the silicon oxide spacer 110 is completed, the polysilicon layer 104 exposed in the opening 108 is removed by lithography and etching processes, thereby exposing a portion of the oxide layer 102 . Next, a silicon oxide spacer 114 is formed, and at the same time, the oxide layer 102 exposed in the opening is removed, thereby exposing a portion of the substrate 100 . At this time, an ion implantation step is performed on the substrate 100 exposed in the opening 108 , so as to form the source electrode 112 in the substrate 100 , as shown in FIG. 3 .

After the source electrode 112 is formed, a polysilicon layer 116 is filled in the opening 108 by deposition, wherein the polysilicon layer 116 covers the exposed substrate 100, the silicon oxide spacer 114 and part of the silicon oxide spacer 110, and contact with source 112 . Next, the excess polysilicon layer 116 is removed by etching back again, leaving only the polysilicon layer 116 in the opening 108 and exposing part of the silicon oxide spacers 110 . At this point, the internal connection implantation of the source 112 of the flash memory has been completed. After that, the surface of the polysilicon layer 116 is oxidized by thermal oxidation, so as to form an oxide layer 118 on the surface of the polysilicon layer 116 . After the oxide layer 118 is formed, the rest of the nitride layer 106, part of the polysilicon layer 104, part of the oxide layer 102 and the silicon nitride spacer 109 are removed, thereby forming the gate structure 120 of the split-gate flash memory unit, as Figure 4 shows.

Then, an oxide layer 122 is formed to cover the gate structure 120 and the substrate 100 by deposition, and then a polysilicon layer 124 is formed to cover the oxide layer 122 by deposition, thereby forming the structure shown in FIG. 5 . Next, an oxide layer 126 is covered on the polysilicon layer 124, wherein the oxide layer 126 is used as a sacrificial mask for subsequent spacer etching, and the formed structure is shown in FIG. 6 .

At this point, the word line of the split-gate flash memory element can be fabricated, and a breakthrough (BreakThrough) etching step is first performed to remove part of the oxide layer 126, but there is still part of the oxide layer 126 remaining on the side of the polysilicon layer 124. next to the wall. An etch-back step is then performed to remove part of the oxide layer 126 and part of the polysilicon layer 124 to form a polysilicon spacer 128 next to the gate structure 120 . Wherein, the formed polysilicon spacer 128 is the word line of the split-gate flash memory unit 130 . Due to the interaction between the structure of the gate structure 120 and the oxide layer 126 and the etch back, a recessed region 132 is formed on the surface of the formed polysilicon spacer 128 , thereby forming a fence structure 134 on the polysilicon spacer 128 .

When the above-mentioned prior art utilizes the etching method to manufacture word lines of split gate flash memory cells, not only is it difficult to effectively control the key dimensions of the memory cells, but also the spacers of the word lines cannot form a better square structure. A fence-like structure is formed on the wall, which seriously affects the electrical quality and process reliability of the memory unit.

Contents of the invention

Therefore the object of the present invention is to provide a kind of manufacturing method of the word line of split gate flash memory cell, and it is after the word line material layer is formed, forms cover layer on this word line material layer, utilizes chemical mechanical polishing technology again The word line material layer is flattened, and then the word line with a square structure can be obtained.

Another object of the present invention is to provide a method for manufacturing a split gate flash memory unit, by adjusting the parameters of the chemical mechanical polishing process, the mechanical stress of chemical mechanical polishing is improved, and the covering on the word line material layer is supplemented In this way, not only the word line material layer covering the gate structure can be smoothly planarized, but also the redundant word line material layer can be removed, so as to manufacture the word line with square structure.

According to the above objectives of the present invention, a method for manufacturing word lines of split gate flash memory cells is proposed.

According to a preferred embodiment of the present invention, the manufacturing method of the word line of the split-gate flash memory unit of the present invention at least includes the following steps: first, a substrate is provided, wherein a gate of the split-gate flash memory unit The structure has been formed on part of the base material, and the sidewall of the gate structure includes at least one spacer, wherein the material of the spacer can be silicon oxide. A dielectric layer is formed on the above-mentioned gate structure and substrate, and the material of the dielectric layer can be silicon oxide. Next, a conductive layer is formed on the above-mentioned dielectric layer, and the material of the conductive layer is preferably polysilicon. After the conductive layer is formed, a cover layer is formed on the conductive layer, wherein the material of the cover layer is preferably silicon nitride. Then, a planarization step is performed by means of chemical mechanical polishing until the above-mentioned spacers are exposed. At this time, the remaining cover layer and the conductive layer under the cover layer after the planarization step are removed, that is, the word line of the square structure of the split-gate flash memory unit is completed.

According to the above object of the present invention, a word line structure of a split gate flash memory unit is proposed, at least including: a gate structure of the split gate flash memory unit is located on a substrate; and a square spacer is located on the above-mentioned on one side wall of the gate structure.

By increasing the mechanical stress of the chemical mechanical polishing process and properly adjusting the thickness of the covering layer, a word line structure with vertical sidewalls can be obtained quite easily, and the critical dimensions of the memory element can also be effectively controlled. Furthermore, after the word line material layer is planarized, the remaining word line material layer has a flat surface, so no fence-like structure will be formed on the word line. In this way, not only the electrical quality of the storage element can be greatly improved, but also the process yield can be improved.

The word line of the split-gate flash memory unit disclosed by the present invention and its manufacturing method can not only effectively control the key size of the memory unit, but also smoothly form the word line with a square structure.

Description of drawings

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

In the attached picture,

1 to 7 are process cross-sectional views of word lines of existing split-gate flash memory cells;

8 to 15 are process cross-sectional views of a word line of a split-gate flash memory cell according to a preferred embodiment of the present invention.

Detailed ways

In order to make the description of the present invention more detailed and complete, please refer to FIG. 8 to FIG. 15 . FIG. 8 to FIG. 15 are process cross-sectional views of a word line of a split-gate flash memory cell according to a preferred embodiment of the present invention. Firstly, a gate dielectric layer 202 is formed on the semiconductor substrate 200 by thermal oxidation, wherein the material of the gate dielectric layer 202 can be, for example, silicon oxide. The conductive layer 204 is then formed by chemical vapor deposition (CVD), wherein the material of the conductive layer 204 is preferably polysilicon. The above-mentioned gate dielectric layer 202 and conductive layer 204 are material layers for making the floating gate. Next, a nitride layer 206 is formed to cover the conductive layer 204 by means of, for example, chemical vapor deposition. After the nitride layer 206 is formed, a defined step is performed by using, for example, lithography and etching processes to remove part of the nitride layer 206 and part of the conductive layer 204, but the gate dielectric layer 202 is not exposed, so that the An opening 208 is formed in layer 206 and conductive layer 204 . The opening 208 is used to provide a region for forming part of the memory gate element, and the sidewall of the opening 208 in the region of the conductive layer 204 is inclined, as shown in FIG. 8 .

After the opening 208 is formed, a dielectric film (only the spacer 210 is shown) is conformally deposited on the nitride layer 206 and the conductive layer 204 exposed by the opening 208, wherein the dielectric film The material can be, for example, silicon nitride. Part of the dielectric film is then removed by, for example, etching back, so as to form a spacer 210 on the sidewall of the opening 208 . Next, using chemical vapor deposition, and using tetraethyloxysilane (TEOS) as a raw material, another dielectric film (only the spacer 212 is shown) is conformally deposited on the nitride layer 206, the gap wall 210 and the exposed conductive layer 204 . Wherein, the material of the another dielectric film may be, for example, silicon oxide. A part of the other dielectric film is then removed by etching back, so that a spacer 212 is formed on the spacer 210 in the opening 208 , as shown in FIG. 9 .

After the spacers 212 are formed, the conductive layer 204 exposed in the opening 208 is removed by using, for example, lithography and etching processes, so as to expose the underlying gate dielectric layer 202 . Next, a dielectric film (only the spacer 214 is shown) is conformally deposited by chemical vapor deposition to cover the gate dielectric layer 202 exposed in the nitride layer 206, the spacer 212 and the opening 208. superior. Wherein, the material of the dielectric film is preferably silicon oxide. Part of the dielectric film is removed by etching back, and the gate dielectric layer 202 exposed in the opening 208 is removed at the same time, so that a spacer 214 is formed on a part of the sidewall of the spacer 212, and part of the base is exposed. Material 200. At this time, an ion implantation step is performed on the substrate 200 exposed in the opening 208 , so as to form the source electrode 216 in the substrate 200 , and the formed structure is shown in FIG. 10 .

Then, a conductive material layer (only the conductive layer 218 is shown) is formed to cover the part of the spacer 212 , the spacer 214 and the substrate 200 exposed in the opening 208 by means of, for example, chemical vapor deposition. Wherein, the material of the conductive material layer is preferably polysilicon. Using, for example, an etch-back technique, part of the conductive layer 218 is removed, and only the conductive material layer in the opening 208 remains, so that the conductive layer 218 in contact with the source 216 is formed in the opening 208, so as to implant the source of the flash memory The internal wiring of pole 216. Wherein, the conductive layer 218 covers the exposed substrate 200 , the spacer 214 and part of the spacer 212 . After the conductive layer 218 is formed, the surface of the conductive layer 218 is oxidized by, for example, a thermal oxidation method, so as to form an oxide layer 220 on the surface of the conductive layer 218 . After the oxide layer 220 is formed on the surface of the conductive layer 218, the remaining nitride layer 206, part of the conductive layer 204, part of the gate dielectric layer 202 and the spacer 210 are removed, thereby forming the gate structure as shown in FIG. 11 222.

After the gate structure 222 is completed, a thin dielectric layer 224 is formed to cover the gate structure 222 and the substrate 200 by means of chemical vapor deposition, wherein the material of the dielectric layer 224 is preferably silicon oxide. A thick conductive layer 226 is then formed to cover the dielectric layer 224 by, for example, chemical vapor deposition, wherein the material of the conductive layer 226 is preferably polysilicon. Next, a capping layer 228 is formed on the conductive layer 226 by using, for example, chemical vapor deposition or low pressure chemical vapor deposition (LPCVD) to facilitate subsequent planarization steps. The formed structure is shown in FIG. 12 . Wherein, the material of the covering layer 228 is preferably silicon nitride, and the thickness of the covering layer 228 is preferably controlled between 600 Ȧ and 1800 Ȧ.

After the capping layer 228 is formed, the structure of FIG. 12 is planarized by using, for example, a chemical mechanical polishing process until the spacers 212 are exposed. In the above-mentioned planarization step, part of the cover layer 228 , part of the conductive layer 226 , part of the dielectric layer 224 and some spacers 212 are removed to form the structure shown in FIG. 13 . Wherein, there may still be a part of the dielectric layer 224 remaining on the oxide layer 220 . When carrying out the above-mentioned chemical mechanical polishing process, it is preferable to use a hard polishing pad, and it is preferable to control the down force (Down Force) between 2 pounds per square inch (psi) to 5 pounds per square inch (psi) ), and the rotation rate of the grinding platform is controlled between 50 revolutions per minute (rpm) to 100 revolutions per minute (rpm), and the rotation rate of the grinding head is controlled between 50 rpm to 100 rpm.

A feature of the present invention is to increase the mechanical stress of the chemical mechanical polishing by controlling the process parameters of the chemical mechanical polishing process, thereby effectively adjusting the polishing rate of the polishing structure with different patterns (such as the structure shown in FIG. 12 ). Combined with a covering layer 228 of appropriate thickness, the conductive layer 226 with a flat surface can be smoothly formed next to the gate structure 222 to facilitate subsequent fabrication of square word lines.

Next, a step such as heat treatment is performed to form an oxide layer 230 on the exposed surface of the conductive layer 226 to form the structure shown in FIG. 14 . Wherein, the thickness of the oxide layer 230 is preferably controlled to be greater than 200 Ȧ. In addition, the material of the cap layer 228 must be selected such that its etch rate is different from the etch rate of the oxide layer 230 . In this way, after the oxide layer 230 is formed, the remaining cover layer 228 and the conductive layer 226 under the cover layer 228 can be removed by using, for example, an etching method and utilizing the difference in etching rates between the oxide layer 230 and the cover layer 228 . Therefore, a spacer 232 having a square structure can be formed beside the sidewall of the gate structure 222 as a word line separating the gate flash memory unit 234 . Wherein, the etching technique used to remove the remaining covering layer 228 and the conductive layer 226 under the covering layer 228 is preferably anisotropic etching.

It can be seen from the above preferred embodiments of the present invention that by adjusting the process parameters of the planarization step and matching with an additional covering layer, a word line structure with a flat surface can be provided. Therefore, the application of the present invention can avoid the fence-like structure on the edge of the word line, thereby preventing electrical short circuit and particle pollution caused by the collapse of the fence-like structure on the edge of the word line, and achieving the goal of improving the process qualification rate and product reliability. Purpose.

From the above preferred embodiments of the present invention, it can be known that, compared with the conventional etching technology used to make word lines, the application of the present invention can not only easily obtain a word line structure with vertical sidewalls, but also smoothly obtain a square structure. character line. Therefore, the critical dimension of the split gate flash memory cell can be easily controlled, and the process reliability is higher.

It can be understood that, for those of ordinary skill in the art, various other corresponding changes and modifications can be made according to the technical scheme and technical concept of the present invention, and all these changes and modifications should belong to the appended rights of the present invention. the scope of protection required.

Claims (15)

1. A method for manufacturing a word line separating gate flash memory cells, characterized in that it at least includes: A substrate is provided, wherein at least a gate structure of the split-gate flash memory unit has been formed on part of the substrate, and the sidewall of the gate structure includes at least one spacer; forming a dielectric layer on the gate structure and the substrate; forming a conductive layer on the dielectric layer; forming a cover layer on the conductive layer; performing a planarization step until the spacer is exposed, and part of the conductive layer is exposed; forming an oxide layer on the exposed portion of the conductive layer, wherein the capping layer has an etch rate different from the etch rates of the spacer, the dielectric layer, and the oxide layer; and An etching step is performed to remove the remaining capping layer and the conductive layer under the capping layer by utilizing the characteristic that the etching rate of the capping layer is different from that of the spacer, the dielectric layer and the oxide layer. 2 . The method for manufacturing a word line of a split gate flash memory cell according to claim 1 , wherein the spacer is made of silicon oxide. 3 . 3. The method for manufacturing a word line of a split gate flash memory cell according to claim 1, wherein the material of the dielectric layer is silicon oxide. 4. The method for manufacturing a word line of a split-gate flash memory cell according to claim 1, wherein the material of the conductive layer is polysilicon. 5. The method for manufacturing a word line of a split gate flash memory cell according to claim 1, wherein the thickness of the covering layer is between 600 Ȧ and 1800 Ȧ. 6 . The method for manufacturing a word line of a split-gate flash memory cell according to claim 1 , wherein the covering layer is made of silicon nitride. 7 . 7. The method for manufacturing word lines of split gate flash memory cells according to claim 1, wherein the planarization step is a chemical mechanical polishing step. 8. The method for manufacturing word lines of split gate flash memory cells according to claim 7, wherein the chemical mechanical polishing step at least includes using a hard polishing pad. 9. The method of manufacturing a word line of a split-gate flash memory cell according to claim 7, wherein the chemical mechanical polishing step at least includes controlling a pressure between 2 lbs/square inch and 5 lbs/square between British hours. 10. The method for manufacturing word lines of split gate flash memory cells according to claim 7, wherein the chemical mechanical polishing step at least includes controlling the rotational speed of a polishing platform between 50 rpm and 100 rpm /min between. 11. The manufacturing method of the word line of the split-gate flash memory unit according to claim 7, wherein the chemical mechanical polishing step at least includes controlling the rotational speed of a polishing head between 50 revolutions per minute and 100 revolutions /min between. 12. The method for manufacturing the word line of the split gate flash memory cell according to claim 1, wherein the oxide layer is formed through a heat treatment reaction. 13. The method for manufacturing word lines of split gate flash memory cells according to claim 1, wherein the step of removing the conductive layer is an anisotropic etching method. 14. The method for manufacturing a word line of a split-gate flash memory cell according to claim 1, wherein the thickness of the oxide layer is greater than 200 Ȧ. 15. The method for manufacturing a word line of a split-gate flash memory cell according to claim 1, wherein the gate structure at least comprises: a source is located in the substrate; two gate oxide layers are on the substrate, and each of the gate oxide layers is on a portion of the source; Two first conductive films are respectively located on some of these gate oxide layers; Two first silicon oxide spacers are respectively located on the first conductive films; Two second silicon oxide spacers are respectively located on the other part of the gate oxide layer and the sidewalls of the first silicon oxide spacers; a second conductive film is located on another part of the source electrode, the first silicon oxide spacers and the second silicon oxide spacers; and An oxide film is located on the second conductive film.

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